[8(ߔti,omap3430-sdpti,omap3 +7TI OMAP3430 SDPchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000cpus+cpu@0arm,cortex-a8dcpupt{cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmupTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busph +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busp + pinmux@30 ti,omap3-padconfpinctrl-singlep08+pinmux_twl4030_pins2AFscm_conf@270sysconsimple-buspp0+ p0Fpbias_regulator@2b0ti,pbias-omap3ti,pbias-omappNpbias_mmc_omap2430Upbias_mmc_omap2430dw@|-Fclocks+mcbsp5_mux_fck@68ti,composite-mux-clocktphFmcbsp5_fckti,composite-clocktFmcbsp1_mux_fck@4ti,composite-mux-clocktpF mcbsp1_fckti,composite-clockt Fmcbsp2_mux_fck@4ti,composite-mux-clockt pF mcbsp2_fckti,composite-clockt Fmcbsp3_mux_fck@68ti,composite-mux-clockt phFmcbsp3_fckti,composite-clockt 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5Fdpll4_m5_ck@f40ti,divider-clockt?p@F2dpll4_m5x2_mul_ckti,fixed-factor-clockt2(5F3dpll4_m5x2_ck@d00ti,gate-clockt3p 5Fidpll4_m6_ck@1140ti,divider-clockt?p@F4dpll4_m6x2_mul_ckfixed-factor-clockt4F5dpll4_m6x2_ck@d00ti,gate-clockt5p F6emu_per_alwon_ckfixed-factor-clockt6Fbclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clockt%p pF8clkout2_src_mux_ck@d70ti,composite-mux-clockt%)7p pF9clkout2_src_ckti,composite-clockt89F:sys_clkout2@d70ti,divider-clockt:@p pHmpu_ckfixed-factor-clockt;F<arm_fck@924ti,divider-clockt<p $emu_mpu_alwon_ckfixed-factor-clockt<Fcl3_ick@a40ti,divider-clockt%p @F=l4_ick@a40ti,divider-clockt=p @F>rm_ick@c40ti,divider-clockt>p @gpt10_gate_fck@a00ti,composite-gate-clockt p F@gpt10_mux_fck@a40ti,composite-mux-clockt?p @FAgpt10_fckti,composite-clockt@Agpt11_gate_fck@a00ti,composite-gate-clockt p FBgpt11_mux_fck@a40ti,composite-mux-clockt?p @FCgpt11_fckti,composite-clocktBCcore_96m_fckfixed-factor-clocktDFmmchs2_fck@a00ti,wait-gate-clocktp Fmmchs1_fck@a00ti,wait-gate-clocktp Fi2c3_fck@a00ti,wait-gate-clocktp Fi2c2_fck@a00ti,wait-gate-clocktp Fi2c1_fck@a00ti,wait-gate-clocktp Fmcbsp5_gate_fck@a00ti,composite-gate-clockt p Fmcbsp1_gate_fck@a00ti,composite-gate-clockt p Fcore_48m_fckfixed-factor-clockt/FEmcspi4_fck@a00ti,wait-gate-clocktEp Fmcspi3_fck@a00ti,wait-gate-clocktEp Fmcspi2_fck@a00ti,wait-gate-clocktEp Fmcspi1_fck@a00ti,wait-gate-clocktEp Fuart2_fck@a00ti,wait-gate-clocktEp Fuart1_fck@a00ti,wait-gate-clocktEp  Fcore_12m_fckfixed-factor-clocktFFGhdq_fck@a00ti,wait-gate-clocktGp Fcore_l3_ickfixed-factor-clockt=FHsdrc_ick@a10ti,wait-gate-clocktHp Fgpmc_fckfixed-factor-clocktHcore_l4_ickfixed-factor-clockt>FImmchs2_ick@a10ti,omap3-interface-clocktIp Fmmchs1_ick@a10ti,omap3-interface-clocktIp Fhdq_ick@a10ti,omap3-interface-clocktIp Fmcspi4_ick@a10ti,omap3-interface-clocktIp Fmcspi3_ick@a10ti,omap3-interface-clocktIp Fmcspi2_ick@a10ti,omap3-interface-clocktIp Fmcspi1_ick@a10ti,omap3-interface-clocktIp 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pF[gpt8_mux_fck@1040ti,composite-mux-clockt?p@F\gpt8_fckti,composite-clockt[\gpt9_gate_fck@1000ti,composite-gate-clockt pF]gpt9_mux_fck@1040ti,composite-mux-clockt?p@F^gpt9_fckti,composite-clockt]^per_32k_alwon_fckfixed-factor-clockt?F_gpio6_dbck@1000ti,gate-clockt_pFgpio5_dbck@1000ti,gate-clockt_pFgpio4_dbck@1000ti,gate-clockt_pFgpio3_dbck@1000ti,gate-clockt_pFgpio2_dbck@1000ti,gate-clockt_p Fwdt3_fck@1000ti,wait-gate-clockt_p Fper_l4_ickfixed-factor-clockt>F`gpio6_ick@1010ti,omap3-interface-clockt`pFgpio5_ick@1010ti,omap3-interface-clockt`pFgpio4_ick@1010ti,omap3-interface-clockt`pFgpio3_ick@1010ti,omap3-interface-clockt`pFgpio2_ick@1010ti,omap3-interface-clockt`p Fwdt3_ick@1010ti,omap3-interface-clockt`p Fuart3_ick@1010ti,omap3-interface-clockt`p Fuart4_ick@1010ti,omap3-interface-clockt`pFgpt9_ick@1010ti,omap3-interface-clockt`p Fgpt8_ick@1010ti,omap3-interface-clockt`p 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sha11_ick@a14ti,omap3-interface-clockthp des1_ick@a14ti,omap3-interface-clockthp cam_mclk@f00ti,gate-clocktip5cam_ick@f10!ti,omap3-no-wait-interface-clockt>pFcsi2_96m_fck@f00ti,gate-clocktpFsecurity_l3_ickfixed-factor-clockt=Fjpka_ick@a14ti,omap3-interface-clocktjp icr_ick@a10ti,omap3-interface-clocktIp des2_ick@a10ti,omap3-interface-clocktIp mspro_ick@a10ti,omap3-interface-clocktIp mailboxes_ick@a10ti,omap3-interface-clocktIp ssi_l4_ickfixed-factor-clockt>Fqsr1_fck@c00ti,wait-gate-clocktp Fsr2_fck@c00ti,wait-gate-clocktp Fsr_l4_ickfixed-factor-clockt>dpll2_fck@40ti,divider-clockt%p@Fkdpll2_ck@4ti,omap3-dpll-clocktkp$@4^pxFldpll2_m2_ck@44ti,divider-clocktlpDFmiva2_ck@0ti,wait-gate-clocktmpFmodem_fck@a00ti,omap3-interface-clocktp Fsad2d_ick@a10ti,omap3-interface-clockt=p Fmad2d_ick@a18ti,omap3-interface-clockt=p Fmspro_fck@a00ti,wait-gate-clocktp ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clocktp Fnssi_ssr_div_fck_3430es2@a40ti,composite-divider-clocktp @$Fossi_ssr_fck_3430es2ti,composite-clocktnoFpssi_sst_fck_3430es2fixed-factor-clocktpFhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clocktHp Fssi_ick_3430es2@a10ti,omap3-ssi-interface-clocktqp Fusim_gate_fck@c00ti,composite-gate-clocktD p F|sys_d2_ckfixed-factor-clocktFsomap_96m_d2_fckfixed-factor-clocktDFtomap_96m_d4_fckfixed-factor-clocktDFuomap_96m_d8_fckfixed-factor-clocktDFvomap_96m_d10_fckfixed-factor-clocktD Fwdpll5_m2_d4_ckfixed-factor-clocktrFxdpll5_m2_d8_ckfixed-factor-clocktrFydpll5_m2_d16_ckfixed-factor-clocktrFzdpll5_m2_d20_ckfixed-factor-clocktrF{usim_mux_fck@c40ti,composite-mux-clock(tstuvwxyz{p @F}usim_fckti,composite-clockt|}usim_ick@c10ti,omap3-interface-clocktMp  Fdpll5_ck@d04ti,omap3-dpll-clocktp  $ L 4^pF~dpll5_m2_ck@d50ti,divider-clockt~p PFrsgx_gate_fck@b00ti,composite-gate-clockt%p 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyio-channelsio-channel-namesusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvqmmc-supplybus-widthstatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinslinux,mtd-namebank-widthgpmc,mux-add-datagpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenlabelti,nand-ecc-optnand-bus-widthgpmc,device-widthmultipointnum-epsram-bitsiommusti,phy-type#thermal-sensor-cellsti,sysc-maskpolling-delay-passivepolling-delaycoefficientsthermal-sensors