8( T*chipspark,popmetal-rk3288rockchip,rk3288&7PopMetal-RK3288aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5< Hcpu@501cpuarm,cortex-a12'@5Hcpu@502cpuarm,cortex-a12'@5Hcpu@503cpuarm,cortex-a12'@5Hcpu-opp-tableoperating-points-v2PHopp-126000000[b opp-216000000[ b opp-312000000[b opp-408000000[Qb opp-600000000[#Fb opp-696000000[)|b~opp-816000000[0,bB@opp-1008000000[<bopp-1200000000[Gbopp-1416000000[TfrbOopp-1512000000[ZJb opp-1608000000[_"bpamba simple-buspdma-controller@ff250000arm,pl330arm,primecell%@w5 apb_pclkHdma-controller@ff600000arm,pl330arm,primecell`@w5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@w5 apb_pclkH\reserved-memorypdma-unusable@fe000000oscillator fixed-clockn6xin24mH timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshc р 5Drvbiuciuciu-driveciu-sample  @#resetokay/9K\nydefault dwmmc@ff0d0000rockchip,rk3288-dw-mshc р 5Eswbiuciuciu-driveciu-sample ! @#reset disableddwmmc@ff0e0000rockchip,rk3288-dw-mshc р 5Ftxbiuciuciu-driveciu-sample "@#reset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshc р 5Guybiuciuciu-driveciu-sample #@#resetokay/9nydefaultsaradc@ff100000rockchip,saradc $ 5I[saradcapb_pclkW #saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk   txrx ,ydefault disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk  txrx -ydefault ! disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclk txrx .ydefault"#$% disabledi2c@ff140000rockchip,rk3288-i2c >i2c5Mydefault&okayak8963@dasahi-kasei,ak8975 &'ydefault(*5l3g4200d@69st,l3g4200d-gyro@i*Pmma8452@1d fsl,mma8452&'ydefault)i2c@ff150000rockchip,rk3288-i2c ?i2c5Oydefault*okayi2c@ff160000rockchip,rk3288-i2c @i2c5Pydefault+okayi2c@ff170000rockchip,rk3288-i2c Ai2c5Qydefault,okayHrserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7]g5MUbaudclkapb_pclkydefault-okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8]g5NVbaudclkapb_pclkydefault.okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9]g5OWbaudclkapb_pclkydefault/okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :]g5PXbaudclkapb_pclkydefault0okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;]g5QYbaudclkapb_pclkydefault1okaythermal-zonesreserve_thermalt2cpu_thermaltd2tripscpu_alert0ppassiveH3cpu_alert1$passiveH4cpu_crit_ criticalcooling-mapsmap03 map14 gpu_thermaltd2tripsgpu_alert0ppassiveH5gpu_crit_ criticalcooling-mapsmap05 tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk #tsadc-apbyinitdefaultsleep676sokay+H2ethernet@ff290000rockchip,rk3288-gmac)Fmacirqeth_wake_irqV885fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB #stmmacethokc9nrgmiiwinput : 'B@;ydefault<0usb@ff500000 generic-ehciP 5usbhost=usb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghost> usb2-phy disabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otgotg!0@@ ? usb2-phyokayusb@ff5c0000 generic-ehci\ 5usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5Lydefault@okaypmic@1brockchip,rk808&AydefaultBC?`xin32krk808-clkout2nDzDDDDDEDPregulatorsDCDC_REG1  q3pKvdd_armH regulator-state-memZDCDC_REG2  P3Kvdd_gpuregulator-state-memsB@DCDC_REG3 Kvcc_ddrregulator-state-memsDCDC_REG4 2Z32ZKvcc_ioHregulator-state-mems2ZLDO_REG1 2Z32ZKvcc_lanH9regulator-state-mems2ZLDO_REG2 w@32Z Kvccio_sdHregulator-state-memZLDO_REG3 B@3B@Kvdd_10regulator-state-memsB@LDO_REG4 w@3w@ Kvcc18_lcdregulator-state-memsw@LDO_REG5w@32ZKldo5LDO_REG6 B@3B@ Kvdd10_lcdregulator-state-memsB@LDO_REG7 w@3w@Kvcc_18HEregulator-state-memsw@LDO_REG8 2Z32ZKvcca_33HYregulator-state-mems2ZSWITCH_REG1  Kvccio_wlH[regulator-state-memsSWITCH_REG2 Kvcc_lcdregulator-state-memsi2c@ff660000rockchip,rk3288-i2cf =i2c5NydefaultFokaypwm@ff680000rockchip,rk3288-pwmhydefaultG5^pwm disabledpwm@ff680010rockchip,rk3288-pwmhydefaultH5^pwm disabledpwm@ff680020rockchip,rk3288-pwmh ydefaultI5^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0ydefaultJ5^pwm disabledbus_intmem@ff700000 mmio-srampppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsHpower-controller!rockchip,rk3288-power-controllerh H_pd_vio@9 5chgfdehilkj$KLMNOPQRSpd_hevc@11 5opTUpd_video@12 5Vpd_gpu@13 5WXreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvV8 Hjk$#gׄeрxhрxhHsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwH8edp-phyrockchip,rk3288-dp-phy5h24m, disabledHoio-domains"rockchip,rk3288-io-voltage-domainokay7YDNZYg9u[usbphyrockchip,rk3288-usb-phyokayusb-phy@320, 5]phyclkH?usb-phy@334,45^phyclkH=usb-phy@348,H5_phyclkH>watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p O disabledsound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif hclkmclk5T\ tx 6ydefault]V8 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5\\ txrxi2s_hclki2s_clk5Rydefault^ disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk #crypto-rstokayiommu@ff900800rockchip,iommu@ Fiep_mmu5 aclkiface disablediommu@ff914000rockchip,iommu @P Fisp_mmu5 aclkiface  disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclk'_ ilm #coreaxiahbvop@ff930000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vop'_ def #axiahbdclk5`okayportH endpoint@0<aHsendpoint@1<bHpendpoint@2<cHjendpoint@3<dHmiommu@ff930300rockchip,iommu  Fvopb_mmu5 aclkiface'_ okayH`vop@ff940000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vop'_  #axiahbdclk5eokayportH endpoint@0<fHtendpoint@1<gHqendpoint@2<hHkendpoint@3<iHniommu@ff940300rockchip,iommu  Fvopl_mmu5 aclkiface'_ okayHemipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclk'_ V8 disabledportsportendpoint@0<jHcendpoint@1<kHhlvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdsylcdcl'_ V8 disabledportsport@0endpoint@0<mHdendpoint@1<nHidp@ff970000rockchip,rk3288-dp@ b5icdppclkodpo#dpV8 disabledportsport@0endpoint@0<pHbendpoint@1<qHghdmi@ff980000rockchip,rk3288-dw-hdmigV8 g5hmniahbisfrcec'_ okayLrportsportendpoint@0<sHaendpoint@1<tHfiommu@ff9a0800rockchip,iommu Fvpu_mmu5 aclkiface disablediommu@ff9c0440rockchip,iommu @@@ o Fhevc_mmu5 aclkiface disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ Fjobmmugpu5u'_  disabledgpu-opp-tableoperating-points-v2Huopp@100000000[b~opp@200000000[ b~opp@300000000[bB@opp@400000000[ׄbopp@500000000[ebOopp@600000000[#Fbqos@ffaa0000syscon HWqos@ffaa0080syscon HXqos@ffad0000syscon HLqos@ffad0100syscon HMqos@ffad0180syscon HNqos@ffad0400syscon HOqos@ffad0480syscon HPqos@ffad0500syscon HKqos@ffad0800syscon HQqos@ffad0880syscon HRqos@ffad0900syscon HSqos@ffae0000syscon HVqos@ffaf0000syscon HTqos@ffaf0080syscon HUinterrupt-controller@ffc01000 arm,gic-400Xm@ @ `   Hefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrlV8pgpio0@ff750000rockchip,gpio-banku Q5@~XmHAgpio1@ff780000rockchip,gpio-bankx R5A~Xmgpio2@ff790000rockchip,gpio-banky S5B~Xmgpio3@ff7a0000rockchip,gpio-bankz T5C~Xmgpio4@ff7b0000rockchip,gpio-bank{ U5D~XmH:gpio5@ff7c0000rockchip,gpio-bank| V5E~Xmgpio6@ff7d0000rockchip,gpio-bank} W5F~Xmgpio7@ff7e0000rockchip,gpio-bank~ X5G~XmH|gpio8@ff7f0000rockchip,gpio-bank Y5H~XmH'hdmihdmi-cec-c0vhdmi-cec-c7vhdmi-ddc vvpcfg-pull-upHwpcfg-pull-downHxpcfg-pull-noneHvpcfg-pull-none-12ma Hysleepglobal-pwroffvHCddrio-pwroffvddr0-retentionwddr1-retentionwedpedp-hpd xi2c0i2c0-xfer vvH@i2c1i2c1-xfer vvH&i2c2i2c2-xfer  v vHFi2c3i2c3-xfer vvH*i2c4i2c4-xfer vvH+i2c5i2c5-xfer vvH,i2s0i2s0-bus`vvvvvvH^lcdclcdc-ctl@vvvvHlsdmmcsdmmc-clkvH sdmmc-cmdwHsdmmc-cdwHsdmmc-bus1wsdmmc-bus4@wwwwHsdmmc-pwr vH}sdio0sdio0-bus1wsdio0-bus4@wwwwsdio0-cmdwsdio0-clkvsdio0-cdwsdio0-wpwsdio0-pwrwsdio0-bkpwrwsdio0-intwsdio1sdio1-bus1wsdio1-bus4@wwwwsdio1-cdwsdio1-wpwsdio1-bkpwrwsdio1-intwsdio1-cmdwsdio1-clkvsdio1-pwr wemmcemmc-clkvHemmc-cmdwHemmc-pwr wHemmc-bus1wemmc-bus4@wwwwemmc-bus8wwwwwwwwHspi0spi0-clk wHspi0-cs0 wHspi0-txwHspi0-rxwHspi0-cs1wspi1spi1-clk wHspi1-cs0 wH!spi1-rxwH spi1-txwHspi2spi2-cs1wspi2-clkwH"spi2-cs0wH%spi2-rxwH$spi2-tx wH#uart0uart0-xfer wvH-uart0-ctswuart0-rtsvuart1uart1-xfer w vH.uart1-cts wuart1-rts vuart2uart2-xfer wvH/uart3uart3-xfer wvH0uart3-cts wuart3-rts vuart4uart4-xfer wvH1uart4-cts wuart4-rts vtsadcotp-gpio vH6otp-out vH7pwm0pwm0-pinvHGpwm1pwm1-pinvHHpwm2pwm2-pinvHIpwm3pwm3-pinvHJgmacrgmii-pinsvvvvyyyyvvv yyvvH<rmii-pinsvvvvvvvvvvspdifspdif-tx vH]ak8963comp-intwH(buttonspwrbtnwHzdvpdvp-pwrvHirir-intwH{mma8452gsensor-intwH)pmicpmic-intwHBmemory@0memoryexternal-gmac-clock fixed-clocksY@ ext_gmacH;gpio-keys gpio-keysydefaultzpower AtGPIO Key Power ` dir-receivergpio-ir-receiver Aydefault{flash-regulatorregulator-fixed Kvcc_flashw@3w@ %Hsdmmc-regulatorregulator-fixed | ydefault}Kvcc_sd2Z32Z 0 %Hvsys-regulatorregulator-fixedKvcc_sysLK@3LK@ HDvcc18-dvp-regulatorregulator-fixed Kvcc18-dvpw@3w@ %~HZvcc28-dvp-regulatorregulator-fixed A Aydefault Kvcc28_dvp*3* %H~ #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclockscpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removable#io-channel-cellsdmasdma-namesvdd-supplyvid-supplyst,drdy-int-pinvddio-supplyreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthautorepeatgpioslinux,codelabellinux,input-typedebounce-intervalvin-supplystartup-delay-usenable-active-high