V8d( ,google,veyron-jaq-rev5google,veyron-jaq-rev4google,veyron-jaq-rev3google,veyron-jaq-rev2google,veyron-jaq-rev1google,veyron-jaqgoogle,veyronrockchip,rk3288& 7Google Jaqaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 -@;Br\ hcpu@501cpuarm,cortex-a12 -@;Brhcpu@502cpuarm,cortex-a12 -@;Brhcpu@503cpuarm,cortex-a12 -@;Brhopp-table-0operating-points-v2phopp-126000000{ opp-216000000{  opp-408000000{Q opp-600000000{#F opp-696000000{)|~opp-816000000{0,B@opp-1008000000{<opp-1200000000{Gopp-1416000000{TfrOopp-1512000000{ZJopp-1608000000{_" opp-1704000000{epopp-1800000000{kI\reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mh timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H ;a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр ;Drvbiuciuciu-driveciu-sample"  @-reset9okay@J\m  Zdefault mmc@ff0d0000rockchip,rk3288-dw-mshcр ;Eswbiuciuciu-driveciu-sample" ! @-reset9okay@\$:Edefault  btmrvl@2marvell,sd8897-bt&S default mmc@ff0e0000rockchip,rk3288-dw-mshcр ;Ftxbiuciuciu-driveciu-sample" "@-reset 9disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр ;Guybiuciuciu-driveciu-sample" #@-reset9okay@Jf:Edefault   saradc@ff100000rockchip,saradc $u;I[saradcapb_pclkW -saradc-apb 9disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi;ARspiclkapb_pclk! ! txrx ,default "#$%9okayec@0google,cros-ec-spi& default &-i2c-tunnelgoogle,cros-ec-i2c-tunnelsbs-battery@bsbs,sbs-battery keyboard-controllergoogle,cros-ec-keyb #D=;<=>?@A B CD}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi;BSspiclkapb_pclk! !txrx -default '()* 9disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi;CTspiclkapb_pclk!!txrx .default +,-.9okayJ flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c;Mdefault /9okay]2udtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c;Odefault 0 9disabledi2c@ff160000rockchip,rk3288-i2c @i2c;Pdefault 19okay]2u,ts3a227e@3b ti,ts3a227e;&2default 3htrackpad@15elan,ekth3000& default 45i2c@ff170000rockchip,rk3288-i2c Ai2c;Qdefault 6 9disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7;MUbaudclkapb_pclk!!txrxdefault  7899okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8;NVbaudclkapb_pclk!!txrxdefault :9okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9;OWbaudclkapb_pclkdefault ;9okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :;PXbaudclkapb_pclk!!txrxdefault < 9disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;;QYbaudclkapb_pclk! ! txrxdefault = 9disableddma-controller@ff250000arm,pl330arm,primecell%@; apb_pclkh!thermal-zonesreserve-thermal2@>cpu-thermald2@>tripscpu_alert0Pp\passiveh?cpu_alert1P$\passiveh@cpu_critP\ criticalcooling-mapsmap0g?0lmap1g@0lgpu-thermald2@>tripsgpu_alert0P4\passivehAgpu_critP\ criticalcooling-mapsmap0gA lBtsadc@ff280000rockchip,rk3288-tsadc( %;HZtsadcapb_pclk -tsadc-apbinitdefaultsleep C{DCEH9okayh>ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irqE8;fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB -stmmaceth 9disabledusb@ff500000 generic-ehciP ; Fusb9okayusb@ff520000 generic-ohciR ); Fusb 9disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T ;otg0host G usb2-phy89okayOusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X ;otg0hostfx@@  H usb2-phy9okayzHOusb@ff5c0000 generic-ehci\ ; 9disableddma-controller@ff600000arm,pl330arm,primecell`@; apb_pclk 9disabledi2c@ff650000rockchip,rk3288-i2ce <i2c;Ldefault I9okay]2udpmic@1brockchip,rk808xin32kwifibt_32kin&2default  JKLM&2?5LYMeMr hregulatorsDCDC_REG1|vdd_arm q qh regulator-state-memDCDC_REG2|vdd_gpu 5qhregulator-state-memDCDC_REG3 |vcc135_ddrregulator-state-memDCDC_REG4|vcc_18w@w@hregulator-state-mem'w@LDO_REG1 |vcc33_io2Z2Zh5regulator-state-mem'2ZLDO_REG3|vdd_10B@B@regulator-state-mem'B@LDO_REG7|vdd10_lcd_pwren_h&%&%regulator-state-memSWITCH_REG1 |vcc33_lcdhcregulator-state-memLDO_REG6 |vcc18_codecw@w@hdregulator-state-memLDO_REG4 |vccio_sdw@2Zhregulator-state-memLDO_REG5 |vcc33_sd2Z2Zhregulator-state-memLDO_REG8 |vcc33_ccd2Z2Zregulator-state-memLDO_REG2|mic_vccw@w@regulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c;Ndefault N9okay]2u max98090@10maxim,max98090&Omclk;qdefault Phpwm@ff680000rockchip,rk3288-pwmhCdefault Q;_9okayhpwm@ff680010rockchip,rk3288-pwmhCdefault R;_9okayhpwm@ff680020rockchip,rk3288-pwmh Cdefault S;_ 9disabledpwm@ff680030rockchip,rk3288-pwmh0Cdefault T;_ 9disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdshpower-controller!rockchip,rk3288-power-controllerNh hhpower-domain@9 ;chgfdehilkj$bUVWXYZ[\]Npower-domain@11 ;opb^_Npower-domain@12 ;b`Npower-domain@13 ;babNreboot-modesyscon-reboot-modeipRB|RBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv; xin24mEHjk$#gׄeрxhрxhhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwhEedp-phyrockchip,rk3288-dp-phy;h24m9okayhxio-domains"rockchip,rk3288-io-voltage-domain9okay55 5 c  ,d 9usbphyrockchip,rk3288-usb-phy9okayusb-phy@320 ;]phyclk -phy-resethHusb-phy@3344;^phyclk -phy-resethFusb-phy@348H;_phyclk -phy-resethGwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt;p O9okaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif G;T mclkhclketx 6default fE 9disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s G 5;Ri2s_clki2s_hclkeetxrxdefault g X s9okayhcrypto@ff8a0000rockchip,rk3288-crypto@ 0 ;}aclkhclksclkapb_pclk -crypto-rstiommu@ff900800rockchip,iommu@ ; aclkiface  9disablediommu@ff914000rockchip,iommu @P ; aclkiface   9disabledrga@ff920000rockchip,rk3288-rga ;jaclkhclksclk h ilm -coreaxiahbvop@ff930000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop h def -axiahbdclk i9okayporth endpoint@0 jhendpoint@1 khzendpoint@2 lhsendpoint@3 mhviommu@ff930300rockchip,iommu ; aclkiface h  9okayhivop@ff940000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop h  -axiahbdclk n9okayporth endpoint@0 ohendpoint@1 ph{endpoint@2 qhtendpoint@3 rhwiommu@ff940300rockchip,iommu ; aclkiface h  9okayhnmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ ;~d refpclk h E 9disabledportsportendpoint@0 shlendpoint@1 thqlvds@ff96c000rockchip,rk3288-lvds@;g pclk_lvdslcdc u h E 9disabledportsport@0endpoint@0 vhmendpoint@1 whrdp@ff970000rockchip,rk3288-dp@ b;icdppclk xdpo-dpE9okaydefault yportsport@0endpoint@0 zhkendpoint@1 {hpport@1endpoint@0 |hhdmi@ff980000rockchip,rk3288-dw-hdmi GE g;hmniahbisfrcec h 9okaydefaultunwedge }{~hportsportendpoint@0 hjendpoint@1 hovideo-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu; aclkhclk  h iommu@ff9a0800rockchip,iommu ; aclkiface  h hiommu@ff9c0440rockchip,iommu @@@ o; aclkiface  9disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu;  h 9okay hBopp-table-1operating-points-v2hopp-100000000{~opp-200000000{ ~opp-300000000{B@opp-400000000{ׄopp-600000000{#Fqos@ffaa0000rockchip,rk3288-qossyscon haqos@ffaa0080rockchip,rk3288-qossyscon hbqos@ffad0000rockchip,rk3288-qossyscon hVqos@ffad0100rockchip,rk3288-qossyscon hWqos@ffad0180rockchip,rk3288-qossyscon hXqos@ffad0400rockchip,rk3288-qossyscon hYqos@ffad0480rockchip,rk3288-qossyscon hZqos@ffad0500rockchip,rk3288-qossyscon hUqos@ffad0800rockchip,rk3288-qossyscon h[qos@ffad0880rockchip,rk3288-qossyscon h\qos@ffad0900rockchip,rk3288-qossyscon h]qos@ffae0000rockchip,rk3288-qossyscon h`qos@ffaf0000rockchip,rk3288-qossyscon h^qos@ffaf0080rockchip,rk3288-qossyscon h_dma-controller@ffb20000arm,pl330arm,primecell@; apb_pclkheefuse@ffb40000rockchip,rk3288-efuse ;q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400  @ @ `   hpinctrlrockchip,rk3288-pinctrlEdefaultsleep {gpio@ff750000rockchip,gpio-banku Q;@     (PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTh2gpio@ff780000rockchip,gpio-bankx R;A    gpio@ff790000rockchip,gpio-banky S;B    M (CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENhgpio@ff7a0000rockchip,gpio-bankz T;C     (FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bank{ U;D     (UART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEhgpio@ff7c0000rockchip,gpio-bank| V;E    A (SPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENhgpio@ff7d0000rockchip,gpio-bank} W;F     (I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HALS_INTINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDhOgpio@ff7e0000rockchip,gpio-bank~ X;G     (LCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVSOKSDMMC_WPEDP_HPDDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDh gpio@ff7f0000rockchip,gpio-bank Y;H    ^ (RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 8hdmi-cec-c7 8hdmi-ddc 8h}hdmi-ddc-unwedge 8h~vcc50-hdmi-en 8hpcfg-output-low Fhpcfg-pull-up Qhpcfg-pull-down ^hpcfg-pull-none mhpcfg-pull-none-12ma m z hsuspendglobal-pwroff 8hddrio-pwroff 8hddr0-retention 8hddr1-retention 8suspend-l-wake 8hsuspend-l-sleep 8hedpedp-hpd 8 hyi2c0i2c0-xfer 8hIi2c1i2c1-xfer 8h/i2c2i2c2-xfer 8  hNi2c3i2c3-xfer 8h0i2c4i2c4-xfer 8h1i2c5i2c5-xfer 8h6i2s0i2s0-bus` 8hglcdclcdc-ctl@ 8husdmmcsdmmc-clk 8hsdmmc-cmd 8hsdmmc-cd 8sdmmc-bus1 8sdmmc-bus4@ 8hsdmmc-cd-disabled 8hsdmmc-cd-pin 8hsdio0sdio0-bus1 8sdio0-bus4@ 8hsdio0-cmd 8hsdio0-clk 8hsdio0-cd 8sdio0-wp 8sdio0-pwr 8sdio0-bkpwr 8sdio0-int 8wifienable-h 8hbt-enable-l 8bt-host-wake 8bt-host-wake-l 8hbt-dev-wake-sleep 8hbt-dev-wake-awake 8hbt-dev-wake 8sdio1sdio1-bus1 8sdio1-bus4@ 8sdio1-cd 8sdio1-wp 8sdio1-bkpwr 8sdio1-int 8sdio1-cmd 8sdio1-clk 8sdio1-pwr 8 emmcemmc-clk 8hemmc-cmd 8hemmc-pwr 8 emmc-bus1 8emmc-bus4@ 8emmc-bus8 8h emmc-reset 8 hspi0spi0-clk 8 h"spi0-cs0 8 h%spi0-tx 8h#spi0-rx 8h$spi0-cs1 8spi1spi1-clk 8 h'spi1-cs0 8 h*spi1-rx 8h)spi1-tx 8h(spi2spi2-cs1 8spi2-clk 8h+spi2-cs0 8h.spi2-rx 8h-spi2-tx 8 h,uart0uart0-xfer 8h7uart0-cts 8h8uart0-rts 8h9uart1uart1-xfer 8 h:uart1-cts 8 uart1-rts 8 uart2uart2-xfer 8h;uart3uart3-xfer 8h<uart3-cts 8 uart3-rts 8 uart4uart4-xfer 8h=uart4-cts 8 uart4-rts 8 tsadcotp-pin 8 hCotp-out 8 hDpwm0pwm0-pin 8hQpwm1pwm1-pin 8hRpwm2pwm2-pin 8hSpwm3pwm3-pin 8hTgmacrgmii-pins 8 rmii-pins 8spdifspdif-tx 8 hfpcfg-pull-none-drv-8ma m zhpcfg-pull-up-drv-8ma Q zpcfg-output-high hbuttonspwr-key-l 8hap-lid-int-l 8hpmicpmic-int-l 8hJdvs-1 8 hKdvs-2 8hLrebootap-warm-reset-h 8 hrecovery-switchrec-mode-l 8 tpmtpm-int-h 8write-protectfw-wp-ap 8codechp-det 8hint-codec 8hPmic-det 8 hheadsetts3a227e-int-l 8h3backlightbl_pwr_en 8 hbl-en 8hlcdlcd-en 8havdd-1v8-disp-en 8 hchargerac-present-ap 8hcros-ecec-int 8h&trackpadtrackpad-int 8h4usb-hosthost1-pwr-en 8 husbotg-pwren-h 8 hbuck-5vdrv-5v 8hchosen serial2:115200n8memorymemorypower-button gpio-keysdefault key-power Power 2 t dgpio-restart gpio-restart 2 default  emmc-pwrseqmmc-pwrseq-emmc default hsdio-pwrseqmmc-pwrseq-simple; ext_clockdefault  hvcc-5vregulator-fixed|vcc_5vLK@LK@   default hMvcc33-sysregulator-fixed |vcc33_sys2Z2Z hvcc50-hdmiregulator-fixed |vcc50_hdmi M  default vdd-logicpwm-regulator |vdd_logic   { ~psound!rockchip,rockchip-audio-max98090default  3VEYRON-I2S B Z oO O   backlight-regulatorregulator-fixed  default |backlight_regulator  :hpanel-regulatorregulator-fixed  default |panel_regulator hvcc18-lcdregulator-fixed  default  |vcc18_lcd backlightpwm-backlight     default  B@ '  <  Mhpanelinnolux,n116bge9okay M Zpanel-timingl dV l y<       portsportendpoint h|gpio-charger gpio-charger mains 2default lid-switch gpio-keysdefault switch-lid Lid 2   vccsysregulator-fixed|vccsyshvcc5-host1-regulatorregulator-fixed  2 default  |vcc5_host1vcc5v-otg-regulatorregulator-fixed  2 default  |vcc5_host2 #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemarvell,wakeup-pinmmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenhsync-activevactivevfront-porchvback-porchvsync-lenvsync-activecharger-typelinux,input-type