8( Xti,omap3-ldpti,omap3&!7TI OMAP3430 LDP (Zoom1 Labrador)chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000 d/displaymemorymmemoryycpuscpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmuarm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp simple-busyh l3_mainaes@480c5000 ti,omap3-aesaesyH PPprm@48306000 ti,omap3-prmyH0`@clocksvirt_16_8m_ck fixed-clockY  osc_sys_ck ti,mux-clock} y @  sys_ckti,divider-clock} ypsys_clkout1ti,gate-clock} y pdpll3_x2_ckfixed-factor-clock} 1<dpll3_m2x2_ckfixed-factor-clock} 1<dpll4_x2_ckfixed-factor-clock} 1<corex2_fckfixed-factor-clock}1<wkup_l4_ickfixed-factor-clock}1<AAcorex2_d3_fckfixed-factor-clock}1<xxcorex2_d5_fckfixed-factor-clock}1<yyclockdomainscm@48004000 ti,omap3-cmyH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock11virt_12m_ck fixed-clockvirt_13m_ck fixed-clock]@virt_19200000_ck fixed-clock$virt_26000000_ck fixed-clockvirt_38_4m_ck fixed-clockIdpll4_ckti,omap3-dpll-per-clock}y D 0  dpll4_m2_ckti,divider-clock} ?y Hdpll4_m2x2_mul_ckfixed-factor-clock}1<dpll4_m2x2_ckti,gate-clock}y Fomap_96m_alwon_fckfixed-factor-clock}1<dpll3_ckti,omap3-dpll-core-clock}y @ 0  dpll3_m3_ckti,divider-clock} y@dpll3_m3x2_mul_ckfixed-factor-clock}1<dpll3_m3x2_ckti,gate-clock} y Femu_core_alwon_ckfixed-factor-clock}1<UUsys_altclk fixed-clockmcbsp_clks fixed-clock88dpll3_m2_ckti,divider-clock} y @  core_ckfixed-factor-clock} 1<dpll1_fckti,divider-clock}y @dpll1_ckti,omap3-dpll-clock}y  $ @ 4dpll1_x2_ckfixed-factor-clock}1<dpll1_x2m2_ckti,divider-clock}y D--cm_96m_fckfixed-factor-clock}1<omap_96m_fck ti,mux-clock}y @66dpll4_m3_ckti,divider-clock}  y@dpll4_m3x2_mul_ckfixed-factor-clock}1<dpll4_m3x2_ckti,gate-clock}y Fomap_54m_fck ti,mux-clock}y @))cm_96m_d2_fckfixed-factor-clock}1<  omap_48m_fck ti,mux-clock} y @!!omap_12m_fckfixed-factor-clock}!1<::dpll4_m4_ckti,divider-clock}  y@""dpll4_m4x2_mul_ckti,fixed-factor-clock}"\jw##dpll4_m4x2_ckti,gate-clock}#y Fw||dpll4_m5_ckti,divider-clock} ?y@$$dpll4_m5x2_mul_ckti,fixed-factor-clock}$\jw%%dpll4_m5x2_ckti,gate-clock}%y F]]dpll4_m6_ckti,divider-clock} ?y@&&dpll4_m6x2_mul_ckfixed-factor-clock}&1<''dpll4_m6x2_ckti,gate-clock}'y F((emu_per_alwon_ckfixed-factor-clock}(1<VVclkout2_src_gate_ck ti,composite-no-wait-gate-clock}y p**clkout2_src_mux_ckti,composite-mux-clock})y p++clkout2_src_ckti,composite-clock}*+,,sys_clkout2ti,divider-clock},@y pmpu_ckfixed-factor-clock}-1<..arm_fckti,divider-clock}.y $emu_mpu_alwon_ckfixed-factor-clock}.1<WWl3_ickti,divider-clock}y @//l4_ickti,divider-clock}/y @00rm_ickti,divider-clock}0y @gpt10_gate_fckti,composite-gate-clock} y 22gpt10_mux_fckti,composite-mux-clock}1y @33gpt10_fckti,composite-clock}23gpt11_gate_fckti,composite-gate-clock} y 44gpt11_mux_fckti,composite-mux-clock}1y @55gpt11_fckti,composite-clock}45core_96m_fckfixed-factor-clock}61<77mmchs2_fckti,wait-gate-clock}7y mmchs1_fckti,wait-gate-clock}7y i2c3_fckti,wait-gate-clock}7y i2c2_fckti,wait-gate-clock}7y i2c1_fckti,wait-gate-clock}7y mcbsp5_gate_fckti,composite-gate-clock}8 y mcbsp1_gate_fckti,composite-gate-clock}8 y core_48m_fckfixed-factor-clock}!1<99mcspi4_fckti,wait-gate-clock}9y mcspi3_fckti,wait-gate-clock}9y mcspi2_fckti,wait-gate-clock}9y mcspi1_fckti,wait-gate-clock}9y uart2_fckti,wait-gate-clock}9y uart1_fckti,wait-gate-clock}9y  core_12m_fckfixed-factor-clock}:1<;;hdq_fckti,wait-gate-clock};y core_l3_ickfixed-factor-clock}/1<<<sdrc_ickti,wait-gate-clock}<y }}gpmc_fckfixed-factor-clock}<1<core_l4_ickfixed-factor-clock}01<==mmchs2_ickti,omap3-interface-clock}=y mmchs1_ickti,omap3-interface-clock}=y hdq_ickti,omap3-interface-clock}=y mcspi4_ickti,omap3-interface-clock}=y mcspi3_ickti,omap3-interface-clock}=y mcspi2_ickti,omap3-interface-clock}=y mcspi1_ickti,omap3-interface-clock}=y i2c3_ickti,omap3-interface-clock}=y i2c2_ickti,omap3-interface-clock}=y i2c1_ickti,omap3-interface-clock}=y uart2_ickti,omap3-interface-clock}=y uart1_ickti,omap3-interface-clock}=y  gpt11_ickti,omap3-interface-clock}=y  gpt10_ickti,omap3-interface-clock}=y  mcbsp5_ickti,omap3-interface-clock}=y  mcbsp1_ickti,omap3-interface-clock}=y  omapctrl_ickti,omap3-interface-clock}=y dss_tv_fckti,gate-clock})ydss_96m_fckti,gate-clock}6ydss2_alwon_fckti,gate-clock}ydummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock}y >>gpt1_mux_fckti,composite-mux-clock}1y @??gpt1_fckti,composite-clock}>?aes2_ickti,omap3-interface-clock}=y wkup_32k_fckfixed-factor-clock}11<@@gpio1_dbckti,gate-clock}@y sha12_ickti,omap3-interface-clock}=y wdt2_fckti,wait-gate-clock}@y wdt2_ickti,omap3-interface-clock}Ay wdt1_ickti,omap3-interface-clock}Ay gpio1_ickti,omap3-interface-clock}Ay omap_32ksync_ickti,omap3-interface-clock}Ay gpt12_ickti,omap3-interface-clock}Ay gpt1_ickti,omap3-interface-clock}Ay per_96m_fckfixed-factor-clock}1<per_48m_fckfixed-factor-clock}!1<BBuart3_fckti,wait-gate-clock}By gpt2_gate_fckti,composite-gate-clock}yCCgpt2_mux_fckti,composite-mux-clock}1y@DDgpt2_fckti,composite-clock}CDgpt3_gate_fckti,composite-gate-clock}yEEgpt3_mux_fckti,composite-mux-clock}1y@FFgpt3_fckti,composite-clock}EFgpt4_gate_fckti,composite-gate-clock}yGGgpt4_mux_fckti,composite-mux-clock}1y@HHgpt4_fckti,composite-clock}GHgpt5_gate_fckti,composite-gate-clock}yIIgpt5_mux_fckti,composite-mux-clock}1y@JJgpt5_fckti,composite-clock}IJgpt6_gate_fckti,composite-gate-clock}yKKgpt6_mux_fckti,composite-mux-clock}1y@LLgpt6_fckti,composite-clock}KLgpt7_gate_fckti,composite-gate-clock}yMMgpt7_mux_fckti,composite-mux-clock}1y@NNgpt7_fckti,composite-clock}MNgpt8_gate_fckti,composite-gate-clock} yOOgpt8_mux_fckti,composite-mux-clock}1y@PPgpt8_fckti,composite-clock}OPgpt9_gate_fckti,composite-gate-clock} yQQgpt9_mux_fckti,composite-mux-clock}1y@RRgpt9_fckti,composite-clock}QRper_32k_alwon_fckfixed-factor-clock}11<SSgpio6_dbckti,gate-clock}Sygpio5_dbckti,gate-clock}Sygpio4_dbckti,gate-clock}Sygpio3_dbckti,gate-clock}Sygpio2_dbckti,gate-clock}Sy wdt3_fckti,wait-gate-clock}Sy per_l4_ickfixed-factor-clock}01<TTgpio6_ickti,omap3-interface-clock}Tygpio5_ickti,omap3-interface-clock}Tygpio4_ickti,omap3-interface-clock}Tygpio3_ickti,omap3-interface-clock}Tygpio2_ickti,omap3-interface-clock}Ty wdt3_ickti,omap3-interface-clock}Ty uart3_ickti,omap3-interface-clock}Ty uart4_ickti,omap3-interface-clock}Tygpt9_ickti,omap3-interface-clock}Ty gpt8_ickti,omap3-interface-clock}Ty gpt7_ickti,omap3-interface-clock}Tygpt6_ickti,omap3-interface-clock}Tygpt5_ickti,omap3-interface-clock}Tygpt4_ickti,omap3-interface-clock}Tygpt3_ickti,omap3-interface-clock}Tygpt2_ickti,omap3-interface-clock}Tymcbsp2_ickti,omap3-interface-clock}Tymcbsp3_ickti,omap3-interface-clock}Tymcbsp4_ickti,omap3-interface-clock}Tymcbsp2_gate_fckti,composite-gate-clock}8ymcbsp3_gate_fckti,composite-gate-clock}8ymcbsp4_gate_fckti,composite-gate-clock}8yemu_src_mux_ck ti,mux-clock}UVWy@XXemu_src_ckti,clkdm-gate-clock}XYYpclk_fckti,divider-clock}Yy@pclkx2_fckti,divider-clock}Yy@atclk_fckti,divider-clock}Yy@traceclk_src_fck ti,mux-clock}UVWy@ZZtraceclk_fckti,divider-clock}Z y@secure_32k_fck fixed-clock[[gpt12_fckfixed-factor-clock}[1<wdt1_fckfixed-factor-clock}[1<security_l4_ick2fixed-factor-clock}01<\\aes1_ickti,omap3-interface-clock}\y rng_ickti,omap3-interface-clock}\y sha11_ickti,omap3-interface-clock}\y des1_ickti,omap3-interface-clock}\y cam_mclkti,gate-clock}]ywcam_ick!ti,omap3-no-wait-interface-clock}0ycsi2_96m_fckti,gate-clock}7ysecurity_l3_ickfixed-factor-clock}/1<^^pka_ickti,omap3-interface-clock}^y icr_ickti,omap3-interface-clock}=y des2_ickti,omap3-interface-clock}=y mspro_ickti,omap3-interface-clock}=y mailboxes_ickti,omap3-interface-clock}=y ssi_l4_ickfixed-factor-clock}01<eesr1_fckti,wait-gate-clock}y sr2_fckti,wait-gate-clock}y sr_l4_ickfixed-factor-clock}01<dpll2_fckti,divider-clock}y@__dpll2_ckti,omap3-dpll-clock}_y$@4``dpll2_m2_ckti,divider-clock}`yDaaiva2_ckti,wait-gate-clock}aymodem_fckti,omap3-interface-clock}y sad2d_ickti,omap3-interface-clock}/y mad2d_ickti,omap3-interface-clock}/y mspro_fckti,wait-gate-clock}7y ssi_ssr_gate_fck_3430es2 ti,composite-no-wait-gate-clock}y bbssi_ssr_div_fck_3430es2ti,composite-divider-clock}y @$ccssi_ssr_fck_3430es2ti,composite-clock}bcddssi_sst_fck_3430es2fixed-factor-clock}d1<hsotgusb_ick_3430es2"ti,omap3-hsotgusb-interface-clock}<y ~~ssi_ick_3430es2ti,omap3-ssi-interface-clock}ey usim_gate_fckti,composite-gate-clock}6 y ppsys_d2_ckfixed-factor-clock}1<ggomap_96m_d2_fckfixed-factor-clock}61<hhomap_96m_d4_fckfixed-factor-clock}61<iiomap_96m_d8_fckfixed-factor-clock}61<jjomap_96m_d10_fckfixed-factor-clock}61< kkdpll5_m2_d4_ckfixed-factor-clock}f1<lldpll5_m2_d8_ckfixed-factor-clock}f1<mmdpll5_m2_d16_ckfixed-factor-clock}f1<nndpll5_m2_d20_ckfixed-factor-clock}f1<oousim_mux_fckti,composite-mux-clock(}ghijklmnoy @qqusim_fckti,composite-clock}pqusim_ickti,omap3-interface-clock}Ay  dpll5_ckti,omap3-dpll-clock}y  $ L 4rrdpll5_m2_ckti,divider-clock}ry Pffsgx_gate_fckti,composite-gate-clock}y zzcore_d3_ckfixed-factor-clock}1<sscore_d4_ckfixed-factor-clock}1<ttcore_d6_ckfixed-factor-clock}1<uuomap_192m_alwon_fckfixed-factor-clock}1<vvcore_d2_ckfixed-factor-clock}1<wwsgx_mux_fckti,composite-mux-clock }stuvwxyy @{{sgx_fckti,composite-clock}z{sgx_ickti,wait-gate-clock}/y cpefuse_fckti,gate-clock}y ts_fckti,gate-clock}1y usbtll_fckti,wait-gate-clock}fy usbtll_ickti,omap3-interface-clock}=y mmchs3_ickti,omap3-interface-clock}=y mmchs3_fckti,wait-gate-clock}7y dss1_alwon_fck_3430es2ti,dss-gate-clock}|ywdss_ick_3430es2ti,omap3-dss-interface-clock}0yusbhost_120m_fckti,gate-clock}fyusbhost_48m_fckti,dss-gate-clock}!yusbhost_ickti,omap3-dss-interface-clock}0yclockdomainscore_l3_clkdmti,clockdomain}}~dpll3_clkdmti,clockdomain} dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}Ydpll4_clkdmti,clockdomain} wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}`d2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}rsgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }scrm@48002000ti,omap3-scrmyH clocksmcbsp5_mux_fckti,composite-mux-clock}78ymcbsp5_fckti,composite-clock}mcbsp1_mux_fckti,composite-mux-clock}78ytmcbsp1_fckti,composite-clock}mcbsp2_mux_fckti,composite-mux-clock}8ytmcbsp2_fckti,composite-clock}mcbsp3_mux_fckti,composite-mux-clock}8ymcbsp3_fckti,composite-clock}mcbsp4_mux_fckti,composite-mux-clock}8ymcbsp4_fckti,composite-clock}clockdomainscounter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap2-intc`yH dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH`   &`pinmux@48002030 ti,omap3-padconfpinctrl-singleyH 084Rpinmux_twl4030_pinsoApinmux_gpio_key_pinsHopinmux_musb_pins`orz|~vxtpinmux_mmc1_pins0opinmux@48002a00 ti,omap3-padconfpinctrl-singleyH*\4Rpinmux_twl4030_vpins otisyscon@48002270sysconyH"ppbias_regulatorti,pbias-omapypbias_mmc_omap2430pbias_mmc_omap2430w@-gpio@48310000ti,omap3-gpioyH1gpio1gpio@49050000ti,omap3-gpioyIgpio2gpio@49052000ti,omap3-gpioyI gpio3gpio@49054000ti,omap3-gpioyI@ gpio4gpio@49056000ti,omap3-gpioyI`!gpio5gpio@49058000ti,omap3-gpioyI"gpio6serial@4806a000ti,omap3-uartyH H 12txrxuart1lserial@4806c000ti,omap3-uartyHI 34txrxuart2lserial@49020000ti,omap3-uartyIJn 56txrxuart3li2c@48070000 ti,omap3-i2cyH8 txrxi2c1'@twl@48yH& ti,twl4030default(rtcti,twl4030-rtc bciti,twl4030-bci 2watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1vccregulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpiotwl4030-usbti,twl4030-usb Tbp~pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madci2c@48072000 ti,omap3-i2cyH 9 txrxi2c2i2c@48060000 ti,omap3-i2cyH= txrxi2c3mailbox@48094000ti,omap3-mailboxmailboxyH @spi@48098000ti,omap2-mcspiyH Amcspi1@ #$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3tsc2046@0y ti,tsc2046B@@!(1AL& Yspi@4809a000ti,omap2-mcspiyH Bmcspi2  +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [mcspi3  tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiyH 0mcspi4 FGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-pre-es3-hsmmcyH Smmc1f =>txrxsdefault(mmc@480b4000ti,omap3-hsmmcyH @Vmmc2 /0txrx disabledmmc@480ad000ti,omap3-hsmmcyH ^mmc3 MNtxrx disabledmmu@480bd400ti,omap2-iommuyH mmu_ispmmu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< commontxrxmcbsp1  txrx disabledmcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone !"txrx disabledmcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetone txrx disabledmcbsp@49026000ti,omap3-mcbspyI`mpu 67 commontxrxmcbsp4 txrx disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR commontxrxmcbsp5 txrx disabledsham@480c3000ti,omap3-shamshamyH 0d1smartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreyH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivayH timer@48318000ti,omap3430-timeryH1%timer1timer@49032000ti,omap3430-timeryI &timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5timer@4903a000ti,omap3430-timeryI*timer6timer@4903c000ti,omap3430-timeryI+timer7timer@4903e000ti,omap3430-timeryI,timer8timer@49040000ti,omap3430-timeryI-timer9timer@48086000ti,omap3430-timeryH`.timer10timer@48088000ti,omap3430-timeryH/timer11timer@48304000ti,omap3430-timeryH0@_timer12usbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hsohci@48064400ti,ohci-omap3yHD&Lehci@48064800 ti,ehci-omapyHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcyn ethernet@gpmcsmsc,lan9221smsc,lan9115-8JXj|066 'Z>ZXr& ynand@0,0 micron,nand ybch8JX,j, |",(6@RR(-partition@0 EX-Loaderypartition@80000EU-Bootypartition@1c0000 EEnvironmentypartition@200000EKernely partition@2000000 EFilesystemyusb_otg_hs@480ab000ti,omap3-musbyH \]mcdma usb_otg_hsKV^ default(gv~2dss@48050000 ti,omap3-dssyHok dss_core}fckdispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpointssi-controller@48058000 ti,omap3-ssissiokyHHsysgddGgdd_mpu }d ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrx&CDssi-port@4805b000ti,omap3-ssi-portyHHtxrx&EFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$4Rregulator-vddvarioregulator-fixed vddvario@regulator-vdd33aregulator-fixedvdd33a@gpio_keys gpio-keysdefault(key_enterEenter key_f1Ef1 ;key_f2Ef2 <key_f3Ef3 =key_f4Ef4  >key_leftEleft  ikey_rightEright  jkey_upEup  gkey_downEdown  lbacklightgpio-backlight regulator-lcd-3v3regulator-fixedlcd_3v32Z2Zp@displaysharp,ls037v7dw01Elcd   portendpoint #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#clock-cellsclock-frequencylinux,phandleti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersinterrupt-controller#interrupt-cellsti,intc-size#dma-cells#dma-channels#dma-requestspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendeddmasdma-namespinctrl-namespinctrl-0bci3v1-supplyregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xylinux,wakeuppendown-gpioti,dual-voltpbias-supplyvmmc-supplybus-widthstatusti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsbank-widthgpmc,mux-add-datagpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,adv-on-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelmultipointnum-epsram-bitsinterface-typeusb-phypowerremote-endpointdata-linesgpioslinux,codegpio-key,wakeupdefault-onstartup-delay-uspower-supplyenable-gpiosreset-gpiosmode-gpios