w8T( #Bgumstix,omap3-overo-tobigumstix,omap3-overoti,omap3430ti,omap3&7OMAP35xx Gumstix Overo on Tobichosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000 d/connector@0memorymmemoryycpuscpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmuarm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp simple-busyh l3_mainaes@480c5000 ti,omap3-aesaesyH PPprm@48306000 ti,omap3-prmyH0`@clocksvirt_16_8m_ck fixed-clockYosc_sys_ck ti,mux-clock}y @  sys_ckti,divider-clock} ypsys_clkout1ti,gate-clock} y pdpll3_x2_ckfixed-factor-clock} %0dpll3_m2x2_ckfixed-factor-clock} %0  dpll4_x2_ckfixed-factor-clock} %0corex2_fckfixed-factor-clock} %0wkup_l4_ickfixed-factor-clock}%0@@corex2_d3_fckfixed-factor-clock}%0wwcorex2_d5_fckfixed-factor-clock}%0xxclockdomainscm@48004000 ti,omap3-cmyH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock00virt_12m_ck fixed-clockvirt_13m_ck fixed-clock]@virt_19200000_ck fixed-clock$virt_26000000_ck fixed-clockvirt_38_4m_ck fixed-clockIdpll4_ckti,omap3-dpll-per-clock}y D 0  dpll4_m2_ckti,divider-clock} ?y Hdpll4_m2x2_mul_ckfixed-factor-clock}%0dpll4_m2x2_ckti,gate-clock}y :omap_96m_alwon_fckfixed-factor-clock}%0dpll3_ckti,omap3-dpll-core-clock}y @ 0  dpll3_m3_ckti,divider-clock} y@dpll3_m3x2_mul_ckfixed-factor-clock}%0dpll3_m3x2_ckti,gate-clock} y :emu_core_alwon_ckfixed-factor-clock}%0TTsys_altclk fixed-clockmcbsp_clks fixed-clock77dpll3_m2_ckti,divider-clock} y @  core_ckfixed-factor-clock} %0dpll1_fckti,divider-clock}y @dpll1_ckti,omap3-dpll-clock}y  $ @ 4dpll1_x2_ckfixed-factor-clock}%0dpll1_x2m2_ckti,divider-clock}y D,,cm_96m_fckfixed-factor-clock}%0omap_96m_fck ti,mux-clock}y @55dpll4_m3_ckti,divider-clock}  y@dpll4_m3x2_mul_ckfixed-factor-clock}%0dpll4_m3x2_ckti,gate-clock}y :omap_54m_fck ti,mux-clock}y @((cm_96m_d2_fckfixed-factor-clock}%0omap_48m_fck ti,mux-clock}y @  omap_12m_fckfixed-factor-clock} %099dpll4_m4_ckti,divider-clock}  y@!!dpll4_m4x2_mul_ckti,fixed-factor-clock}!P^k""dpll4_m4x2_ckti,gate-clock}"y :k{{dpll4_m5_ckti,divider-clock} ?y@##dpll4_m5x2_mul_ckti,fixed-factor-clock}#P^k$$dpll4_m5x2_ckti,gate-clock}$y :\\dpll4_m6_ckti,divider-clock} ?y@%%dpll4_m6x2_mul_ckfixed-factor-clock}%%0&&dpll4_m6x2_ckti,gate-clock}&y :''emu_per_alwon_ckfixed-factor-clock}'%0UUclkout2_src_gate_ck ti,composite-no-wait-gate-clock}y p))clkout2_src_mux_ckti,composite-mux-clock}(y p**clkout2_src_ckti,composite-clock})*++sys_clkout2ti,divider-clock}+@y p~mpu_ckfixed-factor-clock},%0--arm_fckti,divider-clock}-y $emu_mpu_alwon_ckfixed-factor-clock}-%0VVl3_ickti,divider-clock}y @..l4_ickti,divider-clock}.y @//rm_ickti,divider-clock}/y @gpt10_gate_fckti,composite-gate-clock} y 11gpt10_mux_fckti,composite-mux-clock}0y @22gpt10_fckti,composite-clock}12gpt11_gate_fckti,composite-gate-clock} y 33gpt11_mux_fckti,composite-mux-clock}0y @44gpt11_fckti,composite-clock}34core_96m_fckfixed-factor-clock}5%066mmchs2_fckti,wait-gate-clock}6y mmchs1_fckti,wait-gate-clock}6y i2c3_fckti,wait-gate-clock}6y i2c2_fckti,wait-gate-clock}6y i2c1_fckti,wait-gate-clock}6y mcbsp5_gate_fckti,composite-gate-clock}7 y mcbsp1_gate_fckti,composite-gate-clock}7 y core_48m_fckfixed-factor-clock} %088mcspi4_fckti,wait-gate-clock}8y mcspi3_fckti,wait-gate-clock}8y mcspi2_fckti,wait-gate-clock}8y mcspi1_fckti,wait-gate-clock}8y uart2_fckti,wait-gate-clock}8y uart1_fckti,wait-gate-clock}8y  core_12m_fckfixed-factor-clock}9%0::hdq_fckti,wait-gate-clock}:y core_l3_ickfixed-factor-clock}.%0;;sdrc_ickti,wait-gate-clock};y ||gpmc_fckfixed-factor-clock};%0core_l4_ickfixed-factor-clock}/%0<<mmchs2_ickti,omap3-interface-clock}<y mmchs1_ickti,omap3-interface-clock}<y hdq_ickti,omap3-interface-clock}<y mcspi4_ickti,omap3-interface-clock}<y mcspi3_ickti,omap3-interface-clock}<y mcspi2_ickti,omap3-interface-clock}<y mcspi1_ickti,omap3-interface-clock}<y i2c3_ickti,omap3-interface-clock}<y i2c2_ickti,omap3-interface-clock}<y i2c1_ickti,omap3-interface-clock}<y uart2_ickti,omap3-interface-clock}<y uart1_ickti,omap3-interface-clock}<y  gpt11_ickti,omap3-interface-clock}<y  gpt10_ickti,omap3-interface-clock}<y  mcbsp5_ickti,omap3-interface-clock}<y  mcbsp1_ickti,omap3-interface-clock}<y  omapctrl_ickti,omap3-interface-clock}<y dss_tv_fckti,gate-clock}(ydss_96m_fckti,gate-clock}5ydss2_alwon_fckti,gate-clock}ydummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock}y ==gpt1_mux_fckti,composite-mux-clock}0y @>>gpt1_fckti,composite-clock}=>aes2_ickti,omap3-interface-clock}<y wkup_32k_fckfixed-factor-clock}0%0??gpio1_dbckti,gate-clock}?y sha12_ickti,omap3-interface-clock}<y wdt2_fckti,wait-gate-clock}?y wdt2_ickti,omap3-interface-clock}@y wdt1_ickti,omap3-interface-clock}@y gpio1_ickti,omap3-interface-clock}@y omap_32ksync_ickti,omap3-interface-clock}@y gpt12_ickti,omap3-interface-clock}@y gpt1_ickti,omap3-interface-clock}@y per_96m_fckfixed-factor-clock}%0per_48m_fckfixed-factor-clock} %0AAuart3_fckti,wait-gate-clock}Ay ~~gpt2_gate_fckti,composite-gate-clock}yBBgpt2_mux_fckti,composite-mux-clock}0y@CCgpt2_fckti,composite-clock}BCgpt3_gate_fckti,composite-gate-clock}yDDgpt3_mux_fckti,composite-mux-clock}0y@EEgpt3_fckti,composite-clock}DEgpt4_gate_fckti,composite-gate-clock}yFFgpt4_mux_fckti,composite-mux-clock}0y@GGgpt4_fckti,composite-clock}FGgpt5_gate_fckti,composite-gate-clock}yHHgpt5_mux_fckti,composite-mux-clock}0y@IIgpt5_fckti,composite-clock}HIgpt6_gate_fckti,composite-gate-clock}yJJgpt6_mux_fckti,composite-mux-clock}0y@KKgpt6_fckti,composite-clock}JKgpt7_gate_fckti,composite-gate-clock}yLLgpt7_mux_fckti,composite-mux-clock}0y@MMgpt7_fckti,composite-clock}LMgpt8_gate_fckti,composite-gate-clock} yNNgpt8_mux_fckti,composite-mux-clock}0y@OOgpt8_fckti,composite-clock}NOgpt9_gate_fckti,composite-gate-clock} yPPgpt9_mux_fckti,composite-mux-clock}0y@QQgpt9_fckti,composite-clock}PQper_32k_alwon_fckfixed-factor-clock}0%0RRgpio6_dbckti,gate-clock}Rygpio5_dbckti,gate-clock}Rygpio4_dbckti,gate-clock}Rygpio3_dbckti,gate-clock}Rygpio2_dbckti,gate-clock}Ry wdt3_fckti,wait-gate-clock}Ry per_l4_ickfixed-factor-clock}/%0SSgpio6_ickti,omap3-interface-clock}Sygpio5_ickti,omap3-interface-clock}Sygpio4_ickti,omap3-interface-clock}Sygpio3_ickti,omap3-interface-clock}Sygpio2_ickti,omap3-interface-clock}Sy wdt3_ickti,omap3-interface-clock}Sy uart3_ickti,omap3-interface-clock}Sy uart4_ickti,omap3-interface-clock}Sygpt9_ickti,omap3-interface-clock}Sy gpt8_ickti,omap3-interface-clock}Sy gpt7_ickti,omap3-interface-clock}Sygpt6_ickti,omap3-interface-clock}Sygpt5_ickti,omap3-interface-clock}Sygpt4_ickti,omap3-interface-clock}Sygpt3_ickti,omap3-interface-clock}Sygpt2_ickti,omap3-interface-clock}Symcbsp2_ickti,omap3-interface-clock}Symcbsp3_ickti,omap3-interface-clock}Symcbsp4_ickti,omap3-interface-clock}Symcbsp2_gate_fckti,composite-gate-clock}7ymcbsp3_gate_fckti,composite-gate-clock}7ymcbsp4_gate_fckti,composite-gate-clock}7yemu_src_mux_ck ti,mux-clock}TUVy@WWemu_src_ckti,clkdm-gate-clock}WXXpclk_fckti,divider-clock}Xy@pclkx2_fckti,divider-clock}Xy@atclk_fckti,divider-clock}Xy@traceclk_src_fck ti,mux-clock}TUVy@YYtraceclk_fckti,divider-clock}Y y@secure_32k_fck fixed-clockZZgpt12_fckfixed-factor-clock}Z%0wdt1_fckfixed-factor-clock}Z%0security_l4_ick2fixed-factor-clock}/%0[[aes1_ickti,omap3-interface-clock}[y rng_ickti,omap3-interface-clock}[y sha11_ickti,omap3-interface-clock}[y des1_ickti,omap3-interface-clock}[y cam_mclkti,gate-clock}\ykcam_ick!ti,omap3-no-wait-interface-clock}/ycsi2_96m_fckti,gate-clock}6ysecurity_l3_ickfixed-factor-clock}.%0]]pka_ickti,omap3-interface-clock}]y icr_ickti,omap3-interface-clock}<y des2_ickti,omap3-interface-clock}<y mspro_ickti,omap3-interface-clock}<y mailboxes_ickti,omap3-interface-clock}<y ssi_l4_ickfixed-factor-clock}/%0ddsr1_fckti,wait-gate-clock}y sr2_fckti,wait-gate-clock}y sr_l4_ickfixed-factor-clock}/%0dpll2_fckti,divider-clock}y@^^dpll2_ckti,omap3-dpll-clock}^y$@4__dpll2_m2_ckti,divider-clock}_yD``iva2_ckti,wait-gate-clock}`ymodem_fckti,omap3-interface-clock}y sad2d_ickti,omap3-interface-clock}.y mad2d_ickti,omap3-interface-clock}.y mspro_fckti,wait-gate-clock}6y ssi_ssr_gate_fck_3430es2 ti,composite-no-wait-gate-clock}y aassi_ssr_div_fck_3430es2ti,composite-divider-clock}y @$bbssi_ssr_fck_3430es2ti,composite-clock}abccssi_sst_fck_3430es2fixed-factor-clock}c%0hsotgusb_ick_3430es2"ti,omap3-hsotgusb-interface-clock};y }}ssi_ick_3430es2ti,omap3-ssi-interface-clock}dy usim_gate_fckti,composite-gate-clock}5 y oosys_d2_ckfixed-factor-clock}%0ffomap_96m_d2_fckfixed-factor-clock}5%0ggomap_96m_d4_fckfixed-factor-clock}5%0hhomap_96m_d8_fckfixed-factor-clock}5%0iiomap_96m_d10_fckfixed-factor-clock}5%0 jjdpll5_m2_d4_ckfixed-factor-clock}e%0kkdpll5_m2_d8_ckfixed-factor-clock}e%0lldpll5_m2_d16_ckfixed-factor-clock}e%0mmdpll5_m2_d20_ckfixed-factor-clock}e%0nnusim_mux_fckti,composite-mux-clock(}fghijklmny @ppusim_fckti,composite-clock}opusim_ickti,omap3-interface-clock}@y  dpll5_ckti,omap3-dpll-clock}y  $ L 4qqdpll5_m2_ckti,divider-clock}qy Peesgx_gate_fckti,composite-gate-clock}y yycore_d3_ckfixed-factor-clock}%0rrcore_d4_ckfixed-factor-clock}%0sscore_d6_ckfixed-factor-clock}%0ttomap_192m_alwon_fckfixed-factor-clock}%0uucore_d2_ckfixed-factor-clock}%0vvsgx_mux_fckti,composite-mux-clock }rstuvwxy @zzsgx_fckti,composite-clock}yzsgx_ickti,wait-gate-clock}.y cpefuse_fckti,gate-clock}y ts_fckti,gate-clock}0y usbtll_fckti,wait-gate-clock}ey usbtll_ickti,omap3-interface-clock}<y mmchs3_ickti,omap3-interface-clock}<y mmchs3_fckti,wait-gate-clock}6y dss1_alwon_fck_3430es2ti,dss-gate-clock}{ykdss_ick_3430es2ti,omap3-dss-interface-clock}/yusbhost_120m_fckti,gate-clock}eyusbhost_48m_fckti,dss-gate-clock} yusbhost_ickti,omap3-dss-interface-clock}/yclockdomainscore_l3_clkdmti,clockdomain}|}dpll3_clkdmti,clockdomain} dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}~emu_clkdmti,clockdomain}Xdpll4_clkdmti,clockdomain} wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}_d2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}qsgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }scrm@48002000ti,omap3-scrmyH clocksmcbsp5_mux_fckti,composite-mux-clock}67ymcbsp5_fckti,composite-clock}mcbsp1_mux_fckti,composite-mux-clock}67ytmcbsp1_fckti,composite-clock}mcbsp2_mux_fckti,composite-mux-clock}7ytmcbsp2_fckti,composite-clock}mcbsp3_mux_fckti,composite-mux-clock}7ymcbsp3_fckti,composite-clock}mcbsp4_mux_fckti,composite-mux-clock}7ymcbsp4_fckti,composite-clock}clockdomainscounter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap2-intc`yH dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH`  `pinmux@48002030 ti,omap3-padconfpinctrl-singleyH 08(Fcdefaultqpinmux_uart2_pins {<>@Bpinmux_i2c1_pins{pinmux_mmc1_pins0{pinmux_mmc2_pins0{(*,.02pinmux_w3cbw003c_pins{lpinmux_hsusb2_pins@{      pinmux_twl4030_pins{Apinmux_i2c3_pins{pinmux_uart3_pins{nAppinmux_dss_dpi_pins{pinmux@48002a00 ti,omap3-padconfpinctrl-singleyH*\(Fpinmux_twl4030_vpins {tisyscon@48002270sysconyH"ppbias_regulatorti,pbias-omapypbias_mmc_omap2430pbias_mmc_omap2430w@-gpio@48310000ti,omap3-gpioyH1gpio1gpio@49050000ti,omap3-gpioyIgpio2gpio@49052000ti,omap3-gpioyI gpio3gpio@49054000ti,omap3-gpioyI@ gpio4gpio@49056000ti,omap3-gpioyI`!gpio5gpio@49058000ti,omap3-gpioyI"gpio6serial@4806a000ti,omap3-uartyH H12txrxuart1lserial@4806c000ti,omap3-uartyHI34txrxuart2lcdefaultqserial@49020000ti,omap3-uartyIJ56txrxuart3lcdefaultqi2c@48070000 ti,omap3-i2cyH8txrxi2c1cdefaultq'@twl@48yH& ti,twl4030cdefaultqaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci &watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@4regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpioHtwl4030-usbti,twl4030-usb Tbp~pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madci2c@48072000 ti,omap3-i2cyH 9txrxi2c2 disabledi2c@48060000 ti,omap3-i2cyH=txrxi2c3cdefaultq  eeprom@51 atmel,24c01yQlis33de@1dst,lis33dest,lis3lv02dy 1 C U guxx &&( disabledmailbox@48094000ti,omap3-mailboxmailboxyH @spi@48098000ti,omap2-mcspiyH Amcspi17@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspiyH Bmcspi27 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [mcspi37 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&timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5timer@4903a000ti,omap3430-timeryI*timer6timer@4903c000ti,omap3430-timeryI+timer7timer@4903e000ti,omap3430-timeryI,timer8timer@49040000ti,omap3430-timeryI-timer9timer@48086000ti,omap3430-timeryH`.timer10timer@48088000ti,omap3430-timeryH/timer11timer@48304000ti,omap3430-timeryH0@_timer12usbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs ehci-phyohci@48064400ti,ohci-omap3yHD&Lehci@48064800 ti,ehci-omapyHH&M*gpmc@6e000000ti,omap3430-gpmcgpmcyn/;,ethernet@gpmcsmsc,lan9221smsc,lan9115MXjx*$  *$ <6-$<Vm* y&usb_otg_hs@480ab000ti,omap3-musbyH \]mcdma usb_otg_hs&19 BQ* Yusb2-phyc2dss@48050000 ti,omap3-dssyHok dss_core}fckcdefaultqdispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled 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#address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#clock-cellsclock-frequencylinux,phandleti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersinterrupt-controller#interrupt-cellsti,intc-size#dma-cells#dma-channels#dma-requestspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendeddmasdma-namesbci3v1-supplyregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-zti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplyvmmc_aux-supplycap-sdio-irqnon-removableti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-modephysgpmc,num-csgpmc,num-waitpinsbank-widthgpmc,mux-add-datagpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-lineslabelpwmsmax-brightnesslinux,default-triggerti,modelti,mcbspti,codecgpiostartup-delay-usenable-active-highreset-gpiosvcc-supplydigitalddc-i2c-bus