683(3Terasic SoCkit#!altr,socfpga-cyclone5altr,socfpgachosen,console=ttyS0,115200aliases5/soc/ethernet@ff702000?/soc/ethernet@ff702000I/soc/serial0@ffc02000Q/soc/serial1@ffc03000Y/soc/timer0@ffc08000`/soc/timer1@ffc09000g/soc/timer2@ffd00000n/soc/timer3@ffd01000memoryumemory@cpuscpu@0!arm,cortex-a9ucpucpu@1!arm,cortex-a9ucpuintc@fffed000!arm,cortex-a9-gicsoc !simple-bususocamba !arm,amba-buspdma@ffe01000!arm,pl330arm,primecell`hijklmno  apb_pclkcan@ffc00000 !bosch,d_can0 'disabledcan@ffc01000 !bosch,d_can0 'disabledclkmgr@ffd04000 !altr,clk-mgr@clocksosc1. !fixed-clock;}x@osc2. !fixed-clockf2s_periph_ref_clk. !fixed-clock  f2s_sdram_ref_clk. !fixed-clock  main_pll.!altr,socfpga-pll-clock@mpuclk.!altr,socfpga-perip-clk K H  mainclk.!altr,socfpga-perip-clk K Ldbg_base_clk.!altr,socfpga-perip-clk K Pmain_qspi_clk.!altr,socfpga-perip-clkTmain_nand_sdmmc_clk.!altr,socfpga-perip-clkXcfg_h2f_usr0_clk.!altr,socfpga-perip-clk\periph_pll.!altr,socfpga-pll-clock    emac0_clk.!altr,socfpga-perip-clk emac1_clk.!altr,socfpga-perip-clk per_qsi_clk.!altr,socfpga-perip-clk per_nand_mmc_clk.!altr,socfpga-perip-clk per_base_clk.!altr,socfpga-perip-clk h2f_usr1_clk.!altr,socfpga-perip-clk sdram_pll.!altr,socfpga-pll-clock    ddr_dqs_clk.!altr,socfpga-perip-clk ddr_2x_dqs_clk.!altr,socfpga-perip-clk ddr_dq_clk.!altr,socfpga-perip-clk h2f_usr2_clk.!altr,socfpga-perip-clk mpu_periph_clk.!altr,socfpga-perip-clk Smpu_l2_ram_clk.!altr,socfpga-perip-clk Sl4_main_clk.!altr,socfpga-gate-clka`l3_main_clk.!altr,socfpga-perip-clkSl3_mp_clk.!altr,socfpga-gate-clk Kda`l3_sp_clk.!altr,socfpga-gate-clk Kdl4_mp_clk.!altr,socfpga-gate-clk Kda`l4_sp_clk.!altr,socfpga-gate-clk Kda`dbg_at_clk.!altr,socfpga-gate-clk Kha`dbg_clk.!altr,socfpga-gate-clk Kha`dbg_trace_clk.!altr,socfpga-gate-clk Kla`dbg_timer_clk.!altr,socfpga-gate-clka`cfg_clk.!altr,socfpga-gate-clka`h2f_user0_clk.!altr,socfpga-gate-clka` emac_0_clk.!altr,socfpga-gate-clkaemac_1_clk.!altr,socfpga-gate-clkausb_mp_clk.!altr,socfpga-gate-clka Kspi_m_clk.!altr,socfpga-gate-clka Kcan0_clk.!altr,socfpga-gate-clka Kcan1_clk.!altr,socfpga-gate-clka K gpio_db_clk.!altr,socfpga-gate-clka Kh2f_user1_clk.!altr,socfpga-gate-clkasdmmc_clk.!altr,socfpga-gate-clk  ajnand_x_clk.!altr,socfpga-gate-clk  a nand_clk.!altr,socfpga-gate-clk  a Sqspi_clk.!altr,socfpga-gate-clk  a ethernet@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac t`p  smacirq stmmaceth  stmmaceth 'disabledethernet@ff7020000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac t`p  xmacirq stmmaceth! stmmaceth'okayrgmii ("i2c@ffc04000!snps,designware-i2c@  'disabledi2c@ffc05000!snps,designware-i2cP  'disabledi2c@ffc06000!snps,designware-i2c`  'disabledi2c@ffc07000!snps,designware-i2cp  'disabledgpio@ff708000!snps,dw-apb-gpiop 'disabledgpio-controller@0!snps,dw-apb-gpio-port.>J gpio@ff709000!snps,dw-apb-gpiop 'disabledgpio-controller@0!snps,dw-apb-gpio-port.>J gpio@ff70a000!snps,dw-apb-gpiop 'disabledgpio-controller@0!snps,dw-apb-gpio-port.>J l2-cache@fffef000!arm,pl310-cache &Xf r dwmmc0@ff704000!altr,socfpga-dw-mshcp@ biuciuslot@0timer@fffec600!arm,cortex-a9-twd-timer  timer0@ffc08000!snps,dw-apb-timer timertimer1@ffc09000!snps,dw-apb-timer timertimer2@ffd00000!snps,dw-apb-timer timertimer3@ffd01000!snps,dw-apb-timer timerserial0@ffc02000!snps,dw-apb-uart  serial1@ffc03000!snps,dw-apb-uart0 rstmgr@ffd05000 !altr,rst-mgrPusbphy@0!usb-nop-xceiv'okay  usb@ffb00000 !snps,dwc2 }otg  usb2-phy 'disabledusb@ffb40000 !snps,dwc2 otg  usb2-phy'okaywatchdog@ffd02000 !snps,dw-wdt   'disabledwatchdog@ffd03000 !snps,dw-wdt0  'disabledsysmgr@ffd08000!altr,sys-mgrsysconЀ@Ѐ #address-cells#size-cellsmodelcompatiblebootargsethernet0ethernet1serial0serial1timer0timer1timer2timer3device_typeregnext-level-cache#interrupt-cellsinterrupt-controllerlinux,phandleinterrupt-parentrangesinterrupts#dma-cells#dma-channels#dma-requestsclocksclock-namesstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasealtr,sysmgr-sysconinterrupt-namesmac-addressresetsreset-namesphy-modephy-addrrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psgpio-controller#gpio-cellssnps,nr-gpioscache-unifiedcache-levelarm,tag-latencyarm,data-latencyfifo-depthnum-slotssupports-highspeedbroken-cdbus-widthreg-shiftreg-io-width#phy-cellsphysphy-namescpu1-start-addr