N8(pDgumstix,omap3-overo-summitgumstix,omap3-overoti,omap36xxti,omap3&/7OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summitchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000d/ocp/serial@49042000 l/connector@0memoryumemorycpuscpu@0arm,cortex-a8ucpucpus 'O 57pmuarm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp simple-bush l3_mainaes@480c5000 ti,omap3-aesaesH PPprm@48306000 ti,omap3-prmH0`@clocksvirt_16_8m_ck fixed-clockYosc_sys_ck ti,mux-clock @  sys_ckti,divider-clock  psys_clkout1ti,gate-clock  pdpll3_x2_ckfixed-factor-clock -8dpll3_m2x2_ckfixed-factor-clock -8  dpll4_x2_ckfixed-factor-clock -8corex2_fckfixed-factor-clock -8wkup_l4_ickfixed-factor-clock-8@@corex2_d3_fckfixed-factor-clock-8wwcorex2_d5_fckfixed-factor-clock-8xxclockdomainscm@48004000 ti,omap3-cmH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock00virt_12m_ck fixed-clockvirt_13m_ck fixed-clock]@virt_19200000_ck fixed-clock$virt_26000000_ck fixed-clockvirt_38_4m_ck fixed-clockIdpll4_ckti,omap3-dpll-per-j-type-clock D 0  dpll4_m2_ckti,divider-clock  ? Hdpll4_m2x2_mul_ckfixed-factor-clock-8dpll4_m2x2_ckti,hsdiv-gate-clock Bomap_96m_alwon_fckfixed-factor-clock-8dpll3_ckti,omap3-dpll-core-clock @ 0  dpll3_m3_ckti,divider-clock  @dpll3_m3x2_mul_ckfixed-factor-clock-8dpll3_m3x2_ckti,hsdiv-gate-clock  Bemu_core_alwon_ckfixed-factor-clock-8TTsys_altclk fixed-clockmcbsp_clks fixed-clock77dpll3_m2_ckti,divider-clock   @  core_ckfixed-factor-clock -8dpll1_fckti,divider-clock  @dpll1_ckti,omap3-dpll-clock  $ @ 4dpll1_x2_ckfixed-factor-clock-8dpll1_x2m2_ckti,divider-clock  D,,cm_96m_fckfixed-factor-clock-8omap_96m_fck ti,mux-clock @55dpll4_m3_ckti,divider-clock  @dpll4_m3x2_mul_ckfixed-factor-clock-8dpll4_m3x2_ckti,hsdiv-gate-clock Bomap_54m_fck ti,mux-clock @((cm_96m_d2_fckfixed-factor-clock-8omap_48m_fck ti,mux-clock @  omap_12m_fckfixed-factor-clock -899dpll4_m4_ckti,divider-clock  @!!dpll4_m4x2_mul_ckti,fixed-factor-clock!Xfs""dpll4_m4x2_ckti,gate-clock" Bs{{dpll4_m5_ckti,divider-clock  ?@##dpll4_m5x2_mul_ckti,fixed-factor-clock#Xfs$$dpll4_m5x2_ckti,hsdiv-gate-clock$ Bs\\dpll4_m6_ckti,divider-clock  ?@%%dpll4_m6x2_mul_ckfixed-factor-clock%-8&&dpll4_m6x2_ckti,hsdiv-gate-clock& B''emu_per_alwon_ckfixed-factor-clock'-8UUclkout2_src_gate_ck ti,composite-no-wait-gate-clock p))clkout2_src_mux_ckti,composite-mux-clock( p**clkout2_src_ckti,composite-clock)*++sys_clkout2ti,divider-clock+ @ pmpu_ckfixed-factor-clock,-8--arm_fckti,divider-clock- $ emu_mpu_alwon_ckfixed-factor-clock--8VVl3_ickti,divider-clock  @..l4_ickti,divider-clock.  @//rm_ickti,divider-clock/  @gpt10_gate_fckti,composite-gate-clock  11gpt10_mux_fckti,composite-mux-clock0 @22gpt10_fckti,composite-clock12gpt11_gate_fckti,composite-gate-clock  33gpt11_mux_fckti,composite-mux-clock0 @44gpt11_fckti,composite-clock34core_96m_fckfixed-factor-clock5-866mmchs2_fckti,wait-gate-clock6 mmchs1_fckti,wait-gate-clock6 i2c3_fckti,wait-gate-clock6 i2c2_fckti,wait-gate-clock6 i2c1_fckti,wait-gate-clock6 mcbsp5_gate_fckti,composite-gate-clock7  mcbsp1_gate_fckti,composite-gate-clock7  core_48m_fckfixed-factor-clock -888mcspi4_fckti,wait-gate-clock8 mcspi3_fckti,wait-gate-clock8 mcspi2_fckti,wait-gate-clock8 mcspi1_fckti,wait-gate-clock8 uart2_fckti,wait-gate-clock8 uart1_fckti,wait-gate-clock8  core_12m_fckfixed-factor-clock9-8::hdq_fckti,wait-gate-clock: core_l3_ickfixed-factor-clock.-8;;sdrc_ickti,wait-gate-clock; ||gpmc_fckfixed-factor-clock;-8core_l4_ickfixed-factor-clock/-8<<mmchs2_ickti,omap3-interface-clock< mmchs1_ickti,omap3-interface-clock< hdq_ickti,omap3-interface-clock< mcspi4_ickti,omap3-interface-clock< mcspi3_ickti,omap3-interface-clock< mcspi2_ickti,omap3-interface-clock< mcspi1_ickti,omap3-interface-clock< i2c3_ickti,omap3-interface-clock< i2c2_ickti,omap3-interface-clock< i2c1_ickti,omap3-interface-clock< uart2_ickti,omap3-interface-clock< uart1_ickti,omap3-interface-clock<  gpt11_ickti,omap3-interface-clock<  gpt10_ickti,omap3-interface-clock<  mcbsp5_ickti,omap3-interface-clock<  mcbsp1_ickti,omap3-interface-clock<  omapctrl_ickti,omap3-interface-clock< dss_tv_fckti,gate-clock(dss_96m_fckti,gate-clock5dss2_alwon_fckti,gate-clockdummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock ==gpt1_mux_fckti,composite-mux-clock0 @>>gpt1_fckti,composite-clock=>aes2_ickti,omap3-interface-clock< wkup_32k_fckfixed-factor-clock0-8??gpio1_dbckti,gate-clock? sha12_ickti,omap3-interface-clock< wdt2_fckti,wait-gate-clock? wdt2_ickti,omap3-interface-clock@ wdt1_ickti,omap3-interface-clock@ gpio1_ickti,omap3-interface-clock@ omap_32ksync_ickti,omap3-interface-clock@ gpt12_ickti,omap3-interface-clock@ gpt1_ickti,omap3-interface-clock@ per_96m_fckfixed-factor-clock-8per_48m_fckfixed-factor-clock -8AAuart3_fckti,wait-gate-clockA ~~gpt2_gate_fckti,composite-gate-clockBBgpt2_mux_fckti,composite-mux-clock0@CCgpt2_fckti,composite-clockBCgpt3_gate_fckti,composite-gate-clockDDgpt3_mux_fckti,composite-mux-clock0@EEgpt3_fckti,composite-clockDEgpt4_gate_fckti,composite-gate-clockFFgpt4_mux_fckti,composite-mux-clock0@GGgpt4_fckti,composite-clockFGgpt5_gate_fckti,composite-gate-clockHHgpt5_mux_fckti,composite-mux-clock0@IIgpt5_fckti,composite-clockHIgpt6_gate_fckti,composite-gate-clockJJgpt6_mux_fckti,composite-mux-clock0@KKgpt6_fckti,composite-clockJKgpt7_gate_fckti,composite-gate-clockLLgpt7_mux_fckti,composite-mux-clock0@MMgpt7_fckti,composite-clockLMgpt8_gate_fckti,composite-gate-clock NNgpt8_mux_fckti,composite-mux-clock0@OOgpt8_fckti,composite-clockNOgpt9_gate_fckti,composite-gate-clock PPgpt9_mux_fckti,composite-mux-clock0@QQgpt9_fckti,composite-clockPQper_32k_alwon_fckfixed-factor-clock0-8RRgpio6_dbckti,gate-clockRgpio5_dbckti,gate-clockRgpio4_dbckti,gate-clockRgpio3_dbckti,gate-clockRgpio2_dbckti,gate-clockR wdt3_fckti,wait-gate-clockR per_l4_ickfixed-factor-clock/-8SSgpio6_ickti,omap3-interface-clockSgpio5_ickti,omap3-interface-clockSgpio4_ickti,omap3-interface-clockSgpio3_ickti,omap3-interface-clockSgpio2_ickti,omap3-interface-clockS wdt3_ickti,omap3-interface-clockS uart3_ickti,omap3-interface-clockS uart4_ickti,omap3-interface-clockSgpt9_ickti,omap3-interface-clockS gpt8_ickti,omap3-interface-clockS gpt7_ickti,omap3-interface-clockSgpt6_ickti,omap3-interface-clockSgpt5_ickti,omap3-interface-clockSgpt4_ickti,omap3-interface-clockSgpt3_ickti,omap3-interface-clockSgpt2_ickti,omap3-interface-clockSmcbsp2_ickti,omap3-interface-clockSmcbsp3_ickti,omap3-interface-clockSmcbsp4_ickti,omap3-interface-clockSmcbsp2_gate_fckti,composite-gate-clock7mcbsp3_gate_fckti,composite-gate-clock7mcbsp4_gate_fckti,composite-gate-clock7emu_src_mux_ck ti,mux-clockTUV@WWemu_src_ckti,clkdm-gate-clockWXXpclk_fckti,divider-clockX @pclkx2_fckti,divider-clockX @atclk_fckti,divider-clockX @traceclk_src_fck ti,mux-clockTUV@YYtraceclk_fckti,divider-clockY  @secure_32k_fck fixed-clockZZgpt12_fckfixed-factor-clockZ-8wdt1_fckfixed-factor-clockZ-8security_l4_ick2fixed-factor-clock/-8[[aes1_ickti,omap3-interface-clock[ rng_ickti,omap3-interface-clock[ sha11_ickti,omap3-interface-clock[ des1_ickti,omap3-interface-clock[ cam_mclkti,gate-clock\scam_ick!ti,omap3-no-wait-interface-clock/csi2_96m_fckti,gate-clock6security_l3_ickfixed-factor-clock.-8]]pka_ickti,omap3-interface-clock] icr_ickti,omap3-interface-clock< des2_ickti,omap3-interface-clock< mspro_ickti,omap3-interface-clock< mailboxes_ickti,omap3-interface-clock< ssi_l4_ickfixed-factor-clock/-8ddsr1_fckti,wait-gate-clock sr2_fckti,wait-gate-clock sr_l4_ickfixed-factor-clock/-8dpll2_fckti,divider-clock @^^dpll2_ckti,omap3-dpll-clock^$@4__dpll2_m2_ckti,divider-clock_ D``iva2_ckti,wait-gate-clock`modem_fckti,omap3-interface-clock sad2d_ickti,omap3-interface-clock. mad2d_ickti,omap3-interface-clock. mspro_fckti,wait-gate-clock6 ssi_ssr_gate_fck_3430es2 ti,composite-no-wait-gate-clock aassi_ssr_div_fck_3430es2ti,composite-divider-clock @$bbssi_ssr_fck_3430es2ti,composite-clockabccssi_sst_fck_3430es2fixed-factor-clockc-8hsotgusb_ick_3430es2"ti,omap3-hsotgusb-interface-clock; }}ssi_ick_3430es2ti,omap3-ssi-interface-clockd usim_gate_fckti,composite-gate-clock5  oosys_d2_ckfixed-factor-clock-8ffomap_96m_d2_fckfixed-factor-clock5-8ggomap_96m_d4_fckfixed-factor-clock5-8hhomap_96m_d8_fckfixed-factor-clock5-8iiomap_96m_d10_fckfixed-factor-clock5-8 jjdpll5_m2_d4_ckfixed-factor-clocke-8kkdpll5_m2_d8_ckfixed-factor-clocke-8lldpll5_m2_d16_ckfixed-factor-clocke-8mmdpll5_m2_d20_ckfixed-factor-clocke-8nnusim_mux_fckti,composite-mux-clock(fghijklmn @ppusim_fckti,composite-clockopusim_ickti,omap3-interface-clock@  dpll5_ckti,omap3-dpll-clock  $ L 4qqdpll5_m2_ckti,divider-clockq  Peesgx_gate_fckti,composite-gate-clock yycore_d3_ckfixed-factor-clock-8rrcore_d4_ckfixed-factor-clock-8sscore_d6_ckfixed-factor-clock-8ttomap_192m_alwon_fckfixed-factor-clock-8uucore_d2_ckfixed-factor-clock-8vvsgx_mux_fckti,composite-mux-clock rstuvwx @zzsgx_fckti,composite-clockyzsgx_ickti,wait-gate-clock. cpefuse_fckti,gate-clock ts_fckti,gate-clock0 usbtll_fckti,wait-gate-clocke usbtll_ickti,omap3-interface-clock< mmchs3_ickti,omap3-interface-clock< mmchs3_fckti,wait-gate-clock6 dss1_alwon_fck_3430es2ti,dss-gate-clock{sdss_ick_3430es2ti,omap3-dss-interface-clock/usbhost_120m_fckti,gate-clockeusbhost_48m_fckti,dss-gate-clock usbhost_ickti,omap3-dss-interface-clock/uart4_fckti,wait-gate-clockAclockdomainscore_l3_clkdmti,clockdomain|}dpll3_clkdmti,clockdomain dpll1_clkdmti,clockdomainper_clkdmti,clockdomainl~emu_clkdmti,clockdomainXdpll4_clkdmti,clockdomain wkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomain_d2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainqsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain scrm@48002000ti,omap3-scrmH clocksmcbsp5_mux_fckti,composite-mux-clock67mcbsp5_fckti,composite-clockmcbsp1_mux_fckti,composite-mux-clock67tmcbsp1_fckti,composite-clockmcbsp2_mux_fckti,composite-mux-clock7tmcbsp2_fckti,composite-clockmcbsp3_mux_fckti,composite-mux-clock7mcbsp3_fckti,composite-clockmcbsp4_mux_fckti,composite-mux-clock7mcbsp4_fckti,composite-clockclockdomainscounter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap2-intc`H dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`   "`pinmux@48002030 ti,omap3-padconfpinctrl-singleH 080Nkdefaultypinmux_uart2_pins <>@Bpinmux_i2c1_pinspinmux_mmc1_pins0pinmux_mmc2_pins0(*,.02pinmux_w3cbw003c_pinslpinmux_hsusb2_pins@      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regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@<regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpioPtwl4030-usbti,twl4030-usb \jxpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madci2c@48072000 ti,omap3-i2cH 9$txrxi2c2 disabledi2c@48060000 ti,omap3-i2cH=$txrxi2c3kdefaultyeeprom@51 atmel,24c01Qlis33de@1dst,lis33dest,lis3lv02d'9 K ] o}xx&!&0 disabledmailbox@48094000ti,omap3-mailboxmailboxH @spi@48098000ti,omap2-mcspiH Amcspi1?@#$%&'()* $tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspiH Bmcspi2? +,-.$tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [mcspi3? $tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0mcspi4?FG$tx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1M=>$txrxZkdefaultygsmmc@480b4000ti,omap3-hsmmcH @Vmmc2/0$txrxkdefaultyg}smmc@480ad000ti,omap3-hsmmcH ^mmc3MN$txrx disabledmmu@480bd400ti,omap2-iommuH mmu_ispmmu@5d000000ti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< commontxrxmcbsp1 $txrx disabledmcbsp@49022000ti,omap3-mcbspI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"$txrx disabledmcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetone$txrx disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 commontxrxmcbsp4$txrx disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR commontxrxmcbsp5$txrx disabledsham@480c3000ti,omap3-shamshamH 0d1smartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaH timer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI 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gpio-ledskdefaulty heartbeatovero:red:gpio21  !heartbeat #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3display0device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#clock-cellsclock-frequencylinux,phandleti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersinterrupt-controller#interrupt-cellsti,intc-size#dma-cells#dma-channels#dma-requestspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendeddmasdma-namesbci3v1-supplyregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-zti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplyvmmc_aux-supplycap-sdio-irqnon-removableti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-modephysgpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-lines#address-cellti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infolabelpwmsmax-brightnesslinux,default-triggerti,modelti,mcbspti,codecgpiostartup-delay-usenable-active-highreset-gpiosvcc-supplydigitalddc-i2c-bus