8X(r 6compulab,omap5-sbc-t54compulab,omap5-cm-t54ti,omap5&7CompuLab SBC-T54 with CM-T54chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@4807a000Q/ocp/i2c@4807c000V/ocp/serial@4806a000^/ocp/serial@4806c000f/ocp/serial@48020000n/ocp/serial@4806e000v/ocp/serial@48066000~/ocp/serial@48068000memorymemorycpuscpu@0cpuarm,cortex-a15B@,`cpu cpu@1cpuarm,cortex-a15thermal-zonescpu_thermal+9tripscpu_alertIUpassive cpu_critIHU criticalcooling-mapsmap0` egpu_thermal+9tripsgpu_critIHU criticalcore_thermal+9tripscore_critIHU criticaltimerarm,armv7-timer0t   pmuarm,cortex-a15-pmutinterrupt-controller@48211000arm,cortex-a15-gic H!H! H!@ H!`  socti,omap-inframpu ti,omap5-mpumpuocpti,omap4-l3-nocsimple-busl3_main_1l3_main_2l3_main_3D D0E@t  prm@4ae06000 ti,omap5-prmJ`0clockssys_clkin ti,mux-clock  abe_dpll_bypass_clk_mux ti,mux-clock abe_dpll_clk_mux ti,mux-clock  custefuse_sys_gfclk_divfixed-factor-clockdss_syc_gfclk_divfixed-factor-clock( (wkupaon_iclk_mux ti,mux-clock l3instr_ts_gclk_divfixed-factor-clockgpio1_dbclkti,gate-clock8timer1_gfclk_mux ti,mux-clock@clockdomainscm_core_aon@4a004000ti,omap5-cm-core-aonJ@ clockspad_clks_src_ck fixed-clock pad_clks_ckti,gate-clock+ +secure_32k_clk_src_ck fixed-clockslimbus_src_clk fixed-clock slimbus_clkti,gate-clock % %sys_32k_ck fixed-clock virt_12000000_ck fixed-clock virt_13000000_ck fixed-clock]@ virt_16800000_ck fixed-clockY  virt_19200000_ck fixed-clock$  virt_26000000_ck fixed-clock  virt_27000000_ck fixed-clock  virt_38400000_ck fixed-clockI  xclk60mhsp1_ck fixed-clockW Wxclk60mhsp2_ck fixed-clockY Ydpll_abe_ckti,omap4-dpll-m4xen-clock dpll_abe_x2_ckti,omap4-dpll-x2-clock dpll_abe_m2x2_ckti,divider-clock  abe_24m_fclkfixed-factor-clock' 'abe_clkti,divider-clock & &abe_iclkti,divider-clock(-abe_lp_clk_divfixed-factor-clock dpll_abe_m3x2_ckti,divider-clock  dpll_core_ckti,omap4-dpll-core-clock $,( dpll_core_x2_ckti,omap4-dpll-x2-clock dpll_core_h21x2_ckti,divider-clock ?P c2c_fclkfixed-factor-clock c2c_iclkfixed-factor-clockdpll_core_h11x2_ckti,divider-clock ?8dpll_core_h12x2_ckti,divider-clock ?< dpll_core_h13x2_ckti,divider-clock ?@dpll_core_h14x2_ckti,divider-clock ?D\ \dpll_core_h22x2_ckti,divider-clock ?Tdpll_core_h23x2_ckti,divider-clock ?Xdpll_core_h24x2_ckti,divider-clock ?\dpll_core_m2_ckti,divider-clock 0dpll_core_m3x2_ckti,divider-clock 40 0iva_dpll_hs_clk_divfixed-factor-clock  dpll_iva_ckti,omap4-dpll-clock ! !dpll_iva_x2_ckti,omap4-dpll-x2-clock!" "dpll_iva_h11x2_ckti,divider-clock" ?dpll_iva_h12x2_ckti,divider-clock" ?mpu_dpll_hs_clk_divfixed-factor-clock# #dpll_mpu_ckti,omap5-mpu-dpll-clock#`dlh dpll_mpu_m2_ckti,divider-clock pper_dpll_hs_clk_divfixed-factor-clockF Fusb_dpll_hs_clk_divfixed-factor-clockK Kl3_iclk_divfixed-factor-clock$ $gpu_l3_iclkfixed-factor-clock$l4_root_clk_divfixed-factor-clock$slimbus1_slimbus_clkti,gate-clock% `aess_fclkti,divider-clock& ( dmic_sync_mux_ck ti,mux-clock '()8* *dmic_gfclk ti,mux-clock *+%8mcasp_sync_mux_ck ti,mux-clock '()@, ,mcasp_gfclk ti,mux-clock ,+%@mcbsp1_sync_mux_ck ti,mux-clock '()H- -mcbsp1_gfclk ti,mux-clock -+%Hmcbsp2_sync_mux_ck ti,mux-clock '()P. .mcbsp2_gfclk ti,mux-clock .+%Pmcbsp3_sync_mux_ck ti,mux-clock '()X/ /mcbsp3_gfclk ti,mux-clock /+%Xtimer5_gfclk_mux ti,mux-clock(htimer6_gfclk_mux ti,mux-clock(ptimer7_gfclk_mux ti,mux-clock(xtimer8_gfclk_mux ti,mux-clock(dummy_ck fixed-clockclockdomainsscrm@4ae0a000ti,omap5-scrmJ clocksauxclk0_src_gate_ck ti,composite-no-wait-gate-clock02 2auxclk0_src_mux_ckti,composite-mux-clock 013 3auxclk0_src_ckti,composite-clock234 4auxclk0_ckti,divider-clock4 A Aauxclk1_src_gate_ck ti,composite-no-wait-gate-clock05 5auxclk1_src_mux_ckti,composite-mux-clock 016 6auxclk1_src_ckti,composite-clock567 7auxclk1_ckti,divider-clock7 B Bauxclk2_src_gate_ck ti,composite-no-wait-gate-clock08 8auxclk2_src_mux_ckti,composite-mux-clock 019 9auxclk2_src_ckti,composite-clock89: :auxclk2_ckti,divider-clock: C Cauxclk3_src_gate_ck ti,composite-no-wait-gate-clock0; ;auxclk3_src_mux_ckti,composite-mux-clock 01< <auxclk3_src_ckti,composite-clock;<= =auxclk3_ckti,divider-clock= D Dauxclk4_src_gate_ck ti,composite-no-wait-gate-clock0 > >auxclk4_src_mux_ckti,composite-mux-clock 01 ? ?auxclk4_src_ckti,composite-clock>?@ @auxclk4_ckti,divider-clock@  E Eauxclkreq0_ck ti,mux-clockABCDEauxclkreq1_ck ti,mux-clockABCDEauxclkreq2_ck ti,mux-clockABCDEauxclkreq3_ck ti,mux-clockABCDEclockdomainscm_core@4a008000ti,omap5-cm-coreJ0clocksdpll_per_ckti,omap4-dpll-clockF@DLHG Gdpll_per_x2_ckti,omap4-dpll-x2-clockGH Hdpll_per_h11x2_ckti,divider-clockH ?XM Mdpll_per_h12x2_ckti,divider-clockH ?\R Rdpll_per_h14x2_ckti,divider-clockH ?d] ]dpll_per_m2_ckti,divider-clockG PO Odpll_per_m2x2_ckti,divider-clockH PN Ndpll_per_m3x2_ckti,divider-clockH T1 1dpll_unipro1_ckti,omap4-dpll-clock I Idpll_unipro1_clkdcoldofixed-factor-clockIT Tdpll_unipro1_m2_ckti,divider-clockI U Udpll_unipro2_ckti,omap4-dpll-clockJ Jdpll_unipro2_clkdcoldofixed-factor-clockJdpll_unipro2_m2_ckti,divider-clockJ dpll_usb_ckti,omap4-dpll-j-type-clockKL Ldpll_usb_clkdcoldofixed-factor-clockL[ [dpll_usb_m2_ckti,divider-clockL P Pfunc_128m_clkfixed-factor-clockM^ ^func_12m_fclkfixed-factor-clockNfunc_24m_clkfixed-factor-clockO) )func_48m_fclkfixed-factor-clockNQ Qfunc_96m_fclkfixed-factor-clockNS Sl3init_60m_fclkti,divider-clockP-V Vdss_32khz_clkti,gate-clock  dss_48mhz_clkti,gate-clockQ   dss_dss_clkti,gate-clockR 9} }dss_sys_clkti,gate-clock(  ~ ~gpio2_dbclkti,gate-clock`gpio3_dbclkti,gate-clockhgpio4_dbclkti,gate-clockpgpio5_dbclkti,gate-clockxgpio6_dbclkti,gate-clockgpio7_dbclkti,gate-clockgpio8_dbclkti,gate-clockiss_ctrlclkti,gate-clockS lli_txphy_clkti,gate-clockT lli_txphy_ls_clkti,gate-clockU  mmc1_32khz_clkti,gate-clock(sata_ref_clkti,gate-clock| |usb_host_hs_hsic480m_p1_clkti,gate-clockP Xusb_host_hs_hsic480m_p2_clkti,gate-clockPXusb_host_hs_hsic480m_p3_clkti,gate-clockPXusb_host_hs_hsic60m_p1_clkti,gate-clockV Xusb_host_hs_hsic60m_p2_clkti,gate-clockV Xusb_host_hs_hsic60m_p3_clkti,gate-clockVXutmi_p1_gfclk ti,mux-clockVWXX Xusb_host_hs_utmi_p1_clkti,gate-clockXXutmi_p2_gfclk ti,mux-clockVYXZ Zusb_host_hs_utmi_p2_clkti,gate-clockZ Xusb_host_hs_utmi_p3_clkti,gate-clockV Xusb_otg_ss_refclk960mti,gate-clock[v vusb_phy_cm_clk32kti,gate-clock@u uusb_tll_hs_usb_ch0_clkti,gate-clockVhusb_tll_hs_usb_ch1_clkti,gate-clockV husb_tll_hs_usb_ch2_clkti,gate-clockV hfdif_fclkti,divider-clockM (gpu_core_gclk_mux ti,mux-clock\] gpu_hyd_gclk_mux ti,mux-clock\] hsi_fclkti,divider-clockN 8mmc1_fclk_mux ti,mux-clock^N(_ _mmc1_fclkti,divider-clock_ (mmc2_fclk_mux ti,mux-clock^N0` `mmc2_fclkti,divider-clock` 0timer10_gfclk_mux ti,mux-clock(timer11_gfclk_mux ti,mux-clock0timer2_gfclk_mux ti,mux-clock8timer3_gfclk_mux ti,mux-clock@timer4_gfclk_mux ti,mux-clockHtimer9_gfclk_mux ti,mux-clockPclockdomainsl3init_clkdmti,clockdomainLcounter@4ae04000ti,omap-counter32kJ@@ counter_32kpinmux@4a002840 ti,omap4-padconfpinctrl-singleJ(@Ljdefaultabpinmux_led_gpio_pinspa apinmux_i2c1_pinsd dpinmux_mmc1_pins0i ipinmux_mmc2_pinsP  m mpinmux_mmc3_pins0dfhjlno opinmux_wlan_gpios_pins\^p ppinmux_usbhost_pins0hvb bpinmux_i2c4_pinsf fpinmux_mmc1_aux_pins46j jpinmux@4ae0c840 ti,omap4-padconfpinctrl-singleJ@8Ljtisyscon@4a002da0sysconJ-c cpbias_regulatorti,pbias-omap`cpbias_mmc_omap5pbias_mmc_omap5w@-h hdma-controller@4a056000ti,omap4430-sdmaJ`0t   g ggpio@4ae10000ti,omap4-gpioJ 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/disableddmic@4012e000ti,omap4-dmic@Impudma trdmicRgCWup_link /disabledmcbsp@40122000ti,omap4-mcbsp@ I mpudma tcommonmcbsp1Rg!g"Wtxrx /disabledmcbsp@40124000ti,omap4-mcbsp@@I@mpudma tcommonmcbsp2RggWtxrx /disabledmcbsp@40126000ti,omap4-mcbsp@`I`mpudma tcommonmcbsp3RggWtxrx /disabledmailbox@4a0f4000ti,omap4-mailboxJ@ tmailboxtimer@4ae18000ti,omap5430-timerJ t%timer1"timer@48032000ti,omap5430-timerH  t&timer2timer@48034000ti,omap5430-timerH@ t'timer3timer@48036000ti,omap5430-timerH` t(timer4timer@40138000ti,omap5430-timer@I t)timer51>timer@4013a000ti,omap5430-timer@I t*timer61>timer@4013c000ti,omap5430-timer@I t+timer71timer@4013e000ti,omap5430-timer@I t,timer81>timer@4803e000ti,omap5430-timerH t-timer9>timer@48086000ti,omap5430-timerH` t.timer10>timer@48088000ti,omap5430-timerH t/timer11>wdt@4ae14000ti,omap5-wdtti,omap3-wdtJ@ tP wd_timer2dmm@4e000000 ti,omap5-dmmN tqdmmemif@4c000000 ti,emif-4d5emif1K^L tng~emif@4d000000 ti,emif-4d5emif2K^M tog~control-phy@4a002300ti,control-phy-usb2J#powert tcontrol-phy@4a002370ti,control-phy-pipe3J#ppowerw womap_dwc3@4a020000ti,dwc3 usb_otg_ssJ t]dwc3@4a030000 snps,dwc3J t\rsusb2-phyusb3-phy peripheralocp2scp@4a080000ti,omap-ocp2scpJ  ocp2scp1usb2phy@4a084000 ti,omap-usb2J@|tuvwkupclkrefclkr rusb3phy@4a084400 ti,omap-usb3JDJHdJL@phy_rxphy_txpll_ctrlw uvwkupclksysclkrefclks susbhstll@4a062000 ti,usbhs-tllJ  tN usb_tll_hsusbhshost@4a064000ti,usbhs-hostJ@ usb_host_hs VWY3refclk_60m_intrefclk_60m_ext_p1refclk_60m_ext_p2 ehci-hsic ehci-hsicohci@4a064800ti,ohci-omap3JH& tLehci@4a064c00 ti,ehci-omapJL& tM xybandgap@4a0021e0 J! J#, J#,J#< t~ti,omap5430-bandgap control-phy@4a002374ti,control-phy-pipe3J#tpowersysclkz zocp2scp@4a090000ti,omap-ocp2scpJ  ocp2scp3phy@4a096000ti,phy-pipe3-sataJ `J ddJ h@phy_rxphy_txpll_ctrlzsysclk{ {sata@4a141100snps,dwc-ahciJJ t6{ sata-phy|satadss@58000000 ti,omap5-dssX /disabled dss_core}fckdispc@58001000ti,omap5-dispcX t dss_dispc}fckencoder@58004000 ti,omap5-dsiX@XB@XC@protophypll t5 /disabled dss_dsi1}~ fcksys_clkencoder@58005000 ti,omap5-dsiXX@X@protophypll t7 /disabled dss_dsi2}~ fcksys_clkencoder@58060000ti,omap5-hdmi XXXXwppllphycore te /disabled dss_hdmi~ fcksys_clkRgL Waudio_txfixed-regulator-mmcsdregulator-fixed vmmcsd_fixed2Z2Zn nfixed-regulator-vwlan-pdnregulator-fixedvwlan_pdn_fixed2Z2Z $ ) fixed-regulator-vwlanregulator-fixed vwlan_fixed2Z2Z $)q qhsusb2_phyusb-nop-xceiv < x xhsusb3_phyusb-nop-xceiv <y yleds gpio-ledsled@1 HHeartbeat  Nheartbeatdoff #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3serial4serial5device_typeregoperating-pointsclocksclock-namesclock-latencycooling-min-levelcooling-max-level#cooling-cellscpu0-supplylinux,phandlepolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceinterruptsinterrupt-controller#interrupt-cellsti,hwmodsranges#clock-cellsti,index-starts-at-oneclock-multclock-divti,bit-shiftclock-frequencyti,max-divti,index-power-of-twoti,dividersti,set-rate-parentpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#dma-cells#dma-channels#dma-requeststi,gpio-always-ongpio-controller#gpio-cellsgpmc,num-csgpmc,num-waitpinspagesizeti,system-power-controllerti,enable-vbus-detectionti,enable-id-detectionti,wakeupinterrupt-nameti,ldo6-vibratorregulator-always-onregulator-boot-onti,smps-rangestartup-delay-usstatus#hwlock-cellsti,spi-num-csdmasdma-namesti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthcd-invertedwp-invertedcd-gpioswp-gpiosti,non-removableti,iommu-bus-err-backreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,no-idle-on-initphy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertutmi-modephysphy-namesdr_modetx-fifo-resizectrl-module#phy-cellsport2-modeport3-mode#thermal-sensor-cellsvin-supplygpioenable-active-highreset-gpioslabellinux,default-triggerdefault-state