*8(P wm,wm8650&Wondermedia WM8650-MID Tabletchosenaliases,/soc/serial@d82000004/soc/serial@d82b0000memory?pinctrl@d8110000wm,wm8650-pinctrlHdypmc@d8130000via,vt8500-pmcHclocksref25M fixed-clock}x@ref24M fixed-clockn6pllawm,wm8650-pll-clockHpllbwm,wm8650-pll-clockHpllcwm,wm8650-pll-clockHplldwm,wm8650-pll-clockH pllewm,wm8650-pll-clockHarmvia,vt8500-device-clockahbvia,vt8500-device-clockapbvia,vt8500-device-clock ddrvia,vt8500-device-clockuart0via,vt8500-device-clockP  uart1via,vt8500-device-clockP  sdhcvia,vt8500-device-clock(?Ttimer@d8130100via,vt8500-timerH($ehci@d8007900via,vt8500-ehciHy+uhci@d8007b00platform-uhciH{+sdhc@d800a000wm,wm8505-sdhcHfb@d8050800 wm,wm8505-fbH*display-timings9800x480E MU(bXnx  ge_rops@d8050400wm,prizm-ge-ropsHserial@d8200000via,vt8500-uartH @  okayserial@d82b0000via,vt8500-uartH+@!  disabledrtc@d8100000via,vt8500-rtcH0ethernet@d8004000via,vt8500-rhineH@  #address-cells#size-cellscompatiblemodelserial0serial1device_typeregrangesinterrupt-parentinterrupt-controller#interrupt-cellslinux,phandleinterruptsgpio-controller#gpio-cells#clock-cellsclock-frequencyclocksdivisor-regenable-regenable-bitdivisor-maskbus-widthsdon-invertedbits-per-pixelnative-modehactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenstatus