L8I(NId ,Freescale i.MX8QM MEK2fsl,imx8qm-mekfsl,imx8qmaliases=/bus@5b000000/mmc@5b010000B/bus@5b000000/mmc@5b020000G/bus@5b000000/mmc@5b030000L/bus@5a000000/serial@5a060000T/bus@5a000000/serial@5a070000\/bus@5a000000/serial@5a080000d/bus@5a000000/serial@5a090000cpus cpu@0lcpu2arm,cortex-a53x|psci@@cpu@1lcpu2arm,cortex-a53x|psci@@cpu@2lcpu2arm,cortex-a53x|psci@@cpu@3lcpu2arm,cortex-a53x|psci@@l2-cache02cache@l2-cache12cache@interrupt-controller@51a00000 2arm,gic-v3PxQQ R RR - pmu2arm,armv8-pmuv3 -psci 2arm,psci-1.0smctimer2arm,armv8-timer0-   system-controller 2fsl,imx-scu 8tx0rx0gip3$Cpower-controller2fsl,imx8qm-scu-pdfsl,scu-pdJclock-controller2fsl,imx8qm-clkfsl,scu-clk^ pinctrl2fsl,imx8qm-iomuxcfec1grpk              lpuart0grpk   usdhc1grpkA!!!!!!!!!Ausdhc2grpTkA!!!!!!rtc2fsl,imx8qxp-sc-rtcbus@58000000 2simple-bus tXXclock-img-ipg 2fixed-clock^{  img_ipg_clkjpegdec@58400000xX@0-5678peripg (%2nxp,imx8qm-jpgdecnxp,imx8qxp-jpgdecjpegenc@58450000xXE0-1234peripg (%2nxp,imx8qm-jpgdecnxp,imx8qxp-jpgencclock-controller@585d00002fsl,imx8qxp-lpcgxX]^0img_jpeg_dec_lpcg_clkimg_jpeg_dec_lpcg_ipg_clkclock-controller@585f00002fsl,imx8qxp-lpcgxX_^0img_jpeg_enc_lpcg_clkimg_jpeg_enc_lpcg_ipg_clkbus@5a000000 2simple-bus tZZclock-dma-ipg 2fixed-clock^{' dma_ipg_clkserial@5a060000xZ - ipgbaud9okay%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartdefault serial@5a070000xZ -   ipgbaud: disabled%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartserial@5a080000xZ -   ipgbaud; disabled%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartserial@5a090000xZ  -   ipgbaud< disabled%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartclock-controller@5a4600002fsl,imx8qxp-lpcgxZF^ 9'uart0_lpcg_baud_clkuart0_lpcg_ipg_clk9clock-controller@5a4700002fsl,imx8qxp-lpcgxZG^ :'uart1_lpcg_baud_clkuart1_lpcg_ipg_clk: clock-controller@5a4800002fsl,imx8qxp-lpcgxZH^ ;'uart2_lpcg_baud_clkuart2_lpcg_ipg_clk; clock-controller@5a4900002fsl,imx8qxp-lpcgxZI^ <'uart3_lpcg_baud_clkuart3_lpcg_ipg_clk< i2c@5a800000xZ@ -peripg  `n6` disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a810000xZ@ -peripg  an6a disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a820000xZ@ -peripg  bn6b disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a830000xZ@ -peripg  cn6c disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2cclock-controller@5ac000002fsl,imx8qxp-lpcgxZ^ ` i2c0_lpcg_clki2c0_lpcg_ipg_clk`clock-controller@5ac100002fsl,imx8qxp-lpcgxZ^ a i2c1_lpcg_clki2c1_lpcg_ipg_clkaclock-controller@5ac200002fsl,imx8qxp-lpcgxZ^ b i2c2_lpcg_clki2c2_lpcg_ipg_clkbclock-controller@5ac300002fsl,imx8qxp-lpcgxZ^ c i2c3_lpcg_clki2c3_lpcg_ipg_clkcclock-controller@5a4a00002fsl,imx8qxp-lpcgxZJ^ ='uart4_lpcg_baud_clkuart4_lpcg_ipg_clk=bus@5b000000 2simple-bus t[[clock-conn-axi 2fixed-clock^{CU conn_axi_clkclock-conn-ahb 2fixed-clock^{ ! conn_ahb_clkclock-conn-ipg 2fixed-clock^{ conn_ipg_clkmmc@5b010000 -x[ ipgahbperokay32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhcdefault!)mmc@5b020000 -x[ ipgahbper7Lokay32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhcdefault\ h qmmc@5b030000 -x[ ipgahbper disabled32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhcethernet@5b040000x[0-  ipgahbenet_clk_refptp  沀sY@zokay2fsl,imx8qm-fecfsl,imx6sx-fecdefault rgmii-idmdio ethernet-phy@02ethernet-phy-ieee802.3-c22xethernet-phy@12ethernet-phy-ieee802.3-c22xethernet@5b050000x[0-  ipgahbenet_clk_refptp  沀sY@z disabled2fsl,imx8qm-fecfsl,imx6sx-fecclock-controller@5b2000002fsl,imx8qxp-lpcgx[ ^  9sdhc0_lpcg_per_clksdhc0_lpcg_ipg_clksdhc0_lpcg_ahb_clkclock-controller@5b2100002fsl,imx8qxp-lpcgx[!^  9sdhc1_lpcg_per_clksdhc1_lpcg_ipg_clksdhc1_lpcg_ahb_clkclock-controller@5b2200002fsl,imx8qxp-lpcgx["^  9sdhc2_lpcg_per_clksdhc2_lpcg_ipg_clksdhc2_lpcg_ahb_clkclock-controller@5b2300002fsl,imx8qxp-lpcgx[#^0    enet0_lpcg_timer_clkenet0_lpcg_txc_sampling_clkenet0_lpcg_ahb_clkenet0_lpcg_rgmii_txc_clkenet0_lpcg_ipg_clkenet0_lpcg_ipg_s_clkclock-controller@5b2400002fsl,imx8qxp-lpcgx[$^0    enet1_lpcg_timer_clkenet1_lpcg_txc_sampling_clkenet1_lpcg_ahb_clkenet1_lpcg_rgmii_txc_clkenet1_lpcg_ipg_clkenet1_lpcg_ipg_s_clkbus@5d000000 2simple-bus t]]clock-lsio-mem 2fixed-clock^{  lsio_mem_clkclock-lsio-bus 2fixed-clock^{ lsio_bus_clk gpio@5d080000x] -2fsl,imx8qm-gpiofsl,imx35-gpiogpio@5d090000x]  -2fsl,imx8qm-gpiofsl,imx35-gpiogpio@5d0a0000x]  -2fsl,imx8qm-gpiofsl,imx35-gpiogpio@5d0b0000x]  -2fsl,imx8qm-gpiofsl,imx35-gpiogpio@5d0c0000x]  -2fsl,imx8qm-gpiofsl,imx35-gpiogpio@5d0d0000x]  -2fsl,imx8qm-gpiofsl,imx35-gpiogpio@5d0e0000x] -2fsl,imx8qm-gpiofsl,imx35-gpiogpio@5d0f0000x] -2fsl,imx8qm-gpiofsl,imx35-gpiomailbox@5d1b0000x] - disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1c0000x] -,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1d0000x] - disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1e0000x] - disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1f0000x] - disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d200000x]  - disabled2fsl,imx8qm-mufsl,imx6sx-mumailbox@5d210000x]! - disabled2fsl,imx8qm-mufsl,imx6sx-mumailbox@5d280000x]( -2fsl,imx8qm-mufsl,imx6sx-muclock-controller@5d4000002fsl,imx8qxp-lpcgx]@^4    hpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clkclock-controller@5d4100002fsl,imx8qxp-lpcgx]A^4    hpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clkclock-controller@5d4200002fsl,imx8qxp-lpcgx]B^4    hpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clkclock-controller@5d4300002fsl,imx8qxp-lpcgx]C^4    hpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clkclock-controller@5d4400002fsl,imx8qxp-lpcgx]D^4    hpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clkclock-controller@5d4500002fsl,imx8qxp-lpcgx]E^4    hpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clkclock-controller@5d4600002fsl,imx8qxp-lpcgx]F^4    hpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clkclock-controller@5d4700002fsl,imx8qxp-lpcgx]G^4    hpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clkchosen/bus@5a000000/serial@5a060000memory@80000000lmemoryx@usdhc2-vmmc2regulator-fixed SD1_SPWR-- 6; interrupt-parent#address-cells#size-cellsmodelcompatiblemmc0mmc1mmc2serial0serial1serial2serial3device_typeregenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecache-levelphandle#interrupt-cellsinterrupt-controllerinterruptsmbox-namesmboxes#power-domain-cells#clock-cellsfsl,pinsrangesclock-frequencyclock-output-namesclocksclock-namesassigned-clocksassigned-clock-ratespower-domainsclock-indicesstatuspinctrl-namespinctrl-0bus-widthno-sdno-sdionon-removablefsl,tuning-start-tapfsl,tuning-stepvmmc-supplycd-gpioswp-gpiosfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetgpio-controller#gpio-cells#mbox-cellsstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltgpioenable-active-high