Ð þí_¶8YÔ(âYœMarvell Armada CN9130-CRB-A>!marvell,cn9130marvell,armada-ap807-quadmarvell,armada-ap807aliases ,/soc/bus@f0000000/serial@512000 4/soc/bus@f0000000/serial@5121005usb-phy-1!usb-nop-xceivòé.usb-phy-2!usb-nop-xceivòj>é/regulator-3!regulator-gpio  cp0_sd_vccqw@32Z  5Kw@2Z é6regulator-4!regulator-fixed  cp0_sd_vcc2Z 32Z  e5Rué7sfp!sff,sfp‰? ‘=  = ª= » Ê ¸é) #address-cells#size-cellsmodelcompatibleserial0serial1gpio0spi0gpio1gpio2spi1spi2i2c0ethernet0ethernet1ethernet2methodrangesregno-mapinterrupt-parentinterruptsdma-coherent#iommu-cells#global-interruptsstatusphandle#interrupt-cellsinterrupt-controllermsi-controllerarm,msi-base-spiarm,msi-num-spismarvell,odmi-framesmarvell,spi-basemarvell,spi-rangesmsi-parentclocksreg-shiftreg-io-widthclock-namesmarvell,xenon-phy-slow-modebus-widthmmc-ddr-1_8vvqmmc-supplymarvell,pinsmarvell,functionoffsetngpiosgpio-controller#gpio-cellsgpio-rangesmarvell,pwm-offset#pwm-cells#clock-cells#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistypetripcooling-devicedevice_typeenable-method#cooling-cellsi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecache-levelcache-unifiedmarvell,system-controllerinterrupt-namesport-idgop-port-idphy-modemanagedphysphy#phy-cellsdsa,memberlabelphy-handlesfpethernetreg-namesinterrupts-extendedusb-phyphy-namespinctrl-namespinctrl-0spi-max-frequencyclock-frequencycd-gpiosvmmc-supplybus-rangeinterrupt-map-maskinterrupt-mapnum-lanesnum-viewportiommu-mapiommu-map-maskstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltstatesenable-active-highgpiovcc-supplyregulator-always-oni2c-busmod-def0-gpioslos-gpiostx-disable-gpiostx-fault-gpiosmaximum-power-milliwatt