'G8$H($ xiaomi,ax3000tmediatek,mt7981b +7Xiaomi AX3000Tcpus+cpu@0arm,cortex-a53=AcpuMpscicpu@1arm,cortex-a53=AcpuMpscioscillator-40m fixed-clock[bZkclkxtal~psci arm,psci-1.0Tsmcreserved-memory+wo-boot@15194000=@wo-ilm@151e0000=wo-dlm@151e8000= secmon@43000000=Cwmcpu-reserved@47c80000=Gwo-emi@47d80000=G wo-data@47dc0000=G$soc simple-bus+interrupt-controller@c000000 arm,gic-v3 =      clock-controller@10001000 mediatek,mt7981-infracfgsyscon=~clock-controller@1001b000 mediatek,mt7981-topckgensyscon=~watchdog@1001c000mediatek,mt7986-wdt= nclock-controller@1001e000mediatek,mt7981-apmixedsys=~pwm@10048000mediatek,mt7981-pwm=( topmainpwm1pwm2pwm3syscon@10060000"mediatek,mt7981-sgmiisys_0syscon=~syscon@10070000"mediatek,mt7981-sgmiisys_1syscon=~serial@11002000*mediatek,mt7981-uartmediatek,mt6577-uart=  { uartwakeup baudbus default %disabledserial@11003000*mediatek,mt7981-uartmediatek,mt6577-uart=0 | uartwakeup  baudbus %disabledserial@11004000*mediatek,mt7981-uartmediatek,mt6577-uart=@ } uartwakeup! baudbus %disabledi2c@11007000mediatek,mt7981-i2c =p!p  34maindmaarbpmic+ %disabledspi@11009000)mediatek,mt7981-spi-ipmmediatek,spi-ipm=  N"# parent-clksel-clkspi-clkhclk+ %disabledspi@1100a000)mediatek,mt7981-spi-ipmmediatek,spi-ipm=  N') parent-clksel-clkspi-clkhclk+ %disabledspi@1100b000)mediatek,mt7981-spi-ipmmediatek,spi-ipm=  N(* parent-clksel-clkspi-clkhclk+ %disabledthermal@1100c8000mediatek,mt7981-thermalmediatek,mt7986-thermal= 0 thermauxadc,8calibration-dataI_oadc@1100d000.mediatek,mt7981-auxadcmediatek,mt7986-auxadc=0main %disabledusb@11200000'mediatek,mt7986-xhcimediatek,mtk-xhci = . > macippc(7856k$sys_ckref_ckmcu_ckdma_ckxhci_ck   %disabledpcie@11280000*mediatek,mt7981-pciemediatek,mt8192-pcie=(@ pcie-mac  9:;<!pl_250mtl_26mperi_26mtop_133mApci  pcie-phy `    + %disabledinterrupt-controller pinctrl@11d00000mediatek,mt7981-pinctrl=Igpioiocfg_rtiocfg_rmiocfg_rbiocfg_lbiocfg_bliocfg_tmiocfg_tleint   9 uart0-pinsmuxuart uart0topmisc@11d10000mediatek,mt7981-topmiscsyscon=~ t-phy@11e10000.mediatek,mt7981-tphymediatek,generic-tphy-v2+ %disabledusb-phy@0=lrefusb-phy@700= dref   efuse@11f20000%mediatek,mt7981-efusemediatek,efuse=+soc-uuid@140=@thermal-calib@274=t phy-calib@8dc=clock-controller@15000000mediatek,mt7981-ethsyssyscon=~wed@15010000mediatek,mt7981-wedsyscon= 1 %?wo-emiwo-ilmwo-dlmwo-datawo-bootSethernet@15100000mediatek,mt7981-eth=d`at"x@]^fegp2gp1wocpu0sgmii_cksgmii_tx250msgmii_rx250msgmii_cdr_refsgmii_cdr_fbsgmii2_tx250msgmii2_rx250msgmii2_cdr_refsgmii2_cdr_fbnetsys0netsys1`(fe0fe1fe2fe3pdma0pdma1pdma2pdma3  %disabledmdio-bus+ethernet-phy@0ethernet-phy-ieee802.3-c22=gmii, 8phy-cal-datasram@15140000 mmio-sram=+syscon@151a5000mediatek,mt7986-wo-ccifsyscon=P wifi@18000000mediatek,mt7981-wmac0=00_\ mcuap2conn1consys %disabledtimerarm,armv8-timer 0   memory@40000000=@Amemory compatibleinterrupt-parent#address-cells#size-cellsmodelregdevice_typeenable-methodclock-frequencyclock-output-names#clock-cellsrangesno-mapphandleinterruptsinterrupt-controller#interrupt-cells#reset-cellsclocksclock-names#pwm-cellsinterrupt-namespinctrl-namespinctrl-0statusnvmem-cellsnvmem-cell-names#thermal-sensor-cellsmediatek,auxadcmediatek,apmixedsys#io-channel-cellsreg-namesphysbus-rangephy-namesinterrupt-map-maskinterrupt-mapgpio-rangesgpio-controller#gpio-cellsfunctiongroups#phy-cellsmediatek,syscon-typememory-regionmemory-region-namesmediatek,wo-ccifassigned-clocksassigned-clock-parentssrammediatek,ethsysmediatek,sgmiisysmediatek,infracfgmediatek,wedphy-modephy-is-integratedresetsreset-names