8(P$mediatek,mt8186-evbmediatek,mt8186 +!7MediaTek MT8186 evaluation board =embeddedaliasesJ/soc/ovl@14005000O/soc/ovl@14006000W/soc/rdma@14007000]/soc/rdma@1401f000c/soc/serial@11002000fhctl@1000ce00mediatek,mt8186-fhctlk r vdisabledccimediatek,mt8186-ccik}cciintermediate"opp-table-ccioperating-points-v2opp-500000000e 'opp-560000000!` Lopp-612000000$za opp-682000000(~  opp-752000000,Ҝ YF opp-8220000000  opp-8750000004'p  opp-9270000007@ 5 opp-980000000:i ~>opp-1050000000> opp-1120000000B )$opp-1155000000D opp-1190000000F opp-1260000000K~opp-1330000000OF0)opp-1400000000SrNRopp-table-cluster0operating-points-v2opp-500000000e 'opp-774000000."M Lopp-8750000004'p `opp-975000000:Q  opp-1075000000@2 q opp-1175000000F  X opp-1275000000K 5 opp-1375000000Q  opp-1500000000Yh/ opp-1618000000`p Yopp-1666000000cM$ opp-1733000000gK{@Hopp-1800000000kI~opp-1866000000o8opp-1933000000s7=@Zopp-2000000000w5Ropp-table-cluster1operating-points-v2#opp-774000000."M Lopp-8350000001 opp-9190000006 opp-1002000000;N YF opp-1085000000@@ X opp-1169000000E@ 5 opp-1308000000M  opp-1419000000T8 Y opp-1530000000[1 topp-1670000000c-Zopp-1733000000gK{@opp-1796000000k sopp-1860000000nYԼopp-1923000000r6dopp-1986000000v_vopp-2050000000z0cpus+cpu-mapcluster0core0core1core2core3core4core5core6core7cpu@0cpuarm,cortex-a55rpsciw5k}cpuintermediate T'~: JW@iv@!"cpu@100cpuarm,cortex-a55rpsciw5k}cpuintermediate T'~: JW@iv@!"cpu@200cpuarm,cortex-a55rpsciw5k}cpuintermediate T'~: JW@iv@!"cpu@300cpuarm,cortex-a55rpsciw5k}cpuintermediate T'~: JW@iv@!"cpu@400cpuarm,cortex-a55rpsciw5k}cpuintermediate T'~: JW@iv@!"cpu@500cpuarm,cortex-a55rpsciw5k}cpuintermediate T'~: JW@iv@!"cpu@600cpuarm,cortex-a76rpsciz0k}cpuintermediate# O':$%JW@iv@&"cpu@700cpuarm,cortex-a76rpsciz0k}cpuintermediate# O':$%JW@iv@&"idle-statespscicpu-retention-larm,idle-state2d%@cpu-retention-barm,idle-state2d%x$cpu-off-larm,idle-stated%4 cpu-off-barm,idle-stated%l%l2-cache0cache6LY@k'B!l2-cache1cache6LY@k'B&l3-cachecache6LY@kB'fixed-factor-clock-13mfixed-factor-clockPk(]grclk13m5oscillator-26m fixed-clockPrclk26m(oscillator-32k fixed-clockPrclk32kopp-table-gpuoperating-points-v2Nopp-299000000` Xopp-332000000 hopp-366000000з <opp-400000000ׄ Ҧopp-434000000P zopp-484000000A 4Nopp-535000000s }opp-586000000" `opp-637000000%@ 4opp-690000000)  @opp-743000000,IG opp-796000000/q opp-8500000002 5opp-900000000-35 Popp-900000000-45 |opp-900000000-55  opp-950000000-38ـ opp-950000000-48ـ Yopp-950000000-58ـ P opp-1000000000-3;~opp-1000000000-4; topp-1000000000-5; Y pmu-a55arm,cortex-a55-pmu )pmu-a76arm,cortex-a76-pmu *psci arm,psci-1.0smctimerarm,armv8-timer @   soc+ simple-businterrupt-controller@c000000 arm,gic-v3  r    ppi-partitionsinterrupt-partition-0)interrupt-partition-1*syscon@c53a000mediatek,mt8186-mcusyssysconr SPsyscon@10000000 mediatek,mt8186-topckgensysconrP,syscon@10001000#mediatek,mt8186-infracfg_aosysconrP-syscon@10003000mediatek,mt8186-pericfgsysconr0Ipinctrl@10005000mediatek,mt8186-pinctrlrP "$&*,Biocfg0iocfg_ltiocfg_lmiocfg_lbiocfg_bliocfg_rbiocfg_rteint %++i2c0-default-pins:pins-bus18E]i2c1-default-pins;pins-bus18E]i2c2-default-pins<pins-bus18E]i2c3-default-pins=pins-bus18E]i2c4-default-pins>pins-bus18E]i2c5-default-pins?pins-bus18E]i2c6-default-pins@pins-bus1jE]i2c7-default-pinsApins-bus18E]i2c8-default-pinsBpins-bus18E]i2c9-default-pinsFpins-bus1jE]syscon@10006000)mediatek,mt8186-scpsyssysconsimple-mfdr`power-controller!mediatek,mt8186-power-controller+w8power-domain@0rk,}mfg00+wpower-domain@1r-+wpower-domain@2rwpower-domain@3rwpower-domain@17rk,,$}subsys-csirx-top0subsys-csirx-top1wpower-domain@4rk,-=}sys_ckref_ckwpower-domain@5rk-B-?}sys_ckref_ckwpower-domain@18rk,/,>}audioadspsubsys-adsp-bus+wpower-domain@19r+wpower-domain@20r-wpower-domain@16r-wpower-domain@6r0k,*,+. ...M}dispmdpsubsys-smi-infrasubsys-smi-commonsubsys-smi-galssubsys-smi-iommu-+wpower-domain@14rk,)/ }vdec0larb-wpower-domain@10r 8k,,,, 0,#,%6}cam0cam1cam2cam3galssubsys-cam-tmsubsys-cam-top-+wpower-domain@12r wpower-domain@11r wpower-domain@7rk1,&}galssubsys-img-top-+wpower-domain@8rwpower-domain@9r (k,'2222P}subsys-ipe-topsubsys-ipe-larb0subsys-ipe-larb1subsys-ipe-smisubsys-ipe-gals-wpower-domain@13r k,$3}venc0subsys-larb-wpower-domain@15rk,:44%}wpe0subsys-larb-cksubsys-larb-pclk-wwatchdog@10007000mediatek,mt8186-wdtrpGsyscon@1000c000"mediatek,mt8186-apmixedsyssysconrPpwrap@1000d000mediatek,mt8186-pwrapsysconrpwrapk-- }spiwrapspmi@10015000*mediatek,mt8186-spmimediatek,mt8195-spmi rP pmifspmimstk--,2(}pmif_sys_ckpmif_tmr_ckspmimst_clk_mux,2,t  vdisabledtimer@10017000,mediatek,mt8186-timermediatek,mt6765-timerrpk5mailbox@1022c000mediatek,mt8186-gcer"@k-}gceOscp@10500000mediatek,mt8186-scp rP\ sramcfgbadsp@10680000mediatek,mt8186-dsp@rh hhcfgsramsecbusk,/,>}audiodspadsp_bus,/,> (,Erxtx678 vdisabledmailbox@10686100mediatek,mt8186-adsp-mboxrhai6mailbox@10687100mediatek,mt8186-adsp-mboxrhqj7spi@11000000mediatek,mt8186-norr k,3-O-c-d}spisfaxiaxi_s,3,X% vdisabledadc@11001000.mediatek,mt8186-auxadcmediatek,mt8173-auxadcrk-"}mainserial@11002000*mediatek,mt8186-uartmediatek,mt6577-uartr p k(- }baudbusvokayserial@11003000*mediatek,mt8186-uartmediatek,mt6577-uartr0q k(- }baudbus vdisabledi2c@11007000mediatek,mt8186-i2c rp ik9-' }maindma]+vokaydefault(:i2c@11008000mediatek,mt8186-i2c r jk9-' }maindma]+vokay2@default(;i2c@11009000mediatek,mt8186-i2c r kk9-' }maindma]+vokay2'default(<i2c@1100f000mediatek,mt8186-i2c r lk9-' }maindma]+vokaydefault(=i2c@11011000mediatek,mt8186-i2c r mk9-' }maindma]+vokaydefault(>i2c@11016000mediatek,mt8186-i2c r` bk9-' }maindma]+vokaydefault(?i2c@1100d000mediatek,mt8186-i2c r ck9-' }maindma]+vokaydefault(@i2c@11004000mediatek,mt8186-i2c r@ nk9-' }maindma]+vokaydefault(Ai2c@11005000mediatek,mt8186-i2c rP ok9-' }maindma]+vokaydefault(Bspi@1100a000(mediatek,mt8186-spimediatek,mt6765-spi+rk,K, -}parent-clksel-clkspi-clk vdisabledthermal-sensor@1100b000mediatek,mt8186-lvtsrck- L-SCD$_lvts-calib-data-1lvts-calib-data-2pfsvs@1100bc00mediatek,mt8186-svsrk- }mainSEC(_svs-calibration-datat-calibration-dataL-svs_rstpwm@1100e0002mediatek,mt8186-disp-pwmmediatek,mt8183-disp-pwmrk,-4}mainmm vdisabledspi@11010000(mediatek,mt8186-spimediatek,mt6765-spi+rk,K, -8}parent-clksel-clkspi-clk vdisabledspi@11012000(mediatek,mt8186-spimediatek,mt6765-spi+r k,K, -;}parent-clksel-clkspi-clk vdisabledspi@11013000(mediatek,mt8186-spimediatek,mt6765-spi+r0k,K, -<}parent-clksel-clkspi-clk vdisabledspi@11014000(mediatek,mt8186-spimediatek,mt6765-spi+r@tk,K, -J}parent-clksel-clkspi-clk vdisabledspi@11015000(mediatek,mt8186-spimediatek,mt6765-spi+rPuk,K, -K}parent-clksel-clkspi-clk vdisabledclock-controller@11017000mediatek,mt8186-imp_iic_wraprpP9serial@11018000*mediatek,mt8186-uartmediatek,mt6577-uartr k(- }baudbus vdisabledi2c@11019000mediatek,mt8186-i2c r dk9 -' }maindma]+vokaydefault(Faudio-controller@11210000mediatek,mt8186-soundr! k-,-6,,,F, , ,,e,,h,?,@,A,B,C,,,,,,,(}}aud_infra_clkmtkaif_26m_clktop_mux_audiotop_mux_audio_inttop_mainpll_d2_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d8top_mux_aud_eng2top_apll2_d8top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s4_m_seltop_tdm_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div4top_apll12_div_tdmtop_mux_audio_htop_clk26m_clk-,LG audiosys vdisabledusb@11201000#mediatek,mt8186-mtu3mediatek,mtu3 r - > macippc(k,-=-3-->$}sys_ckref_ckmcu_ckdma_ckxhci_ck/H8+ I  vdisabledusb@11200000'mediatek,mt8186-xhcimediatek,mtk-xhcir mac(k,-=-3-->$}sys_ckref_ckmcu_ckdma_ckxhci_ck& vdisabledmmc@11230000(mediatek,mt8186-mmcmediatek,mt8183-mmc r# k, --U-}sourcehclksource_cgcryptod,  vdisabledmmc@11240000(mediatek,mt8186-mmcmediatek,mt8183-mmc r$k,--V}sourcehclksource_cge,,o vdisabledusb@11281000#mediatek,mt8186-mtu3mediatek,mtu3 r(-(> macippc$k-B-?-7(-@$}sys_ckref_ckmcu_ckdma_ckxhci_ckKJK8+ I$ vdisabledusb@11280000'mediatek,mt8186-xhcimediatek,mtk-xhcir(mac$k-B-?-7(-@$}sys_ckref_ckmcu_ckdma_ckxhci_ckD vdisabledt-phy@11c80000.mediatek,mt8186-tphymediatek,generic-tphy-v2+vokayusb-phy@0rk(}refJusb-phy@700r k(}refKt-phy@11ca0000.mediatek,mt8186-tphymediatek,generic-tphy-v2+vokayusb-phy@0rk(}refHefuse@11cb0000%mediatek,mt8186-efusemediatek,efuser+lvts1-calib@1ccrClvts2-calib@2f8rDcalib@550rPPEgpu-speedbin@59crMsocinfo-data1@7a0rdsi-phy@11cc0000mediatek,mt8183-mipi-txrk(P rmipi_tx0_pll vdisabledRclock-controller@13000000mediatek,mt8186-mfgsysrPLgpu@13040000&mediatek,mt8186-maliarm,mali-bifrostr@kL0  jobmmugpu88 core0core1SM _speed-binN O vdisabledksyscon@14000000mediatek,mt8186-mmsyssysconrPOO0O.mutex@14001000mediatek,mt8186-disp-mutexrk.'0OH8smi@14002000mediatek,mt8186-smi-commonr  k....}apbsmigals0gals18Psmi@14003000mediatek,mt8186-smi-larbr0k..}apbsmi\mP8Ssmi@14004000mediatek,mt8186-smi-larbr@k..}apbsmi\mP8Tovl@140050002mediatek,mt8186-disp-ovlmediatek,mt8192-disp-ovlrPk.)zQ0OP8ovl@140060008mediatek,mt8186-disp-ovl-2lmediatek,mt8192-disp-ovl-2lr`k.*zQ!0O`8rdma@140070004mediatek,mt8186-disp-rdmamediatek,mt8183-disp-rdmarpk.+zQ"0Op8color@140090006mediatek,mt8186-disp-colormediatek,mt8173-disp-colorrk. -0O8dpi@1400a000mediatek,mt8186-dpirk,;. }pixelenginepll,;,j58 vdisabledportendpointccorr@1400b0006mediatek,mt8186-disp-ccorrmediatek,mt8192-disp-ccorrrk..0O8aal@1400c0002mediatek,mt8186-disp-aalmediatek,mt8183-disp-aalrk.00O8gamma@1400d0006mediatek,mt8186-disp-gammamediatek,mt8183-disp-gammark. 10O8postmask@1400e000<mediatek,mt8186-disp-postmaskmediatek,mt8192-disp-postmaskrk. 20O8dither@1400f0008mediatek,mt8186-disp-dithermediatek,mt8183-disp-ditherrk.30O8dsi@14013000mediatek,mt8186-dsir0k..R}enginedigitalhs78L.Rdphy vdisabledportendpointiommu@14016000mediatek,mt8186-iommu-mmr`k.}bclk98STUVWXYZ[\]^_`8Qrdma@1401f0004mediatek,mt8186-disp-rdmamediatek,mt8183-disp-rdmark.4zQ 0O8clock-controller@14020000mediatek,mt8186-wpesysrP4smi@14023000mediatek,mt8186-smi-larbr0k44}apbsmi\mP8Xclock-controller@15020000mediatek,mt8186-imgsys1rP1smi@1502e000mediatek,mt8186-smi-larbrk11}apbsmi\ mP8Yclock-controller@15820000mediatek,mt8186-imgsys2rPasmi@1582e000mediatek,mt8186-smi-larbrk1a}apbsmi\ mP8Zvideo-decoder@16000000mediatek,mt8186-vcodec-decr+@zQbvideo-codec@16025000mediatek,mtk-vcodec-corerPW`zQQQQQQQQQQQQ k,)//,U%}vdec-selvdec-soc-vdecvdecvdec-top,),U8smi@1602e000mediatek,mt8186-smi-larbrk//}apbsmi\mP8Vclock-controller@1602f000mediatek,mt8186-vdecsysrP/clock-controller@17000000mediatek,mt8186-vencsysrP3smi@17010000mediatek,mt8186-smi-larbrk33}apbsmi\mP8 Wvideo-encoder@170200006mediatek,mt8186-vcodec-encmediatek,mt8183-vcodec-encr HzQQQQQQQQQk3 }venc_sel,$,U8 bjpeg-encoder@17030000+mediatek,mt8186-jpgencmediatek,mtk-jpgencrk3}jpgenc zQQQQ8 clock-controller@1a000000mediatek,mt8186-camsysrP0smi@1a001000mediatek,mt8186-smi-larbrk00}apbsmi\ mP8 [smi@1a002000mediatek,mt8186-smi-larbr k00}apbsmi\mP8 \smi@1a00f000mediatek,mt8186-smi-larbrk0c}apbsmi\mP8 ]smi@1a010000mediatek,mt8186-smi-larbrk0d}apbsmi\mP8 ^clock-controller@1a04f000mediatek,mt8186-camsys_rawarPcclock-controller@1a06f000mediatek,mt8186-camsys_rawbrPdclock-controller@1b000000mediatek,mt8186-mdpsysrPesmi@1b002000mediatek,mt8186-smi-larbr kee}apbsmi\mP8Uclock-controller@1c000000mediatek,mt8186-ipesysrP2smi@1c00f000mediatek,mt8186-smi-larbrk22}apbsmi\mP8 `smi@1c10f000mediatek,mt8186-smi-larbrk22}apbsmi\mP8 _thermal-zonescpu-little0-thermalftripstrip-alert0LEpassivegtrip-alert1sEhottrip-crit Ecriticalcooling-mapsmap0gHcpu-little1-thermalftripstrip-alert0LEpassivehtrip-alert1sEhottrip-crit Ecriticalcooling-mapsmap0hHcpu-little2-thermalftripstrip-alert0LEpassiveitrip-alert1sEhottrip-crit Ecriticalcooling-mapsmap0iHcam-thermalftripstrip-alert0LEpassivetrip-alert1sEhottrip-crit Ecriticalnna-thermalftripstrip-alert0LEpassivetrip-alert1sEhottrip-crit Ecriticaladsp-thermalftripstrip-alert0LEpassivetrip-alert1sEhottrip-crit Ecriticalgpu-thermalftripstrip-alert0LEpassivejtrip-alert1sEhottrip-crit Ecriticalcooling-mapsmap0j kcpu-big0-thermaldftripstrip-alert0LEpassiveltrip-alert1sEhottrip-crit Ecriticalcooling-mapsmap0lcpu-big1-thermaldftripstrip-alert0LEpassivemtrip-alert1sEhottrip-crit Ecriticalcooling-mapsmap0mchosenserial0:921600n8memory@40000000memoryr@regulator-vproc12regulator-fixedvproc12.BTOlO compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeovl0ovl-2l0rdma0rdma1serial0clocksregstatusclock-namesoperating-points-v2proc-supplyphandleopp-sharedopp-hzopp-microvoltrequired-oppscpudevice_typeenable-methodclock-frequencydynamic-power-coefficientcapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsmediatek,ccientry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-divclock-multclock-output-namesopp-supported-hwinterruptsdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-disabledrive-strength-microampinput-enablebias-pull-up#power-domain-cellsmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#mbox-cellsmbox-namesmboxespower-domains#io-channel-cellspinctrl-namespinctrl-0i2c-scl-internal-delay-nsresetsnvmem-cellsnvmem-cell-names#thermal-sensor-cellsreset-names#pwm-cellsmediatek,apmixedsysmediatek,topckgenphyswakeup-sourcemediatek,syscon-wakeup#phy-cellsmediatek,discthbitsinterrupt-namespower-domain-namesmediatek,gce-client-regmediatek,gce-eventsmediatek,larb-idmediatek,smiiommusphy-namesmediatek,larbs#iommu-cellsmediatek,scppolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvolt