8{(%{`google,dojo-sku7google,dojo-sku5google,dojo-sku3google,dojo-sku1google,dojomediatek,mt8195 +7HP Dojo (sku 1, 3, 5, 7) board =convertiblealiasesJ/soc/dp-intf@1c015000S/soc/dp-intf@1c113000\/soc/dpi@1c112000a/soc/mailbox@10320000f/soc/mailbox@10330000k/soc/hdmi-tx@1c300000q/soc/hdr-engine@1c114000x/soc/mutex@1c016000/soc/mutex@1c101000/soc/vpp-merge@1c10c000/soc/vpp-merge@1c10d000/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/i2c@11e00000/soc/i2c@11e01000 /soc/i2c@11e02000/soc/i2c@11e03000/soc/i2c@11e04000/soc/i2c@11d00000/soc/i2c@11d02000$/soc/mmc@11230000)/soc/mmc@11240000./soc/serial@11001100cpus+cpu@06cpuarm,cortex-a55BFpsciThec3@x4@@ cpu@1006cpuarm,cortex-a55BFpsciThec3@x4@@ cpu@2006cpuarm,cortex-a55BFpsciThec3@x4@@ cpu@3006cpuarm,cortex-a55BFpsciThec3@x4@@cpu@4006cpuarm,cortex-a78BFpsciThfx@@  cpu@5006cpuarm,cortex-a78BFpsciThfx@@  cpu@6006cpuarm,cortex-a78BFpsciThfx@@  cpu@7006cpuarm,cortex-a78BFpsciThfx@@  cpu-mapcluster0core0& core1& core2& core3&core4&core5&core6&core7&idle-states*pscicpu-retention-larm,idle-state7N_2p_Dcpu-retention-barm,idle-state7N_-pcpu-off-larm,idle-state7N_7pHcpu-off-barm,idle-state7N_2pl2-cache0cache@l2-cache1cache@ l3-cachecache @dsu-pmu arm,dsu-pmu  faildmic-codec dmic-codec2mt8195-soundokay}DL10_FEDPTX_BEETDM1_IN_BEETDM2_IN_BEETDM1_OUT_BEETDM2_OUT_BEUL_SRC1_BEAFE_SOF_DL2AFE_SOF_DL3AFE_SOF_UL4AFE_SOF_UL5default[)HeadphoneHPOLHeadphoneHPORIN1PHeadset MicRight SpkRight BE_OUTLeft SpkLeft BE_OUT'mediatek,mt8195_mt6359_max98390_rt56827m8195_m98390_5682smm-dai-link 7ETDM1_IN_BEAcpuhs-playback-dai-link 7ETDM1_OUT_BEAcpucodecWhs-capture-dai-link 7ETDM2_IN_BEAcpucodecWspk-playback-dai-link 7ETDM2_OUT_BEAcpucodecWdisplayport-dai-link7DPTX_BEcodecWfixed-factor-clock-13mfixed-factor-clockanuclk13m3oscillator-26m fixed-clockahclk26moscillator-32k fixed-clockahclk32kperformance-controller@11bc10mediatek,cpufreq-hw B 0 opp-table-gpuoperating-points-v2~opp-390000000> hopp-410000000p opp-431000000 opp-4730000001h@ <opp-515000000F <opp-556000000!# Ҧopp-598000000# opp-640000000&% opp-670000000'c opp-700000000)' Lopp-730000000+ }opp-760000000-L `opp-790000000/q 4opp-82000000005 opp-8500000002 @opp-8800000004s qpmu-a55arm,cortex-a55-pmu pmu-a78arm,cortex-a78-pmu psci arm,psci-1.0Msmctimerarm,armv8-timer @   soc+ simple-businterrupt-controller@c000000 arm,gic-v3  B    &ppi-partitionsinterrupt-partition-0F interrupt-partition-1Fsyscon@10000000 mediatek,mt8195-topckgensysconBa"syscon@10001000#mediatek,mt8195-infracfg_aosysconBaO#syscon@10003000mediatek,mt8195-pericfgsysconB0aIpinctrl@10005000mediatek,mt8195-pinctrlBPB\iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintfvdefault>I2S_SPKR_MCLKI2S_SPKR_DATAINI2S_SPKR_LRCKI2S_SPKR_BCLKEC_AP_INT_ODLAP_FLASH_WP_LTCHPAD_INT_ODLEDP_HPD_1V8AP_I2C_CAM_SDAAP_I2C_CAM_SCLAP_I2C_TCHPAD_SDA_1V8AP_I2C_TCHPAD_SCL_1V8AP_I2C_AUD_SDAAP_I2C_AUD_SCLAP_I2C_TPM_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_TCHSCR_SCL_1V8EC_AP_HPD_ODPCIE_NVME_RST_LPCIE_NVME_CLKREQ_ODLPCIE_RST_1V8_LPCIE_CLKREQ_1V8_ODLPCIE_WAKE_1V8_ODLCLK_24M_CAM0CAM1_SEN_ENAP_I2C_PWR_SCL_1V8AP_I2C_PWR_SDA_1V8AP_I2C_MISC_SCLAP_I2C_MISC_SDAEN_PP5000_HDMI_XAP_HDMITX_HTPLGAP_HDMITX_SCL_1V8AP_HDMITX_SDA_1V8AP_RTC_CLK32KAP_EC_WATCHDOG_LSRCLKENA0SRCLKENA1PWRAP_SPI0_CS_LPWRAP_SPI0_CKPWRAP_SPI0_MOSIPWRAP_SPI0_MISOSPMI_SCLSPMI_SDAI2S_HP_DATAINI2S_HP_MCLKI2S_HP_BCKI2S_HP_LRCKI2S_HP_DATAOUTSD_CD_ODLEN_PP3300_DISP_XTCHSCR_RST_1V8_LTCHSCR_REPORT_DISABLEEN_PP3300_WLAN_XBT_KILL_1V8_LI2S_SPKR_DATAOUTWIFI_KILL_1V8_LBEEP_ONSCP_I2C_SENSOR_SCL_1V8SCP_I2C_SENSOR_SDA_1V8AUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_DAT_MISO0AUD_DAT_MISO1AUD_DAT_MISO2SCP_VREQ_VAOAP_SPI_GSC_TPM_CLKAP_SPI_GSC_TPM_MOSIAP_SPI_GSC_TPM_CS_LAP_SPI_GSC_TPM_MISOEN_PP1000_CAM_XAP_EDP_BKLTENUSB3_HUB_RST_LWLAN_ALERT_ODLEC_IN_RW_ODLGSC_AP_INT_ODLHP_INT_ODLCAM0_RST_LCAM1_RST_LTCHSCR_INT_1V8_LCAM1_DET_LRST_ALC1011_LBL_PWM_1V8UART_AP_TX_DBG_RXUART_DBG_TX_AP_RXEN_SPKRAP_EC_WARM_RST_REQUART_SCP_TX_DBGCON_RXUART_DBGCON_TX_SCP_RXKPCOL0MT6315_GPU_INTMT6315_PROC_BC_INTSD_CMDSD_CLKSD_DAT0SD_DAT1SD_DAT2SD_DAT3EMMC_DAT7EMMC_DAT6EMMC_DAT5EMMC_DAT4EMMC_RSTBEMMC_CMDEMMC_CLKEMMC_DAT3EMMC_DAT2EMMC_DAT1EMMC_DAT0EMMC_DSLMT6360_INT_ODLSCP_JTAG0_TRSTNAP_SPI_EC_CS_LAP_SPI_EC_CLKAP_SPI_EC_MOSIAP_SPI_EC_MISOSCP_JTAG0_TMSSCP_JTAG0_TCKSCP_JTAG0_TDOSCP_JTAG0_TDIAP_SPI_FLASH_CS_LAP_SPI_FLASH_CLKAP_SPI_FLASH_MOSIAP_SPI_FLASH_MISOaudio-default-pinspins-cmd-datDEFGHIJK<12345pins-hp-jack-int-odlYecr50-irq-default-pinsmpins-gsc-ap-int-odlXcros-ec-irq-default-pins?pins-ec-ap-int-odleedptx-default-pinspins-cmd-datdisp-pwm0-default-pinsCpins-disp-pwmRadptx-default-pinspins-cmd-dati2c0-default-pinsepins-bus i2c1-default-pinsfpins-bus  i2c2-default-pinsipins-bus  i2c3-default-pinslpins-busi2c4-default-pinsnpins-busi2c5-default-pinsapins-busi2c7-default-pinsbpins-busmmc0-default-pinsLpins-cmd-dat$~}|{wvutyepins-clkzfpins-rstxemmc0-uhs-pinsMpins-cmd-dat$~}|{wvutyepins-clkzfpins-dsfpins-rstxemmc1-detect-pinsQpins-insert6mmc1-default-pinsPpins-cmd-datnpqrsepins-clkofnor-default-pins_pins-ck-io pins-cspcie0-default-pins[pins-bus pcie1-default-pins^pins-bus panel-pwr-default-pinspins-vreg-en7pio-default-pinspins-wifi-enable:&pins-low-power-pd,./0ABCDpins-low-power-pupd<MNOPSUZ[]^_`hikepins-low-power-hdmi-disable  !pins-low-power-hdmi-rsel-disable"#$rt1019p-default-pinspins-amp-sdbd2scp-default-pins5pins-vreqLspi0-default-pins>pins-cs-mosi-clk pins-misosubpmic-default-pinscpins-subpmic-int-ntrackpad-default-pinsgpins-int-ntouchscreen-default-pinsopins-int-n\epins-rst8&pins-report-sw92syscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfdB`power-controller!mediatek,mt8195-power-controller+=7power-domain@8B+=Q power-domain@9B n!"_mfgaltk#+=Q$power-domain@10B =power-domain@11B =power-domain@12B =power-domain@13B =power-domain@14B=power-domain@15Bn"""" "@"A"K"% % %%%%%%%%%%%%%%%%% _vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18k#+=power-domain@16B8n"&$&%&&&'&(&)D_vdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5k#+=power-domain@17Bn"''_vppsys1vppsys1-0vppsys1-1k#=power-domain@22B n(((($_wepsys-0wepsys-1wepsys-2wepsys-3k#=power-domain@23Bn)_vdec0-0k#+=power-domain@24Bn*_vdec1-0k#=power-domain@25Bn+_vdec2-0k#=power-domain@26Bn, _venc0-larbk#+=power-domain@27Bn- _venc1-larbk#=power-domain@18B n"...&_vdosys1vdosys1-0vdosys1-1vdosys1-2k#+=power-domain@19Bk#=power-domain@20Bk#=power-domain@21Bn"Q_hdmi_tx=power-domain@28Bn//  _img-0img-1k#+=power-domain@29B=power-domain@30Bn"/0_ipeipe-0ipe-1k#=power-domain@31B(n11111_cam-0cam-1cam-2cam-3cam-4k#+=power-domain@32B =power-domain@33B!=power-domain@34B"=power-domain@0Bk#=power-domain@1Bk#=power-domain@2B=power-domain@3B=power-domain@4Bn"5"7_csi_rx_topcsi_rx_top1=power-domain@5Bn2 _ether=power-domain@6Bn"X"n _adspadsp1+k#=power-domain@7B n"g"""n#2_audioaudio1audio2audio3k#=watchdog@10007000mediatek,mt8195-wdt}BpO<syscon@1000c000"mediatek,mt8195-apmixedsyssysconBa!timer@10017000,mediatek,mt8195-timermediatek,mt6765-timerBp n3pwrap@10024000mediatek,mt8195-pwrapsysconB@\pwrapn## _spiwrap"$"pmicmediatek,mt6359 adcmediatek,mt6359-auxadcaudio-codecmediatek,mt6359-codecregulatorsmediatek,mt6359-regulatorbuck_vs1vs1) 5A!Yubuck_vgpu11vgpu11)A7Y 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Artcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi Bp \pmifspmimstn##"E(_pmif_sys_ckpmif_tmr_ckspmimst_clk_mux"$"+mt6315@6mediatek,mt6315-regulatorBregulatorsvbuck1Vbcpu)A7Yj u mt6315@7mediatek,mt6315-regulatorBregulatorsvbuck1Vgpu)A7Yj  infra-iommu@10315000mediatek,mt8195-iommu-infraB1PPPXmailbox@10320000mediatek,mt8195-gceB2@n#mailbox@10330000mediatek,mt8195-gceB3@n#scp@10500000mediatek,mt8195-scp0BPrp\sramcfgl1tcmokaymediatek/mt8195/scp.img4default5cros-ec-rpmsggoogle,cros-ec-rpmsgcros-ec-rpmsgclock-controller@10720000mediatek,mt8195-scp_adspBra6dsp@10803000mediatek,mt8195-dsp B0 \cfgsram,n"X"n"6"#K_adsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h7 rxtx89okay:;mailbox@10816000mediatek,mt8195-adsp-mboxB`8mailbox@10817000mediatek,mt8195-adsp-mboxBp9mt8195-afe-pcm@10890000mediatek,mt8195-audioB"761< 8audiosysn!!""""""g"""#"n"e"a"b"c"d#26_clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodspokayDd=serial@11001100*mediatek,mt8195-uartmediatek,mt6577-uartB n# _baudbusokayserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uartB n# _baudbus disabledserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uartB n# _baudbus disabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uartB n# _baudbus disabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uartB n# _baudbus disabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uartB n# _baudbus disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadcB n#_mainokaysyscon@11003000"mediatek,mt8195-pericfg_aosysconB0a2spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+Bn""#_parent-clksel-clkspi-clkokaydefault>ec@0+google,cros-ec-spiB default?-i2c-tunnelgoogle,cros-ec-i2c-tunnel+sbs-battery@bsbs,sbs-batteryB regulator@0google,cros-ec-regulatorBmt_pmic_vmc_ldo)OA6Sregulator@1google,cros-ec-regulatorBmt_pmic_vmch_ldo))2A6Rtypecgoogle,cros-ec-typec+connector@0usb-c-connectorBdualhost sourceconnector@1usb-c-connectorBdualhost sourcekeyboard-controllergoogle,cros-ec-keyb( ;PU}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g itxc  qrs4b  thermal-sensor@1100b000mediatek,mt8195-lvts-apB n#1#w@A$lvts-calib-data-1lvts-calib-data-2svs@1100bc00mediatek,mt8195-svsBn#_mainwB@(svs-calibration-datat-calibration-data1#8svs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmB7n"*#0_mainmmokaydefaultCpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmBn"+#N_mainmm disabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+Bn""#3_parent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+B n""#4_parent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+B0n""#5_parent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+Bn""#<_parent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+Bn""#=_parent-clksel-clkspi-clk disabledspi@1101d000mediatek,mt8195-spi-slaveBn#R_spi"" disabledspi@1101e000mediatek,mt8195-spi-slaveBn#S_spi"" disabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10aB@macirq._axiapbmac_mainptp_refrmii_internalmac_cg0n22"R"S"T2 "R"S"T"""7#DEF   " disabledmdiosnps,dwmac-mdio+stmmac-axi-config / ? ODrx-queues-config Y oEqueue0  queue1  queue2  queue3  tx-queues-config  Fqueue0   queue1   queue2   queue3   usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3 B - > \macippc ?+n#/"#B_sys_ckref_ckmcu_ck GH Igokay host Jusb@0'mediatek,mt8195-xhcimediatek,mtk-xhciB\mac","-""$n#/"!#B$_sys_ckref_ckmcu_ckdma_ckxhci_ckokay   -Kmmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc B#n"##_sourcehclksource_cgokay 9 C U fL  u    defaultstate_uhsL M N Ommc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc B$n"##$_sourcehclksource_cg""okay 9  6   defaultstate_uhsPQ P   R Smmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc B%n" ##I_sourcehclksource_cg" " disabledufshci@11270000mediatek,mt8195-ufshciB'# T@n#?#@#A#6#7#8#Z#]X_ufsufs_aesufs_tickunipro_sysclkunipro_tickunipro_mp_bclkufs_tx_symbolufs_mem_sub@   disabledthermal-sensor@11278000mediatek,mt8195-lvts-mcuB'n#1#w@A$lvts-calib-data-1lvts-calib-data-2usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci B))> \macippc U"."/""$n2"!2$_sys_ckref_ckmcu_ckdma_ckxhci_ck Ihokay   J -K 5usb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 B*-*> \macippc*?+"0"n2"2_sys_ckref_ckmcu_ck V Iiokay host Jusb@0'mediatek,mt8195-xhcimediatek,mtk-xhciB\mac"1"n2_sys_ckokay -Kusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 B+-+> \macippc+?+"2"n2"2 _sys_ckref_ckmcu_ck W Ijokay host Jusb@0'mediatek,mt8195-xhcimediatek,mtk-xhciB\mac"3"n2 _sys_ckokay J -Kpcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pcie6pci+B/@ \pcie-mac [8ׁ  eX o0n#V###&#+#K2/_pl_250mtl_26mtl_96mtl_32kperi_26mperi_mem"G" Y ~pcie-phy7 ` ZZZZokaydefault[interrupt-controllerZpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pcie6pci+B/@ \pcie-mac [8ׁ$$ $ $  eX o(n#W#X#Q2/_pl_250mtl_26mtl_96mtl_32kperi_26mperi_mem"H" \ ~pcie-phy7 ` ]]]]okaydefault^interrupt-controller]spi@1132c000(mediatek,mt8195-normediatek,mt8173-norB29n"o22 _spisfaxi+okaydefault_flash@0jedec,spi-norBu  efuse@11c10000%mediatek,mt8195-efusemediatek,efuseB+usb3-tx-imp@184,1B uusb3-rx-imp@184,2B tusb3-intr@185B susb3-tx-imp@186,1B rusb3-rx-imp@186,2B qusb3-intr@187B pusb2-intr-p0@188,1B usb2-intr-p1@188,2B usb2-intr-p2@189,1B usb2-intr-p3@189,2B pciephy-rx-ln1@190,1B |pciephy-tx-ln1-nmos@190,2B {pciephy-tx-ln1-pmos@191,1B zpciephy-rx-ln0@191,2B ypciephy-tx-ln0-nmos@192,1B xpciephy-tx-ln0-pmos@192,2B wpciephy-glb-intr@193B vdp-data@1acBlvts1-calib@1bcB@lvts2-calib@1d0B8Asvs-calib@580BdBsocinfo-data1@7a0Bt-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0Bn"_ref Vt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0Bn"_ref Wdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txBn mipi_tx0_plla  disableddsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txBn mipi_tx1_plla  disabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c B"un`#; _maindma+okayhdefaultai2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c B"un`#; _maindma+ disabledi2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c B "un`#; _maindma+okayhdefaultbpmic@34mediatek,mt6360B4 IRQBdefaultcclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_sB0a`hdmi-phy@11d5f000mediatek,mt8195-hdmi-phyB n"P#! ! _pll_ref26mpll1pll2 hdmi_txplla    disabledi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c B"und#; _maindma+okayhdefaultei2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c B"und#; _maindma+okayh 0defaultftrackpad@15elan,ekth3000B defaultg hi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c B "und#; _maindma+okayhdefaulticodec@1aB Y ! 0j <j Ik Wjrealtek,rt5682s famplifier@38maxim,max98390B8 |d Rightamplifier@39maxim,max98390B9 Lefti2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c B0"und#; _maindma+okayhdefaultltpm@50 google,cr50BP Xdefaultmi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c B@"und#; _maindma+okayhdefaultntouchscreen@10 hid-over-i2cB  \defaulto  h disabledtouchscreen@15 hid-over-i2cB  \defaulto  hclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wBPadt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+7okayusb-phy@0B n" _refda_ref Uusb-phy@700Bn!" _refda_ref wpqrintrrx_imptx_imp \t-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0B n" _refda_ref Gusb-phy@700Bn!" _refda_ref wstuintrrx_imptx_imp Hphy@11e80000mediatek,mt8195-pcie-phyB\sifwvwxyz{|Gglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln17 okayYufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphyBn _unipromp  disabledTgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jmB@n}0 jobmmugpu ~(7 7 7 7 7 core0core1core2core3core4okay clock-controller@13fbf000mediatek,mt8195-mfgcfgBa}syscon@14000000mediatek,mt8195-vppsys0sysconBa %dma-controller@14001000mediatek,mt8195-mdp3-rdmaB    *7 7n%<   >display@14002000mediatek,mt8195-mdp3-fgB   n%display@14003000mediatek,mt8195-mdp3-stitchB0 0n%display@14004000mediatek,mt8195-mdp3-hdrB@ @n%"display@14005000mediatek,mt8195-mdp3-aalBPF Pn% 7display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszB` ` %n% display@14007000mediatek,mt8195-mdp3-tdshpBp pn%#display@14008000mediatek,mt8195-mdp3-colorBI n%$7display@14009000mediatek,mt8195-mdp3-ovlBJ n%%7 7display@1400a000mediatek,mt8195-mdp3-paddingB n%7display@1400b000mediatek,mt8195-mdp3-tccB n%dma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotB   +n% 77 >mutex@1400f000mediatek,mt8195-vpp-mutexBP n%7smi@14010000mediatek,mt8195-smi-sub-commonBn%%%_apbsmigals0 I7smi@14011000mediatek,mt8195-smi-sub-commonBn%%%_apbsmigals0 I7smi@14012000mediatek,mt8195-smi-common-vppB  n%%%%_apbsmigals0gals17larb@14013000mediatek,mt8195-smi-larbB0 V In%%_apbsmi7iommu@14018000mediatek,mt8195-iommu-vppB8 gRn%_bclk7clock-controller@14e00000mediatek,mt8195-wpesysBa(clock-controller@14e02000mediatek,mt8195-wpesys_vpp0B aclock-controller@14e03000mediatek,mt8195-wpesys_vpp1B0alarb@14e04000mediatek,mt8195-smi-larbB@ V In((_apbsmi7larb@14e05000mediatek,mt8195-smi-larbBP V In((% _apbsmigals7syscon@14f00000mediatek,mt8195-vppsys1sysconBa  'mutex@14f01000mediatek,mt8195-vpp-mutexB{  n''7larb@14f02000mediatek,mt8195-smi-larbB  V In''% _apbsmigals7larb@14f03000mediatek,mt8195-smi-larbB0 V In''% _apbsmigals7display@14f06000mediatek,mt8195-mdp3-splitB`  `n''+',7display@14f07000mediatek,mt8195-mdp3-tccBp  pn'dma-controller@14f08000mediatek,mt8195-mdp3-rdmaB   n' 77 >dma-controller@14f09000mediatek,mt8195-mdp3-rdmaB   n'  77 >dma-controller@14f0a000mediatek,mt8195-mdp3-rdmaB   n'  77 >display@14f0b000mediatek,mt8195-mdp3-fgB  n' display@14f0c000mediatek,mt8195-mdp3-fgB  n' display@14f0d000mediatek,mt8195-mdp3-fgB  n' display@14f0e000mediatek,mt8195-mdp3-hdrB  n'display@14f0f000mediatek,mt8195-mdp3-hdrB  n'display@14f10000mediatek,mt8195-mdp3-hdrB  n' display@14f11000mediatek,mt8195-mdp3-aalBi  n'7display@14f12000mediatek,mt8195-mdp3-aalB j  n'7display@14f13000mediatek,mt8195-mdp3-aalB0k  0n'!7display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszB@  @ n'display@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszBP  P n'$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszB`  ` n'%display@14f17000mediatek,mt8195-mdp3-tdshpBp  pn'display@14f18000mediatek,mt8195-mdp3-tdshpB  n'(display@14f19000mediatek,mt8195-mdp3-tdshpB  n')display@14f1a000mediatek,mt8195-mdp3-mergeB  n'7display@14f1b000mediatek,mt8195-mdp3-mergeB  n'7display@14f1c000mediatek,mt8195-mdp3-colorBt  n'7display@14f1d000mediatek,mt8195-mdp3-colorB  un'7display@14f1e000mediatek,mt8195-mdp3-colorBv  n'7display@14f1f000mediatek,mt8195-mdp3-ovlBw  n'7 7display@14f20000mediatek,mt8195-mdp3-paddingB  n'7display@14f21000mediatek,mt8195-mdp3-paddingB  n'7display@14f22000mediatek,mt8195-mdp3-paddingB   n'7dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotB0  0 n' 77 >dma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotB@  @ n' 77 >dma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotBP  P n' 77 >clock-controller@15000000mediatek,mt8195-imgsysBa/larb@15001000mediatek,mt8195-smi-larbB V  In///  _apbsmigals7smi@15002000mediatek,mt8195-smi-sub-commonB n//%_apbsmigals0 I7smi@15003000mediatek,mt8195-smi-sub-commonB0n/// _apbsmigals0 I7clock-controller@15110000 mediatek,mt8195-imgsys1_dip_topBalarb@15120000mediatek,mt8195-smi-larbB V  In/_apbsmi7clock-controller@15130000mediatek,mt8195-imgsys1_dip_nrBaclock-controller@15220000mediatek,mt8195-imgsys1_wpeB"alarb@15230000mediatek,mt8195-smi-larbB# V  In/_apbsmi7clock-controller@15330000mediatek,mt8195-ipesysB3a0larb@15340000mediatek,mt8195-smi-larbB4 V  In00_apbsmi7clock-controller@16000000mediatek,mt8195-camsysBa1larb@16001000mediatek,mt8195-smi-larbB V  In111 _apbsmigals7larb@16002000mediatek,mt8195-smi-larbB  V In11_apbsmi7smi@16004000mediatek,mt8195-smi-sub-commonB@n111_apbsmigals0 I7smi@16005000mediatek,mt8195-smi-sub-commonBPn11%_apbsmigals0 I7larb@16012000mediatek,mt8195-smi-larbB  V In_apbsmi7 larb@16013000mediatek,mt8195-smi-larbB0 V In_apbsmi7 larb@16014000mediatek,mt8195-smi-larbB@ V In_apbsmi7!larb@16015000mediatek,mt8195-smi-larbBP V In_apbsmi7!clock-controller@1604f000mediatek,mt8195-camsys_rawaBaclock-controller@1606f000mediatek,mt8195-camsys_yuvaBaclock-controller@1608f000mediatek,mt8195-camsys_rawbBaclock-controller@160af000mediatek,mt8195-camsys_yuvbB aclock-controller@16140000mediatek,mt8195-camsys_mrawBalarb@16141000mediatek,mt8195-smi-larbB V In11 _apbsmigals7"larb@16142000mediatek,mt8195-smi-larbB  V In_apbsmi7"clock-controller@17200000mediatek,mt8195-ccusysB alarb@17201000mediatek,mt8195-smi-larbB  V In_apbsmi7video-codec@18000000mediatek,mt8195-vcodec-dec * 7+ B@`video-codec@2000mediatek,mtk-vcodec-lat-socB  7 n"A))"_selvdeclattop"A"7video-codec@10000mediatek,mtk-vcodec-latB0 7 n"A))"_selvdeclattop"A"7video-codec@25000mediatek,mtk-vcodec-coreBPP 7 n"A**"_selvdeclattop"A"7larb@1800d000mediatek,mt8195-smi-larbB V In))_apbsmi7larb@1800e000mediatek,mt8195-smi-larbB V In%)_apbsmi7clock-controller@1800f000mediatek,mt8195-vdecsys_socBa)larb@1802e000mediatek,mt8195-smi-larbB V In**_apbsmi7clock-controller@1802f000mediatek,mt8195-vdecsysBa*larb@1803e000mediatek,mt8195-smi-larbB V In%+_apbsmi7clock-controller@1803f000mediatek,mt8195-vdecsys_core1Ba+clock-controller@190f3000mediatek,mt8195-apusys_pllB0aclock-controller@1a000000mediatek,mt8195-vencsysBa,larb@1a010000mediatek,mt8195-smi-larbB V In,,_apbsmi7video-codec@1a020000mediatek,mt8195-vcodec-encBH 7`abcdvwxyU *n, _venc_sel"@"7+jpeg-decoder@1a040000mediatek,mt8195-jpgdec70 7mnrstu+0jpgdec@0,0mediatek,mt8195-jpgdec-hwB0 7mnrstuWn,_jpgdec7jpgdec@0,10000mediatek,mt8195-jpgdec-hwB0 7mnrstuXn,_jpgdec7jpgdec@1,0mediatek,mt8195-jpgdec-hwB0 7\n-_jpgdec7clock-controller@1b000000mediatek,mt8195-vencsys_core1Ba-syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssysconB a &port+endpoint@0B vjpeg-encoder@1a030000mediatek,mt8195-jpgenc7 7+0jpgenc@0,0mediatek,mt8195-jpgenc-hwB 7ghilVn,_jpgenc7jpgenc@1,0mediatek,mt8195-jpgenc-hwB 7[n-_jpgenc7larb@1b010000mediatek,mt8195-smi-larbB V In--%  _apbsmigals7ovl@1c000000mediatek,mt8195-disp-ovlB|7n& 7 ports+port@0Bendpoint vport@1Bendpoint vrdma@1c002000mediatek,mt8195-disp-rdmaB ~7n& 7  ports+port@0Bendpoint vport@1Bendpoint vcolor@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-colorB07n& 0ports+port@0Bendpoint vport@1Bendpoint vccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorrB@7n& @ports+port@0Bendpoint vport@1Bendpoint vaal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aalBP7n& Pports+port@0Bendpoint vport@1Bendpoint vgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gammaB`7n& `ports+port@0Bendpoint vport@1Bendpoint vdither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-ditherBp7n&  pports+port@0Bendpoint vport@1Bendpoint vdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsiB7n&&*_enginedigitalhs  ~dphy disableddsc@1c009000mediatek,mt8195-disp-dscB7n& ports+port@0Bendpoint vport@1Bendpoint vdsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsiB 7n&&+_enginedigitalhs  ~dphy disabledmerge@1c014000mediatek,mt8195-disp-mergeB@7n& @ports+port@0Bendpoint vport@1Bendpoint vdp-intf@1c015000mediatek,mt8195-dp-intfBP7n&,&!_pixelenginepllokayports+port@0Bendpoint vport@1Bendpoint vmutex@1c016000mediatek,mt8195-disp-mutexB`7n& ` Ularb@1c018000mediatek,mt8195-smi-larbB V In&(&(%  _apbsmigals7larb@1c019000mediatek,mt8195-smi-larbB V In&(% % _apbsmigals7syscon@1c100000mediatek,mt8195-vdosys1sysconB  aO.port+endpoint@1B vsmi@1c01b000mediatek,mt8195-smi-common-vdoB n&%&&&)&$_apbsmigals0gals17iommu@1c01f000mediatek,mt8195-iommu-vdoB8 gn&'_bclk7mutex@1c101000mediatek,mt8195-disp-mutexB7n.  larb@1c102000mediatek,mt8195-smi-larbB  V In... _apbsmigals7larb@1c103000mediatek,mt8195-smi-larbB0 V In..%  _apbsmigals7dma-controller@1c104000mediatek,mt8195-vdo1-rdmaB@n.7 7@ @ >dma-controller@1c105000mediatek,mt8195-vdo1-rdmaBPn.7 7` P >dma-controller@1c106000mediatek,mt8195-vdo1-rdmaB`n.7 7A ` >dma-controller@1c107000mediatek,mt8195-vdo1-rdmaBpn.7 7a p >dma-controller@1c108000mediatek,mt8195-vdo1-rdmaBn.7 7B  >dma-controller@1c109000mediatek,mt8195-vdo1-rdmaBn.7 7b  >dma-controller@1c10a000mediatek,mt8195-vdo1-rdmaBn.7 7C  >dma-controller@1c10b000mediatek,mt8195-vdo1-rdmaBn.7 7c  >vpp-merge@1c10c000mediatek,mt8195-disp-mergeBn. ._mergemerge_async7  1.vpp-merge@1c10d000mediatek,mt8195-disp-mergeBn. ._mergemerge_async7  1.vpp-merge@1c10e000mediatek,mt8195-disp-mergeBn. ._mergemerge_async7  1.vpp-merge@1c10f000mediatek,mt8195-disp-mergeBn. ._mergemerge_async7  1.vpp-merge@1c110000mediatek,mt8195-disp-mergeBn. ._mergemerge_async7  1.ports+port@0+Bendpoint@1B vport@1+Bendpoint@1B vdpi@1c112000mediatek,mt8195-dpiB n.-..2_pixelenginepll71. disabledports+port@0Bendpointport@1Bendpointdp-intf@1c113000mediatek,mt8195-dp-intfB07n./.!_pixelenginepllokayports+port@0+Bendpoint@1B vport@1+Bendpoint@1B vhdr-engine@1c114000mediatek,mt8195-disp-ethdrpB@Pp4\mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp @Pphn.%. .#.!.$.".1.&.'.(.).*"_mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top7 7de(1.3.4.5.6.7E8vdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncports+port@0+Bendpoint@1B vport@1+Bendpoint@1B vhdmi-tx@1c300000mediatek,mt8195-hdmi-txB0 n"Q"L"M',_bushdcphdcp24mhdmi-split"L"7  ~hdmi disabledi2cmediatek,mt8195-hdmi-ddcnports+port@0Bendpointport@1Bendpointedp-tx@1c500000mediatek,mt8195-edp-txBPwdp_calibration_data7 okaydefaultports+port@0Bendpoint vport@1Bendpoint  vaux-buspanel edp-panel  portendpoint vdp-tx@1c600000mediatek,mt8195-dp-txB`wdp_calibration_data7 okaydefaultports+port@0+Bendpoint@1B vport@1Bendpoint thermal-zonescpu0-thermal  tripstrip-alertL$Epassivetrip-crit$ Ecriticalcooling-mapsmap0/04 cpu1-thermal  tripstrip-alertL$Epassivetrip-crit$ Ecriticalcooling-mapsmap0/04 cpu2-thermal  tripstrip-alertL$Epassivetrip-crit$ Ecriticalcooling-mapsmap0/04 cpu3-thermal  tripstrip-alertL$Epassivetrip-crit$ Ecriticalcooling-mapsmap0/04 cpu4-thermal  tripstrip-alertL$Epassivetrip-crit$ Ecriticalcooling-mapsmap0/04cpu5-thermal  tripstrip-alertL$Epassivetrip-crit$ Ecriticalcooling-mapsmap0/04cpu6-thermal  tripstrip-alertL$Epassivetrip-crit$ Ecriticalcooling-mapsmap0/04cpu7-thermal  tripstrip-alertL$Epassivetrip-crit$ Ecriticalcooling-mapsmap0/04vpu0-thermal  tripstrip-alertL$Epassivetrip-crit$ Ecriticalvpu1-thermal   tripstrip-alertL$Epassivetrip-crit$ Ecriticalgpu-thermal   tripstrip-alertL$Epassivetrip-crit$ Ecriticalgpu1-thermal   tripstrip-alertL$Epassivetrip-crit$ Ecriticalvdec-thermal   tripstrip-alertL$Epassivetrip-crit$ Ecriticalimg-thermal   tripstrip-alertL$Epassivetrip-crit$ Ecriticalinfra-thermal  tripstrip-alertL$Epassivetrip-crit$ Ecriticalcam0-thermal  tripstrip-alertL$Epassivetrip-crit$ Ecriticalcam1-thermal  tripstrip-alertL$Epassivetrip-crit$ Ecriticalsoc-area-thermal  tripstrip-critH $ Ecriticalpmic-area-thermal  tripstrip-critH $ Ecriticalbacklight-lcd0pwm-backlightCU@ nR{   chosenserial0:115200n8memory@400000006memoryB@regulator-pp3300-disp-xregulator-fixedpp3300_disp_x)2ZA2ZY  7defaultkregulator-pp3300-ldo-z5regulator-fixedpp3300_ldo_z5u)2ZA2Zregulator-pp3300-s3regulator-fixed pp3300_s3u)2ZA2Zkhregulator-pp3300-z2regulator-fixed pp3300_z2u)2ZA2Zkregulator-pp4200-z2regulator-fixed pp4200_z2u)@@A@@regulator-pp5000-s5regulator-fixed pp5000_s5u)LK@ALK@regulator-ppvar-sysregulator-fixed ppvar_sysuthermal-sensor-t1generic-adc-thermalsensor-channelx~%':[N au0@] P`Gp$8L_}sk\(OD8;3H,thermal-sensor-t2generic-adc-thermalsensor-channelx~%':[N au0@] P`Gp$8L_}sk\(OD8;3H,regulator-5v0-usb-vbusregulator-fixed usb-vbus)LK@ALK@uKreserved-memory+memory@50000000shared-dma-poolBP4memory@60000000shared-dma-poolB`;memory@60d80000shared-dma-poolB`=memory@60e80000shared-dma-poolB`(:rt1019prealtek,rt1019prt1019pdefault d disabled compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typedp-intf0dp-intf1dpi1gce0gce1hdmi0ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7i2c0i2c1i2c2i2c3i2c4i2c5i2c7mmc0mmc1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellscpu-supplyphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platformmediatek,adspmediatek,dai-linkpinctrl-namespinctrl-0audio-routinglink-namemediatek,clk-providersound-dai#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesmediatek,rsel-resistance-in-si-unitgpio-line-namespinmuxinput-enablebias-pull-upbias-disabledrive-strength-microampdrive-strengthbias-pull-downoutput-highoutput-low#power-domain-cellsdomain-supplyclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#sound-dai-cellsinterrupts-extended#io-channel-cellsmediatek,dmic-modemediatek,mic-type-0regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#iommu-cells#mbox-cellsfirmware-namememory-regionmediatek,rpmsg-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namesmediatek,etdm-in2-cowork-sourcemediatek,etdm-out2-cowork-sourcemediatek,pad-selectspi-max-frequencywakeup-sourcegoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphysmediatek,syscon-wakeupdr_modevusb33-supplyrx-fifo-depthvbus-supplybus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablepinctrl-1vmmc-supplyvqmmc-supplycap-sd-highspeedcd-gpiosno-mmcsd-uhs-sdr50sd-uhs-sdr104freq-table-hzmediatek,ufs-disable-mcqmediatek,u3p-dis-mskusb2-lpm-disablebus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapspi-rx-bus-widthspi-tx-bus-widthbits#phy-cellsmediatek,ibiasmediatek,ibias_upi2c-scl-internal-delay-nsvcc-supplyrealtek,jd-srcAVDD-supplyDBVDD-supplyMICVDD-supplyLDO1-IN-supplyrealtek,amic-delay-msreset-gpiossound-name-prefixhid-descr-addrpost-power-on-delay-msvdd-supplyoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzdata-lanespower-supplybacklightpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicebrightness-levelsdefault-brightness-levelenable-gpiosnum-interpolated-stepspwmsstdout-pathenable-active-highgpiovin-supplyregulator-boot-onio-channelsio-channel-namestemperature-lookup-tableno-maplabelsdb-gpios