8x(x1google,tomato-rev1google,tomatomediatek,mt8195 +7Acer Tomato (rev1) boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/mailbox@10320000Y/soc/mailbox@10330000^/soc/hdmi-tx@1c300000d/soc/hdr-engine@1c114000k/soc/mutex@1c016000r/soc/mutex@1c101000y/soc/vpp-merge@1c10c000/soc/vpp-merge@1c10d000/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/i2c@11e00000/soc/i2c@11e01000/soc/i2c@11e02000/soc/i2c@11e03000/soc/i2c@11e04000 /soc/i2c@11d00000/soc/i2c@11d02000/soc/mmc@11230000/soc/mmc@11240000!/soc/serial@11001100cpus+cpu@0)cpuarm,cortex-a5559psciG[ec3@k4~@@ cpu@100)cpuarm,cortex-a5559psciG[ec3@k4~@@ cpu@200)cpuarm,cortex-a5559psciG[ec3@k4~@@ cpu@300)cpuarm,cortex-a5559psciG[ec3@k4~@@cpu@400)cpuarm,cortex-a7859psciG[fk~@@  cpu@500)cpuarm,cortex-a7859psciG[fk~@@  cpu@600)cpuarm,cortex-a7859psciG[fk~@@  cpu@700)cpuarm,cortex-a7859psciG[fk~@@  cpu-mapcluster0core0 core1 core2 core3core4core5core6core7idle-statespscicpu-retention-larm,idle-state*AR2c_sDcpu-retention-barm,idle-state*AR-cscpu-off-larm,idle-state*AR7csHcpu-off-barm,idle-state*AR2csl2-cache0cache@l2-cache1cache@ l3-cachecache @dsu-pmu arm,dsu-pmu  faildmic-codec dmic-codec2mt8195-soundokay}DL10_FEDPTX_BEETDM1_IN_BEETDM2_IN_BEETDM1_OUT_BEETDM2_OUT_BEUL_SRC1_BEAFE_SOF_DL2AFE_SOF_DL3AFE_SOF_UL4AFE_SOF_UL5default?HeadphoneHPOLHeadphoneHPORIN1PHeadset MicExt SpkSpeaker%mediatek,mt8195_mt6359_rt1019_rt56827mt8195_r1019_5682mm-dai-link *ETDM1_IN_BE4cpuhs-playback-dai-link *ETDM1_OUT_BE4cpucodecJhs-capture-dai-link *ETDM2_IN_BE4cpucodecJspk-playback-dai-link *ETDM2_OUT_BE4cpucodecJdisplayport-dai-link*DPTX_BEcodecJfixed-factor-clock-13mfixed-factor-clockTahr}clk13m2oscillator-26m fixed-clockT[}clk26moscillator-32k fixed-clockT[}clk32kperformance-controller@11bc10mediatek,cpufreq-hw 5 0 opp-table-gpuoperating-points-v2}opp-390000000> hopp-410000000p opp-431000000 opp-4730000001h@ <opp-515000000F <opp-556000000!# Ҧopp-598000000# opp-640000000&% opp-670000000'c opp-700000000)' Lopp-730000000+ }opp-760000000-L `opp-790000000/q 4opp-82000000005 opp-8500000002 @opp-8800000004s qpmu-a55arm,cortex-a55-pmu pmu-a78arm,cortex-a78-pmu psci arm,psci-1.0@smctimerarm,armv8-timer @   soc+ simple-businterrupt-controller@c000000 arm,gic-v3  5    ppi-partitionsinterrupt-partition-09 interrupt-partition-19syscon@10000000 mediatek,mt8195-topckgensyscon5T!syscon@10001000#mediatek,mt8195-infracfg_aosyscon5TB"syscon@10003000mediatek,mt8195-pericfgsyscon50THpinctrl@10005000mediatek,mt8195-pinctrl5PBOiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintYiudefault>I2S_SPKR_MCLKI2S_SPKR_DATAINI2S_SPKR_LRCKI2S_SPKR_BCLKEC_AP_INT_ODLAP_FLASH_WP_LTCHPAD_INT_ODLEDP_HPD_1V8AP_I2C_CAM_SDAAP_I2C_CAM_SCLAP_I2C_TCHPAD_SDA_1V8AP_I2C_TCHPAD_SCL_1V8AP_I2C_AUD_SDAAP_I2C_AUD_SCLAP_I2C_TPM_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_TCHSCR_SCL_1V8EC_AP_HPD_ODPCIE_NVME_RST_LPCIE_NVME_CLKREQ_ODLPCIE_RST_1V8_LPCIE_CLKREQ_1V8_ODLPCIE_WAKE_1V8_ODLCLK_24M_CAM0CAM1_SEN_ENAP_I2C_PWR_SCL_1V8AP_I2C_PWR_SDA_1V8AP_I2C_MISC_SCLAP_I2C_MISC_SDAEN_PP5000_HDMI_XAP_HDMITX_HTPLGAP_HDMITX_SCL_1V8AP_HDMITX_SDA_1V8AP_RTC_CLK32KAP_EC_WATCHDOG_LSRCLKENA0SRCLKENA1PWRAP_SPI0_CS_LPWRAP_SPI0_CKPWRAP_SPI0_MOSIPWRAP_SPI0_MISOSPMI_SCLSPMI_SDAI2S_HP_DATAINI2S_HP_MCLKI2S_HP_BCKI2S_HP_LRCKI2S_HP_DATAOUTSD_CD_ODLEN_PP3300_DISP_XTCHSCR_RST_1V8_LTCHSCR_REPORT_DISABLEEN_PP3300_WLAN_XBT_KILL_1V8_LI2S_SPKR_DATAOUTWIFI_KILL_1V8_LBEEP_ONSCP_I2C_SENSOR_SCL_1V8SCP_I2C_SENSOR_SDA_1V8AUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_DAT_MISO0AUD_DAT_MISO1AUD_DAT_MISO2SCP_VREQ_VAOAP_SPI_GSC_TPM_CLKAP_SPI_GSC_TPM_MOSIAP_SPI_GSC_TPM_CS_LAP_SPI_GSC_TPM_MISOEN_PP1000_CAM_XAP_EDP_BKLTENUSB3_HUB_RST_LWLAN_ALERT_ODLEC_IN_RW_ODLGSC_AP_INT_ODLHP_INT_ODLCAM0_RST_LCAM1_RST_LTCHSCR_INT_1V8_LCAM1_DET_LRST_ALC1011_LBL_PWM_1V8UART_AP_TX_DBG_RXUART_DBG_TX_AP_RXEN_SPKRAP_EC_WARM_RST_REQUART_SCP_TX_DBGCON_RXUART_DBGCON_TX_SCP_RXKPCOL0MT6315_GPU_INTMT6315_PROC_BC_INTSD_CMDSD_CLKSD_DAT0SD_DAT1SD_DAT2SD_DAT3EMMC_DAT7EMMC_DAT6EMMC_DAT5EMMC_DAT4EMMC_RSTBEMMC_CMDEMMC_CLKEMMC_DAT3EMMC_DAT2EMMC_DAT1EMMC_DAT0EMMC_DSLMT6360_INT_ODLSCP_JTAG0_TRSTNAP_SPI_EC_CS_LAP_SPI_EC_CLKAP_SPI_EC_MOSIAP_SPI_EC_MISOSCP_JTAG0_TMSSCP_JTAG0_TCKSCP_JTAG0_TDOSCP_JTAG0_TDIAP_SPI_FLASH_CS_LAP_SPI_FLASH_CLKAP_SPI_FLASH_MOSIAP_SPI_FLASH_MISOaudio-default-pinspins-cmd-datDEFGHIJK<12345pins-hp-jack-int-odlYecr50-irq-default-pinslpins-gsc-ap-int-odlXcros-ec-irq-default-pins>pins-ec-ap-int-odleedptx-default-pinspins-cmd-datdisp-pwm0-default-pinsBpins-disp-pwmRadptx-default-pinspins-cmd-dati2c0-default-pinscpins-bus i2c1-default-pinsdpins-bus  i2c2-default-pinsgpins-bus  i2c3-default-pinskpins-busi2c4-default-pinsmpins-busi2c5-default-pins_pins-busi2c7-default-pins`pins-busmmc0-default-pinsKpins-cmd-dat$~}|{wvutyepins-clkz fpins-rstxemmc0-uhs-pinsLpins-cmd-dat$~}|{wvutyepins-clkz fpins-ds fpins-rstxemmc1-detect-pinsPpins-insert6mmc1-default-pinsOpins-cmd-datnpqrsepins-clko fnor-default-pins]pins-ck-io  pins-cspcie0-default-pinspins-bus pcie1-default-pins\pins-bus panel-pwr-default-pinspins-vreg-en7pio-default-pinspins-wifi-enable:pins-low-power-pd,./0ABCD pins-low-power-pupd<MNOPSUZ[]^_`hik ert1019p-default-pinspins-amp-sdbd%scp-default-pins4pins-vreqLspi0-default-pins=pins-cs-mosi-clk pins-miso subpmic-default-pinsapins-subpmic-int-ntrackpad-default-pinsepins-int-ntouchscreen-default-pinsnpins-int-n\epins-rst8pins-report-sw9%syscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd5`power-controller!mediatek,mt8195-power-controller+06power-domain@85+0Dpower-domain@95 a !Rmfgalt^"+0D#power-domain@105 0power-domain@115 0power-domain@125 0power-domain@135 0power-domain@1450power-domain@155a!!!! !@!A!K!$ $ $$$$$$$$$$$$$$$$$ Rvppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18^"+0power-domain@1658a!%$%%%&%'%(%)DRvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5^"+0power-domain@175a!&&Rvppsys1vppsys1-0vppsys1-1^"0power-domain@225 a''''$Rwepsys-0wepsys-1wepsys-2wepsys-3^"0power-domain@235a(Rvdec0-0^"+0power-domain@245a)Rvdec1-0^"0power-domain@255a*Rvdec2-0^"0power-domain@265a+ Rvenc0-larb^"+0power-domain@275a, Rvenc1-larb^"0power-domain@185 a!---&Rvdosys1vdosys1-0vdosys1-1vdosys1-2^"+0power-domain@195^"0power-domain@205^"0power-domain@215a!QRhdmi_tx0power-domain@285a..  Rimg-0img-1^"+0power-domain@2950power-domain@305a!./Ripeipe-0ipe-1^"0power-domain@315(a00000Rcam-0cam-1cam-2cam-3cam-4^"+0power-domain@325 0power-domain@335!0power-domain@345"0power-domain@05^"0power-domain@15^"0power-domain@250power-domain@350power-domain@45a!5!7Rcsi_rx_topcsi_rx_top10power-domain@55a1 Rether0power-domain@65a!X!n Radspadsp1+^"0power-domain@75 a!g!"!n"2Raudioaudio1audio2audio3^"0watchdog@10007000mediatek,mt8195-wdt5pB;syscon@1000c000"mediatek,mt8195-apmixedsyssyscon5T timer@10017000,mediatek,mt8195-timermediatek,mt6765-timer5p a2pwrap@10024000mediatek,mt8195-pwrapsyscon5@Opwrapa"" Rspiwrapp!$!pmicmediatek,mt6359 adcmediatek,mt6359-auxadcaudio-codecmediatek,mt6359-codecregulatorsmediatek,mt6359-regulatorbuck_vs1vs1 5!4Pbuck_vgpu11vgpu117d4 yPbuck_vmodemvmodemd*4buck_vpuvpu7d4 yPbuck_vcorevcore d4 yPbuck_vs2vs2 5j4Pbuck_vpavpa 74,buck_vproc2vproc27dL4 ybuck_vproc1vproc17dL4 ybuck_vcore_sshub vcore_sshub7buck_vgpu11_sshub vgpu11_sshubdpdpPldo_vaud18vaud18w@w@4ldo_vsim1vsim1/M`ldo_vibrvibrO2Zldo_vrf12vrf12 Pldo_vusbvusb--4PIldo_vsram_proc2 vsram_proc2 dL4Pldo_vio18vio184Phldo_vcamiovcamioldo_vcn18vcn18w@w@4ldo_vfe28vfe28**4xldo_vcn13vcn13  ldo_vcn33_1_bt vcn33_1_bt*5gldo_vcn33_1_wifi vcn33_1_wifi*5gldo_vaux18vaux18w@w@4Pldo_vsram_others vsram_others q qd4#ldo_vefusevefuseldo_vxo22vxo22w@!Pldo_vrfckvrfck`ldo_vrfck_1vrfckjldo_vbif28vbif28**4ldo_vio28vio28*2ZPldo_vemcvemc,@ 2Zldo_vemc_1vemc&%2ZMldo_vcn33_2_bt vcn33_2_bt*5gldo_vcn33_2_wifi vcn33_2_wifi*5gldo_va12va12O Pldo_va09va09 5Oldo_vrf18vrf18Pldo_vsram_md vsram_md d*4ldo_vufsvufsPNldo_vm18vm18Pldo_vbbckvbbckOldo_vsram_proc1 vsram_proc1 dL4Pldo_vsim2vsim2/M`ldo_vsram_others_sshubvsram_others_sshub rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi 5p Opmifspmimsta""!E(Rpmif_sys_ckpmif_tmr_ckspmimst_clk_muxp!$!+mt6315@6mediatek,mt6315-regulator5regulatorsvbuck1Vbcpu74dj yP mt6315@7mediatek,mt6315-regulator5regulatorsvbuck1Vgpu74dj yinfra-iommu@10315000mediatek,mt8195-iommu-infra51PPPWmailbox@10320000mediatek,mt8195-gce52@a"mailbox@10330000mediatek,mt8195-gce53@a"~scp@10500000mediatek,mt8195-scp05PrpOsramcfgl1tcmokaymediatek/mt8195/scp.img3default4cros-ec-rpmsggoogle,cros-ec-rpmsgcros-ec-rpmsgclock-controller@10720000mediatek,mt8195-scp_adsp5rT5dsp@10803000mediatek,mt8195-dsp 50 Ocfgsram,a!X!n!5!#KRadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h6rxtx78okay9:mailbox@10816000mediatek,mt8195-adsp-mbox5`7mailbox@10817000mediatek,mt8195-adsp-mbox5p8mt8195-afe-pcm@10890000mediatek,mt8195-audio5!66 ; audiosysa  !!!!!!g!"!#!n!e!a!b!c!d"25Rclk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodspokay?<serial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart5 a" Rbaudbusokayserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart5 a" Rbaudbus disabledserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart5 a" Rbaudbus disabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart5 a" Rbaudbus disabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart5 a" Rbaudbus disabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart5 a" Rbaudbus disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc5 a"Rmainokaysyscon@11003000"mediatek,mt8195-pericfg_aosyscon50T1spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+5a!!"Rparent-clksel-clkspi-clkokaydefault=`ec@0+google,cros-ec-spi5 default>t-i2c-tunnelgoogle,cros-ec-i2c-tunnel+sbs-battery@bsbs,sbs-battery5 regulator@0google,cros-ec-regulator5mt_pmic_vmc_ldoO6Rregulator@1google,cros-ec-regulator5mt_pmic_vmch_ldo)26Qtypecgoogle,cros-ec-typec+connector@0usb-c-connector5dualhostsourceconnector@1usb-c-connector5dualhostsourcekeyboard-controllergoogle,cros-ec-keyb D0txc q rs}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g i4=  thermal-sensor@1100b000mediatek,mt8195-lvts-ap5 a" "R?@$^lvts-calib-data-1lvts-calib-data-2osvs@1100bc00mediatek,mt8195-svs5a"RmainRA?(^svs-calibration-datat-calibration-data "svs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm56a!*"0RmainmmokaydefaultBpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm5a!+"NRmainmm disabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+5a!!"3Rparent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+5 a!!"4Rparent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+50a!!"5Rparent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+5a!!"<Rparent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+5a!!"=Rparent-clksel-clkspi-clk disabledspi@1101d000mediatek,mt8195-spi-slave5a"RRspip!! disabledspi@1101e000mediatek,mt8195-spi-slave5a"SRspip!! disabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a5@macirq.Raxiapbmac_mainptp_refrmii_internalmac_cg0a11!R!S!T1 p!R!S!T!!!6"CDE disabledmdiosnps,dwmac-mdio+stmmac-axi-config   *Crx-queues-config 4 JDqueue0 [ nqueue1 [ nqueue2 [ nqueue3 [ ntx-queues-config  Equeue0  [ queue1  [ queue2  [ queue3  [ usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3 5 - > Omacippc ?+a"/!"BRsys_ckref_ckmcu_ck FG Hgokay host Iusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci5Omacp!,!-!!$a"/! "B$Rsys_ckref_ckmcu_ckdma_ckxhci_ckokay  Jmmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc 5#a!""Rsourcehclksource_cgokay   0 ALx  P _ n v |defaultstate_uhsK L M Nmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc 5$a!""$Rsourcehclksource_cgp!!okay   6x   ndefaultstate_uhsOP O   Q Rmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc 5%a! ""IRsourcehclksource_cgp! ! disabledufshci@11270000mediatek,mt8195-ufshci5'# S@a"?"@"A"6"7"8"Z"]XRufsufs_aesufs_tickunipro_sysclkunipro_tickunipro_mp_bclkufs_tx_symbolufs_mem_sub@   disabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu5'a" "R?@$^lvts-calib-data-1lvts-calib-data-2ousb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci 5))> Omacippc Tp!.!/!!$a1! 1$Rsys_ckref_ckmcu_ckdma_ckxhci_ck Hhokay  I J usb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 5*-*> Omacippc*?+p!0!a1!1Rsys_ckref_ckmcu_ck U Hiokay host Iusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci5Omacp!1!a1Rsys_ckokay Jusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 5+-+> Omacippc+?+p!2!a1!1 Rsys_ckref_ckmcu_ck V Hjokay host Iusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci5Omacp!3!a1 Rsys_ckokay % Jpcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pcie)pci+5/@ Opcie-mac 68ʁ  @W J0a"V"#"&"+"K1/Rpl_250mtl_26mtl_96mtl_32kperi_26mperi_memp!G! X Ypcie-phy6 c` vYYYY disabledinterrupt-controllerYpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pcie)pci+5/@ Opcie-mac 68ʁ$$ $ $  @W J(a"W"X"Q1/Rpl_250mtl_26mtl_96mtl_32kperi_26mperi_memp!H! Z Ypcie-phy6 c` v[[[[okaydefault\interrupt-controller[spi@1132c000(mediatek,mt8195-normediatek,mt8173-nor529a!o11 Rspisfaxi+okaydefault]flash@0jedec,spi-nor5tu  efuse@11c10000%mediatek,mt8195-efusemediatek,efuse5+usb3-tx-imp@184,15 tusb3-rx-imp@184,25 susb3-intr@1855 rusb3-tx-imp@186,15 qusb3-rx-imp@186,25 pusb3-intr@1875 ousb2-intr-p0@188,15 usb2-intr-p1@188,25 usb2-intr-p2@189,15 usb2-intr-p3@189,25 pciephy-rx-ln1@190,15 {pciephy-tx-ln1-nmos@190,25 zpciephy-tx-ln1-pmos@191,15 ypciephy-rx-ln0@191,25 xpciephy-tx-ln0-nmos@192,15 wpciephy-tx-ln0-pmos@192,25 vpciephy-glb-intr@1935 udp-data@1ac5lvts1-calib@1bc5?lvts2-calib@1d058@svs-calib@5805dAsocinfo-data1@7a05t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@05a!Rref Ut-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@05a!Rref Vdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx5a }mipi_tx0_pllT  disableddsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx5a }mipi_tx1_pllT  disabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c 5"ha^"; Rmaindma+okay[default_i2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c 5"ha^"; Rmaindma+ disabledi2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c 5 "ha^"; Rmaindma+okay[default`pmic@34mediatek,mt636054 IRQBdefaultaclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s50T^hdmi-phy@11d5f000mediatek,mt8195-hdmi-phy5 a!P" Rpll_ref26mpll1pll2 }hdmi_txpllT    disabledi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c 5"hab"; Rmaindma+okay[defaultci2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c 5"hab"; Rmaindma+okay[ 0defaultdtrackpad@15elan,ekth30005 defaulte fi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c 5 "hab"; Rmaindma+okay[defaultgcodec@1a5 Y  h h $i 2hrealtek,rt5682i A Vji2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 50"hab"; Rmaindma+okay[defaultktpm@50 google,cr505P Xdefaultli2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c 5@"hab"; Rmaindma+okay[defaultmtouchscreen@10 hid-over-i2c5 b \defaultn q  fokayclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_w5PTbt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+6okayusb-phy@05 a! Rrefda_ref Tusb-phy@7005a ! Rrefda_ref Ropq^intrrx_imptx_imp Zt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@05 a! Rrefda_ref Fusb-phy@7005a ! Rrefda_ref Rrst^intrrx_imptx_imp Gphy@11e80000mediatek,mt8195-pcie-phy5OsifRuvwxyz{G^glb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln16  disabledXufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy5a Runipromp  disabledSgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm5@a|0 jobmmugpu }(6 6 6 6 6 core0core1core2core3core4okay clock-controller@13fbf000mediatek,mt8195-mfgcfg5T|syscon@14000000mediatek,mt8195-vppsys0syscon5T ~$dma-controller@14001000mediatek,mt8195-mdp3-rdma5 ~   6 a$<~ ~ ~~~ display@14002000mediatek,mt8195-mdp3-fg5  ~ a$display@14003000mediatek,mt8195-mdp3-stitch50 ~0a$display@14004000mediatek,mt8195-mdp3-hdr5@ ~@a$"display@14005000mediatek,mt8195-mdp3-aal5PF ~Pa$ 6display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz5` ~` %a$ display@14007000mediatek,mt8195-mdp3-tdshp5p ~pa$#display@14008000mediatek,mt8195-mdp3-color5I ~a$$6display@14009000mediatek,mt8195-mdp3-ovl5J ~a$%6 display@1400a000mediatek,mt8195-mdp3-padding5 ~a$6display@1400b000mediatek,mt8195-mdp3-tcc5 ~a$dma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot5 ~  +a$ 6 mutex@1400f000mediatek,mt8195-vpp-mutex5P ~a$6smi@14010000mediatek,mt8195-smi-sub-common5a$$$Rapbsmigals0 6smi@14011000mediatek,mt8195-smi-sub-common5a$$$Rapbsmigals0 6smi@14012000mediatek,mt8195-smi-common-vpp5  a$$$$Rapbsmigals0gals16larb@14013000mediatek,mt8195-smi-larb50  a$$Rapbsmi6iommu@14018000mediatek,mt8195-iommu-vpp58 /Ra$Rbclk6clock-controller@14e00000mediatek,mt8195-wpesys5T'clock-controller@14e02000mediatek,mt8195-wpesys_vpp05 Tclock-controller@14e03000mediatek,mt8195-wpesys_vpp150Tlarb@14e04000mediatek,mt8195-smi-larb5@  a''Rapbsmi6larb@14e05000mediatek,mt8195-smi-larb5P  a''$ Rapbsmigals6syscon@14f00000mediatek,mt8195-vppsys1syscon5T ~ &mutex@14f01000mediatek,mt8195-vpp-mutex5{ ~ a&'6larb@14f02000mediatek,mt8195-smi-larb5   a&&$ Rapbsmigals6larb@14f03000mediatek,mt8195-smi-larb50  a&&$ Rapbsmigals6display@14f06000mediatek,mt8195-mdp3-split5` ~ `a&&+&,6display@14f07000mediatek,mt8195-mdp3-tcc5p ~ pa&dma-controller@14f08000mediatek,mt8195-mdp3-rdma5 ~  a& 6 dma-controller@14f09000mediatek,mt8195-mdp3-rdma5 ~  a&  6 dma-controller@14f0a000mediatek,mt8195-mdp3-rdma5 ~  a&  6 display@14f0b000mediatek,mt8195-mdp3-fg5 ~ a& display@14f0c000mediatek,mt8195-mdp3-fg5 ~ a& display@14f0d000mediatek,mt8195-mdp3-fg5 ~ a& display@14f0e000mediatek,mt8195-mdp3-hdr5 ~ a&display@14f0f000mediatek,mt8195-mdp3-hdr5 ~ a&display@14f10000mediatek,mt8195-mdp3-hdr5 ~ a& display@14f11000mediatek,mt8195-mdp3-aal5i ~ a&6display@14f12000mediatek,mt8195-mdp3-aal5 j ~ a&6display@14f13000mediatek,mt8195-mdp3-aal50k ~ 0a&!6display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz5@ ~ @ a&display@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz5P ~ P a&$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz5` ~ ` a&%display@14f17000mediatek,mt8195-mdp3-tdshp5p ~ pa&display@14f18000mediatek,mt8195-mdp3-tdshp5 ~ a&(display@14f19000mediatek,mt8195-mdp3-tdshp5 ~ a&)display@14f1a000mediatek,mt8195-mdp3-merge5 ~ a&6display@14f1b000mediatek,mt8195-mdp3-merge5 ~ a&6display@14f1c000mediatek,mt8195-mdp3-color5t ~ a&6display@14f1d000mediatek,mt8195-mdp3-color5 ~ ua&6display@14f1e000mediatek,mt8195-mdp3-color5v ~ a&6display@14f1f000mediatek,mt8195-mdp3-ovl5w ~ a&6 display@14f20000mediatek,mt8195-mdp3-padding5 ~ a&6display@14f21000mediatek,mt8195-mdp3-padding5 ~ a&6display@14f22000mediatek,mt8195-mdp3-padding5  ~ a&6dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot50 ~ 0 a& 6 dma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot5@ ~ @ a& 6 dma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot5P ~ P a& 6 clock-controller@15000000mediatek,mt8195-imgsys5T.larb@15001000mediatek,mt8195-smi-larb5   a...  Rapbsmigals6smi@15002000mediatek,mt8195-smi-sub-common5 a..$Rapbsmigals0 6smi@15003000mediatek,mt8195-smi-sub-common50a... Rapbsmigals0 6clock-controller@15110000 mediatek,mt8195-imgsys1_dip_top5Tlarb@15120000mediatek,mt8195-smi-larb5   a.Rapbsmi6clock-controller@15130000mediatek,mt8195-imgsys1_dip_nr5Tclock-controller@15220000mediatek,mt8195-imgsys1_wpe5"Tlarb@15230000mediatek,mt8195-smi-larb5#   a.Rapbsmi6clock-controller@15330000mediatek,mt8195-ipesys53T/larb@15340000mediatek,mt8195-smi-larb54   a//Rapbsmi6clock-controller@16000000mediatek,mt8195-camsys5T0larb@16001000mediatek,mt8195-smi-larb5   a000 Rapbsmigals6larb@16002000mediatek,mt8195-smi-larb5   a00Rapbsmi6smi@16004000mediatek,mt8195-smi-sub-common5@a000Rapbsmigals0 6smi@16005000mediatek,mt8195-smi-sub-common5Pa00$Rapbsmigals0 6larb@16012000mediatek,mt8195-smi-larb5   aRapbsmi6 larb@16013000mediatek,mt8195-smi-larb50  aRapbsmi6 larb@16014000mediatek,mt8195-smi-larb5@  aRapbsmi6!larb@16015000mediatek,mt8195-smi-larb5P  aRapbsmi6!clock-controller@1604f000mediatek,mt8195-camsys_rawa5Tclock-controller@1606f000mediatek,mt8195-camsys_yuva5Tclock-controller@1608f000mediatek,mt8195-camsys_rawb5Tclock-controller@160af000mediatek,mt8195-camsys_yuvb5 Tclock-controller@16140000mediatek,mt8195-camsys_mraw5Tlarb@16141000mediatek,mt8195-smi-larb5  a00 Rapbsmigals6"larb@16142000mediatek,mt8195-smi-larb5   aRapbsmi6"clock-controller@17200000mediatek,mt8195-ccusys5 Tlarb@17201000mediatek,mt8195-smi-larb5   aRapbsmi6video-codec@18000000mediatek,mt8195-vcodec-dec  + 5@`video-codec@2000mediatek,mtk-vcodec-lat-soc5   a!A((!Rselvdeclattopp!A!6video-codec@10000mediatek,mtk-vcodec-lat50  a!A((!Rselvdeclattopp!A!6video-codec@25000mediatek,mtk-vcodec-core5PP  a!A))!Rselvdeclattopp!A!6larb@1800d000mediatek,mt8195-smi-larb5  a((Rapbsmi6larb@1800e000mediatek,mt8195-smi-larb5  a$(Rapbsmi6clock-controller@1800f000mediatek,mt8195-vdecsys_soc5T(larb@1802e000mediatek,mt8195-smi-larb5  a))Rapbsmi6clock-controller@1802f000mediatek,mt8195-vdecsys5T)larb@1803e000mediatek,mt8195-smi-larb5  a$*Rapbsmi6clock-controller@1803f000mediatek,mt8195-vdecsys_core15T*clock-controller@190f3000mediatek,mt8195-apusys_pll50Tclock-controller@1a000000mediatek,mt8195-vencsys5T+larb@1a010000mediatek,mt8195-smi-larb5  a++Rapbsmi6video-codec@1a020000mediatek,mt8195-vcodec-enc5H `abcdvwxyU a+ Rvenc_selp!@!6+jpeg-decoder@1a040000mediatek,mt8195-jpgdec60 mnrstu+0jpgdec@0,0mediatek,mt8195-jpgdec-hw50 mnrstuWa+Rjpgdec6jpgdec@0,10000mediatek,mt8195-jpgdec-hw50 mnrstuXa+Rjpgdec6jpgdec@1,0mediatek,mt8195-jpgdec-hw50 \a,Rjpgdec6clock-controller@1b000000mediatek,mt8195-vencsys_core15T,syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon5 T %port+endpoint@05 >jpeg-encoder@1a030000mediatek,mt8195-jpgenc6 +0jpgenc@0,0mediatek,mt8195-jpgenc-hw5 ghilVa+Rjpgenc6jpgenc@1,0mediatek,mt8195-jpgenc-hw5 [a,Rjpgenc6larb@1b010000mediatek,mt8195-smi-larb5  a,,$  Rapbsmigals6ovl@1c000000mediatek,mt8195-disp-ovl5|6a%  ports+port@05endpoint >port@15endpoint >rdma@1c002000mediatek,mt8195-disp-rdma5 ~6a%   ports+port@05endpoint >port@15endpoint >color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color506a% 0ports+port@05endpoint >port@15endpoint >ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr5@6a% @ports+port@05endpoint >port@15endpoint >aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aal5P6a% Pports+port@05endpoint >port@15endpoint >gamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma5`6a% `ports+port@05endpoint >port@15endpoint >dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-dither5p6a%  pports+port@05endpoint >port@15endpoint >dsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsi56a%%*Renginedigitalhs  Ydphy disableddsc@1c009000mediatek,mt8195-disp-dsc56a% ports+port@05endpoint >port@15endpoint >dsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi5 6a%%+Renginedigitalhs  Ydphy disabledmerge@1c014000mediatek,mt8195-disp-merge5@6a% @ports+port@05endpoint >port@15endpoint >dp-intf@1c015000mediatek,mt8195-dp-intf5P6a%,% Rpixelenginepllokayports+port@05endpoint >port@15endpoint >mutex@1c016000mediatek,mt8195-disp-mutex5`6a% ` Ularb@1c018000mediatek,mt8195-smi-larb5  a%(%($  Rapbsmigals6larb@1c019000mediatek,mt8195-smi-larb5  a%($ $ Rapbsmigals6syscon@1c100000mediatek,mt8195-vdosys1syscon5  TB-port+endpoint@15 >smi@1c01b000mediatek,mt8195-smi-common-vdo5 a%%%&%)%$Rapbsmigals0gals16iommu@1c01f000mediatek,mt8195-iommu-vdo58 /a%'Rbclk6mutex@1c101000mediatek,mt8195-disp-mutex56a-  larb@1c102000mediatek,mt8195-smi-larb5   a--- Rapbsmigals6larb@1c103000mediatek,mt8195-smi-larb50  a--$  Rapbsmigals6dma-controller@1c104000mediatek,mt8195-vdo1-rdma5@a-6 @ @ dma-controller@1c105000mediatek,mt8195-vdo1-rdma5Pa-6 ` P dma-controller@1c106000mediatek,mt8195-vdo1-rdma5`a-6 A ` dma-controller@1c107000mediatek,mt8195-vdo1-rdma5pa-6 a p dma-controller@1c108000mediatek,mt8195-vdo1-rdma5a-6 B  dma-controller@1c109000mediatek,mt8195-vdo1-rdma5a-6 b  dma-controller@1c10a000mediatek,mt8195-vdo1-rdma5a-6 C  dma-controller@1c10b000mediatek,mt8195-vdo1-rdma5a-6 c  vpp-merge@1c10c000mediatek,mt8195-disp-merge5a- -Rmergemerge_async6  N -vpp-merge@1c10d000mediatek,mt8195-disp-merge5a- -Rmergemerge_async6  N -vpp-merge@1c10e000mediatek,mt8195-disp-merge5a- -Rmergemerge_async6  N -vpp-merge@1c10f000mediatek,mt8195-disp-merge5a- -Rmergemerge_async6  N -vpp-merge@1c110000mediatek,mt8195-disp-merge5a- -Rmergemerge_async6  b -ports+port@0+5endpoint@15 >port@1+5endpoint@15 >dpi@1c112000mediatek,mt8195-dpi5 a----2Rpixelenginepll6 - disabledports+port@05endpointport@15endpointdp-intf@1c113000mediatek,mt8195-dp-intf506a-/- Rpixelenginepllokayports+port@0+5endpoint@15 >port@1+5endpoint@15 >hdr-engine@1c114000mediatek,mt8195-disp-ethdrp5@Pp4Omixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp @Ppha-%- -#-!-$-"-1-&-'-(-)-*!Rmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top6 de( -3-4-5-6-7Evdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncports+port@0+5endpoint@15 >port@1+5endpoint@15 >hdmi-tx@1c300000mediatek,mt8195-hdmi-tx50 a!Q!L!M&,Rbushdcphdcp24mhdmi-splitp!L!6  Yhdmi disabledi2cmediatek,mt8195-hdmi-ddcaports+port@05endpointport@15endpointedp-tx@1c500000mediatek,mt8195-edp-tx5PR^dp_calibration_data6 yokaydefaultports+port@05endpoint >port@15endpoint  >aux-buspanel edp-panel  portendpoint >dp-tx@1c600000mediatek,mt8195-dp-tx5`R^dp_calibration_data6 yokaydefaultports+port@0+5endpoint@15 >port@15endpoint thermal-zonescpu0-thermal   tripstrip-alert L 0passivetrip-crit   0criticalcooling-mapsmap0 0 cpu1-thermal   tripstrip-alert L 0passivetrip-crit   0criticalcooling-mapsmap0 0 cpu2-thermal   tripstrip-alert L 0passivetrip-crit   0criticalcooling-mapsmap0 0 cpu3-thermal   tripstrip-alert L 0passivetrip-crit   0criticalcooling-mapsmap0 0 cpu4-thermal   tripstrip-alert L 0passivetrip-crit   0criticalcooling-mapsmap0 0 cpu5-thermal   tripstrip-alert L 0passivetrip-crit   0criticalcooling-mapsmap0 0 cpu6-thermal   tripstrip-alert L 0passivetrip-crit   0criticalcooling-mapsmap0 0 cpu7-thermal   tripstrip-alert L 0passivetrip-crit   0criticalcooling-mapsmap0 0 vpu0-thermal   tripstrip-alert L 0passivetrip-crit   0criticalvpu1-thermal   tripstrip-alert L 0passivetrip-crit   0criticalgpu-thermal   tripstrip-alert L 0passivetrip-crit   0criticalgpu1-thermal   tripstrip-alert L 0passivetrip-crit   0criticalvdec-thermal   tripstrip-alert L 0passivetrip-crit   0criticalimg-thermal   tripstrip-alert L 0passivetrip-crit   0criticalinfra-thermal   tripstrip-alert L 0passivetrip-crit   0criticalcam0-thermal   tripstrip-alert L 0passivetrip-crit   0criticalcam1-thermal   tripstrip-alert L 0passivetrip-crit   0criticalsoc-area-thermal   tripstrip-crit H   0criticalpmic-area-thermal   tripstrip-crit H   0criticalbacklight-lcd0pwm-backlight @ 6RC Z  chosen_serial0:115200n8memory@40000000)memory5@regulator-pp3300-disp-xregulator-fixedpp3300_disp_x2Z2Z4 k ~7defaultiregulator-pp3300-ldo-z5regulator-fixedpp3300_ldo_z5P2Z2Zjregulator-pp3300-s3regulator-fixed pp3300_s3P2Z2Zifregulator-pp3300-z2regulator-fixed pp3300_z2P2Z2Ziregulator-pp4200-z2regulator-fixed pp4200_z2P@@@@regulator-pp5000-s5regulator-fixed pp5000_s5PLK@LK@regulator-ppvar-sysregulator-fixed ppvar_sysPthermal-sensor-t1generic-adc-thermalosensor-channelx~%':[N au0@] P`Gp$8L_}sk\(OD8;3H,thermal-sensor-t2generic-adc-thermalosensor-channelx~%':[N au0@] P`Gp$8L_}sk\(OD8;3H,regulator-5v0-usb-vbusregulator-fixed usb-vbusLK@LK@kPJreserved-memory+memory@50000000shared-dma-pool5P3memory@60000000shared-dma-pool5`:memory@60d80000shared-dma-pool5`<memory@60e80000shared-dma-pool5`(9rt1019prealtek,rt1019prt1019pdefault d compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1gce0gce1hdmi0ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7i2c0i2c1i2c2i2c3i2c4i2c5i2c7mmc0mmc1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellscpu-supplyphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platformmediatek,adspmediatek,dai-linkpinctrl-namespinctrl-0audio-routinglink-namemediatek,clk-providersound-dai#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesmediatek,rsel-resistance-in-si-unitgpio-line-namespinmuxinput-enablebias-pull-upbias-disabledrive-strength-microampdrive-strengthbias-pull-downoutput-highoutput-low#power-domain-cellsdomain-supplyclock-namesmediatek,infracfgassigned-clocksassigned-clock-parents#sound-dai-cellsinterrupts-extended#io-channel-cellsmediatek,dmic-modemediatek,mic-type-0regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#iommu-cells#mbox-cellsfirmware-namememory-regionmediatek,rpmsg-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namesmediatek,etdm-in2-cowork-sourcemediatek,etdm-out2-cowork-sourcemediatek,pad-selectspi-max-frequencywakeup-sourcegoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphysmediatek,syscon-wakeupdr_modevusb33-supplyrx-fifo-depthvbus-supplybus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablepinctrl-1vmmc-supplyvqmmc-supplycap-sd-highspeedcd-gpiosno-mmcsd-uhs-sdr50sd-uhs-sdr104freq-table-hzmediatek,ufs-disable-mcqmediatek,u3p-dis-mskusb2-lpm-disablebus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapspi-rx-bus-widthspi-tx-bus-widthbits#phy-cellsmediatek,ibiasmediatek,ibias_upi2c-scl-internal-delay-nsvcc-supplyrealtek,jd-srcAVDD-supplyDBVDD-supplyMICVDD-supplyLDO1-IN-supplyrealtek,btndet-delayVBAT-supplyhid-descr-addrpost-power-on-delay-msvdd-supplyoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzdata-lanespower-supplybacklightpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicebrightness-levelsdefault-brightness-levelenable-gpiosnum-interpolated-stepspwmsstdout-pathenable-active-highgpiovin-supplyregulator-boot-onio-channelsio-channel-namestemperature-lookup-tableno-maplabelsdb-gpios