Q8F( F%mediatek,mt8195-demomediatek,mt8195 +7MediaTek MT8195 demo boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/mailbox@10320000Y/soc/mailbox@10330000^/soc/hdmi-tx@1c300000d/soc/hdr-engine@1c114000k/soc/mutex@1c016000r/soc/mutex@1c101000y/soc/vpp-merge@1c10c000/soc/vpp-merge@1c10d000/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55 psci.ec3@>4Qan@@ cpu@100cpuarm,cortex-a55 psci.ec3@>4Qan@@ cpu@200cpuarm,cortex-a55 psci.ec3@>4Qan@@ cpu@300cpuarm,cortex-a55 psci.ec3@>4Qan@@ cpu@400cpuarm,cortex-a78 psci.f>Qan@@ cpu@500cpuarm,cortex-a78 psci.f>Qan@@cpu@600cpuarm,cortex-a78 psci.f>Qan@@cpu@700cpuarm,cortex-a78 psci.f>Qan@@cpu-mapcluster0core0 core1 core2 core3 core4 core5core6core7idle-statespscicpu-retention-larm,idle-state 2+_;Dcpu-retention-barm,idle-state -+;cpu-off-larm,idle-state 7+;Hcpu-off-barm,idle-state 2+;l2-cache0cacheLcp@Xl2-cache1cacheLcp@Xl3-cachecacheLc p@Xdsu-pmu arm,dsu-pmuf q vfaildmic-codec dmic-codec}2mt8195-sound vdisabledfixed-factor-clock-13mfixed-factor-clockclk13m(oscillator-26m fixed-clock.clk26moscillator-32k fixed-clock.clk32kperformance-controller@11bc10mediatek,cpufreq-hw  0 opp-table-gpuoperating-points-v2aopp-390000000 > hopp-410000000 p opp-431000000  opp-473000000 1h@ <opp-515000000 F <opp-556000000 !# Ҧopp-598000000 # opp-640000000 &% opp-670000000 'c opp-700000000 )' Lopp-730000000 + }opp-760000000 -L `opp-790000000 /q 4opp-820000000 05 opp-850000000 2 @opp-880000000 4s qpmu-a55arm,cortex-a55-pmu fpmu-a78arm,cortex-a78-pmu fpsci arm,psci-1.0smctimerarm,armv8-timer @f   soc+ simple-bus")interrupt-controller@c000000 arm,gic-v34E \    f ppi-partitionsinterrupt-partition-0q interrupt-partition-1q syscon@10000000 mediatek,mt8195-topckgensysconsyscon@10001000#mediatek,mt8195-infracfg_aosysconzsyscon@10003000mediatek,mt8195-pericfgsyscon0;pinctrl@10005000mediatek,mt8195-pinctrlPBiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint\f4eth-default-pins7pins-txdMNOPpins-ccUXWVpins-rxdQRSTpins-mdioYZpins-power[\eth-sleep-pins8pins-txdMNOPpins-ccUXWVpins-rxdQRSTpins-mdioYZgpio-keys-pinspinsji2c6-pinsPpinsmmc0-default-pins>pins-clkzfpins-cmd-dat$~}|{wvutyepins-rstxemmc0-uhs-pins?pins-clkzfpins-cmd-dat$~}|{wvutyepins-dsfpins-rstxemmc1-default-pinsBpins-clkofpins-cmd-datnpqrsepins-insertmmc1-uhs-pinsCpins-clkofpins-cmd-datnpqrseuart0-pins.pinsbcuart1-pins/pinsfgsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+*power-domain@8+power-domain@9 3mfgalt?+power-domain@10 power-domain@11 power-domain@12 power-domain@13 power-domain@14power-domain@15 @AK   3vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18?+power-domain@168$%&'()D3vdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5?+power-domain@173vppsys1vppsys1-0vppsys1-1?power-domain@22 $3wepsys-0wepsys-1wepsys-2wepsys-3?power-domain@233vdec0-0?+power-domain@243vdec1-0?power-domain@25 3vdec2-0?power-domain@26! 3venc0-larb?+power-domain@27" 3venc1-larb?power-domain@18 ###&3vdosys1vdosys1-0vdosys1-1vdosys1-2?+power-domain@19?power-domain@20?power-domain@21Q3hdmi_txpower-domain@28$$  3img-0img-1?+power-domain@29power-domain@30$%3ipeipe-0ipe-1?power-domain@31(&&&&&3cam-0cam-1cam-2cam-3cam-4?+power-domain@32 power-domain@33!power-domain@34"power-domain@0?power-domain@1?power-domain@2power-domain@3power-domain@4573csi_rx_topcsi_rx_top1power-domain@5' 3etherpower-domain@6Xn 3adspadsp1+?power-domain@7 g"n23audioaudio1audio2audio3?watchdog@10007000mediatek,mt8195-wdtQpz-syscon@1000c000"mediatek,mt8195-apmixedsyssyscontimer@10017000,mediatek,mt8195-timermediatek,mt6765-timerpf (pwrap@10024000mediatek,mt8195-pwrapsyscon@pwrapf 3spiwrapi$ypmicmediatek,mt6359\4 adcmediatek,mt6359-auxadcaudio-codecmediatek,mt6359-codecregulatorsmediatek,mt6359-regulatorbuck_vs1vs1 5!"buck_vgpu11vgpu1176 K"buck_vmodemvmodem6*buck_vpuvpu76 K"buck_vcorevcore 6 K"buck_vs2vs2 5j"buck_vpavpa 7,buck_vproc2vproc276L K"buck_vproc1vproc176L K"buck_vcore_sshub vcore_sshub7buck_vgpu11_sshub vgpu11_sshub7ldo_vaud18vaud18w@w@ldo_vsim1vsim1/M`ldo_vibrvibrO2Zldo_vrf12vrf12 "ldo_vusbvusb--"<ldo_vsram_proc2 vsram_proc2 6L"ldo_vio18vio18"ldo_vcamiovcamioldo_vcn18vcn18w@w@ldo_vfe28vfe28**xldo_vcn13vcn13  ldo_vcn33_1_bt vcn33_1_bt*5gldo_vcn33_1_wifi vcn33_1_wifi*5gldo_vaux18vaux18w@w@"ldo_vsram_others vsram_others 6"ldo_vefusevefuseldo_vxo22vxo22w@!"ldo_vrfckvrfck`ldo_vrfck_1vrfckjldo_vbif28vbif28**ldo_vio28vio28*2Z"ldo_vemcvemc,@ 2Zldo_vemc_1vemc&%2Z@ldo_vcn33_2_bt vcn33_2_bt*5gldo_vcn33_2_wifi vcn33_2_wifi*5gldo_va12va12O "ldo_va09va09 5Oldo_vrf18vrf18Pldo_vsram_md vsram_md 6*"ldo_vufsvufsAldo_vm18vm18"ldo_vbbckvbbckO"ldo_vsram_proc1 vsram_proc1 6L"ldo_vsim2vsim2/M`ldo_vsram_others_sshubvsram_others_sshub rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi p pmifspmimstE(3pmif_sys_ckpmif_tmr_ckspmimst_clk_muxi$yinfra-iommu@10315000mediatek,mt8195-iommu-infra1PPPfcKmailbox@10320000mediatek,mt8195-gce2@fpmailbox@10330000mediatek,mt8195-gce3@fpbscp@10500000mediatek,mt8195-scp0Prpsramcfgl1tcmf vdisabledcclock-controller@10720000mediatek,mt8195-scp_adspr)dsp@10803000mediatek,mt8195-dsp 0 cfgsram,Xn)#K3adsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h|*rxtx+, vdisabledmailbox@10816000mediatek,mt8195-adsp-mboxp`f+mailbox@10817000mediatek,mt8195-adsp-mboxppf,mt8195-afe-pcm@10890000mediatek,mt8195-audio|*f6- audiosysg"#neabcd2)3clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp vdisabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uartf  3baudbusvokaydefault.serial@11001200*mediatek,mt8195-uartmediatek,mt6577-uartf  3baudbusvokaydefault/serial@11001300*mediatek,mt8195-uartmediatek,mt6577-uartf  3baudbus vdisabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uartf  3baudbus vdisabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uartf  3baudbus vdisabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uartf  3baudbus vdisabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc 3main vdisabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon0'spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+f3parent-clksel-clkspi-clk vdisabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap f01$lvts-calib-data-1lvts-calib-data-2svs@1100bc00mediatek,mt8195-svsf3main20(svs-calibration-datat-calibration-datasvs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmf|* *03mainmm vdisabledpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmf +N3mainmm vdisabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+f33parent-clksel-clkspi-clk vdisabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ f43parent-clksel-clkspi-clk vdisabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+0f53parent-clksel-clkspi-clk vdisabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+f<3parent-clksel-clkspi-clk vdisabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+f=3parent-clksel-clkspi-clk vdisabledspi@1101d000mediatek,mt8195-spi-slavefR3spiiy vdisabledspi@1101e000mediatek,mt8195-spi-slavefS3spiiy vdisabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a@fmacirq.3axiapbmac_mainptp_refrmii_internalmac_cg0''RST' iRSTy|*'83H4[5nyvokay rgmii-id6 ] '8defaultsleep78mdiosnps,dwmac-mdio+ethernet-phy@16stmmac-axi-config3rx-queues-config%4queue06Iqueue16Iqueue26Iqueue36Itx-queues-configaw5queue06queue16queue26queue36usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3  - > macippc" ?+f/B3sys_ckref_ckmcu_ck9: ;gvokay<usb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimacfi,-y$/B$3sys_ckref_ckmcu_ckdma_ckxhci_ckvokay=mmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #f3sourcehclksource_cgvokaydefaultstate_uhs>?  /@HNL]@iAvmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc $f$3sourcehclksource_cgiyvokaydefaultstate_uhsBC  ]DiEmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %f I3sourcehclksource_cgi y vdisabledufshci@11270000mediatek,mt8195-ufshci'#fF@?@A678Z]X3ufsufs_aesufs_tickunipro_sysclkunipro_tickunipro_mp_bclkufs_tx_symbolufs_mem_sub@ vdisabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu'f01$lvts-calib-data-1lvts-calib-data-2usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ))> macippcfGHi./y$''$3sys_ckref_ckmcu_ckdma_ckxhci_ck ;hvokay<usb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 *-*> macippc"*?+fi0y''3sys_ckref_ckmcu_ckI ;ivokay<usb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimacfi1y'3sys_ckvokayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 +-+> macippc"+?+fi2y'' 3sys_ckref_ckmcu_ckJ ;jvokay<usb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimacfi3y' 3sys_ckvokaypcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ pcie-macf8" K0V#&+K'/3pl_250mtl_26mtl_96mtl_32kperi_26mperi_memiGyL pcie-phy|*4 ` MMMM vdisabledinterrupt-controller\4Mpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ pcie-macf8"$$ $ $ K(WXQ'/3pl_250mtl_26mtl_96mtl_32kperi_26mperi_memiHyH pcie-phy|*4 ` NNNN vdisabledinterrupt-controller\4Nspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor2f9o'' 3spisfaxi+ vdisabledefuse@11c10000%mediatek,mt8195-efusemediatek,efuse+usb3-tx-imp@184,1 .Xusb3-rx-imp@184,2 .Wusb3-intr@185 .Vusb3-tx-imp@186,1 .Uusb3-rx-imp@186,2 .Tusb3-intr@187 .Susb2-intr-p0@188,1 .usb2-intr-p1@188,2 .usb2-intr-p2@189,1 .usb2-intr-p3@189,2 .pciephy-rx-ln1@190,1 ._pciephy-tx-ln1-nmos@190,2 .^pciephy-tx-ln1-pmos@191,1 .]pciephy-rx-ln0@191,2 .\pciephy-tx-ln0-nmos@192,1 .[pciephy-tx-ln0-pmos@192,2 .Zpciephy-glb-intr@193 .Ydp-data@1aclvts1-calib@1bc0lvts2-calib@1d081svs-calib@580d2socinfo-data1@7a0t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"vokayusb-phy@03ref 3It-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"vokayusb-phy@03ref 3Jdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx0_pll 3 vdisableddsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx1_pll 3 vdisabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "fO; 3maindma+ vdisabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "fO; 3maindma+vokay.Pdefaultpmic@34mediatek,mt63604\4 eIRQBchargermediatek,mt6360-chg >@usb-otg-vbus-regulator usb-otg-vbusC(X=regulatormediatek,mt6360-regulator WQbuck1 mt6360,buck1  K"buck2 mt6360,buck2  K"Qldo1 mt6360,ldo1O6Kldo2 mt6360,ldo2O6Kldo3 mt6360,ldo3O6KEldo5 mt6360,ldo5)26KDldo6 mt6360,ldo6  Kldo7 mt6360,ldo7  K"i2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "fO; 3maindma+ vdisabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s0Ohdmi-phy@11d5f000mediatek,mt8195-hdmi-phy P  3pll_ref26mpll1pll2 hdmi_txpll 3 g  v vdisabledi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "fR; 3maindma+ vdisabledi2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "fR; 3maindma+ vdisabledi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "fR; 3maindma+ vdisabledi2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 0"fR; 3maindma+ vdisabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c @"fR; 3maindma+ vdisabledclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wPRt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"|*vokayusb-phy@0  3refda_ref 3Gusb-phy@700 3refda_ref STUintrrx_imptx_imp 3Ht-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"vokayusb-phy@0  3refda_ref 39usb-phy@700 3refda_ref VWXintrrx_imptx_imp 3:phy@11e80000mediatek,mt8195-pcie-physifYZ[\]^_Gglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1|* 3 vdisabledLufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy 3unipromp 3 vdisabledFgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm@`0f jobmmugpu a(|* * * * * core0core1core2core3core4 vdisabledclock-controller@13fbf000mediatek,mt8195-mfgcfg`syscon@14000000mediatek,mt8195-vppsys0syscon bdma-controller@14001000mediatek,mt8195-mdp3-rdma b   c|* d<b b bbb display@14002000mediatek,mt8195-mdp3-fg  b display@14003000mediatek,mt8195-mdp3-stitch0 b0display@14004000mediatek,mt8195-mdp3-hdr@ b@"display@14005000mediatek,mt8195-mdp3-aalPfF bP |*display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz` b` % display@14007000mediatek,mt8195-mdp3-tdshpp bp#display@14008000mediatek,mt8195-mdp3-colorfI b$|*display@14009000mediatek,mt8195-mdp3-ovlfJ b%|* ddisplay@1400a000mediatek,mt8195-mdp3-padding b|*display@1400b000mediatek,mt8195-mdp3-tcc bdma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot b  + d|* mutex@1400f000mediatek,mt8195-vpp-mutexfP b|*smi@14010000mediatek,mt8195-smi-sub-common3apbsmigals0 e|*fsmi@14011000mediatek,mt8195-smi-sub-common3apbsmigals0 e|*smi@14012000mediatek,mt8195-smi-common-vpp  3apbsmigals0gals1|*elarb@14013000mediatek,mt8195-smi-larb0  f3apbsmi|*iiommu@14018000mediatek,mt8195-iommu-vpp8 ghijklmnopqrstfR3bclkc|*dclock-controller@14e00000mediatek,mt8195-wpesysclock-controller@14e02000mediatek,mt8195-wpesys_vpp0 clock-controller@14e03000mediatek,mt8195-wpesys_vpp10larb@14e04000mediatek,mt8195-smi-larb@  u3apbsmi|*larb@14e05000mediatek,mt8195-smi-larbP  e 3apbsmigals|*ksyscon@14f00000mediatek,mt8195-vppsys1syscon b mutex@14f01000mediatek,mt8195-vpp-mutexf{ b '|*larb@14f02000mediatek,mt8195-smi-larb   u 3apbsmigals|*larb@14f03000mediatek,mt8195-smi-larb0  f 3apbsmigals|*jdisplay@14f06000mediatek,mt8195-mdp3-split` b `+,|*display@14f07000mediatek,mt8195-mdp3-tccp b pdma-controller@14f08000mediatek,mt8195-mdp3-rdma b   v|* dma-controller@14f09000mediatek,mt8195-mdp3-rdma b    v|* dma-controller@14f0a000mediatek,mt8195-mdp3-rdma b    d|* display@14f0b000mediatek,mt8195-mdp3-fg b  display@14f0c000mediatek,mt8195-mdp3-fg b  display@14f0d000mediatek,mt8195-mdp3-fg b  display@14f0e000mediatek,mt8195-mdp3-hdr b display@14f0f000mediatek,mt8195-mdp3-hdr b display@14f10000mediatek,mt8195-mdp3-hdr b  display@14f11000mediatek,mt8195-mdp3-aalfi b |*display@14f12000mediatek,mt8195-mdp3-aal fj b |*display@14f13000mediatek,mt8195-mdp3-aal0fk b 0!|*display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz@ b @ display@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszP b P $display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz` b ` %display@14f17000mediatek,mt8195-mdp3-tdshpp b pdisplay@14f18000mediatek,mt8195-mdp3-tdshp b (display@14f19000mediatek,mt8195-mdp3-tdshp b )display@14f1a000mediatek,mt8195-mdp3-merge b |*display@14f1b000mediatek,mt8195-mdp3-merge b |*display@14f1c000mediatek,mt8195-mdp3-colorft b |*display@14f1d000mediatek,mt8195-mdp3-color b fu|*display@14f1e000mediatek,mt8195-mdp3-colorfv b |*display@14f1f000mediatek,mt8195-mdp3-ovlfw b |* vdisplay@14f20000mediatek,mt8195-mdp3-padding b |*display@14f21000mediatek,mt8195-mdp3-padding b |*display@14f22000mediatek,mt8195-mdp3-padding  b |*dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot0 b 0  v|* dma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot@ b @  v|* dma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotP b P  d|* clock-controller@15000000mediatek,mt8195-imgsys$larb@15001000mediatek,mt8195-smi-larb   w$$$  3apbsmigals|*smi@15002000mediatek,mt8195-smi-sub-common $$3apbsmigals0 e|*zsmi@15003000mediatek,mt8195-smi-sub-common0$$$ 3apbsmigals0 u|*wclock-controller@15110000 mediatek,mt8195-imgsys1_dip_topxlarb@15120000mediatek,mt8195-smi-larb   w$x3apbsmi|*clock-controller@15130000mediatek,mt8195-imgsys1_dip_nrclock-controller@15220000mediatek,mt8195-imgsys1_wpe"ylarb@15230000mediatek,mt8195-smi-larb#   w$y3apbsmi|*clock-controller@15330000mediatek,mt8195-ipesys3%larb@15340000mediatek,mt8195-smi-larb4   z%%3apbsmi|*lclock-controller@16000000mediatek,mt8195-camsys&larb@16001000mediatek,mt8195-smi-larb   {&&& 3apbsmigals|*larb@16002000mediatek,mt8195-smi-larb   |&&3apbsmi|*msmi@16004000mediatek,mt8195-smi-sub-common@&&&3apbsmigals0 u|*{smi@16005000mediatek,mt8195-smi-sub-commonP&&3apbsmigals0 e|*|larb@16012000mediatek,mt8195-smi-larb   |}}3apbsmi|* nlarb@16013000mediatek,mt8195-smi-larb0  {~~3apbsmi|* larb@16014000mediatek,mt8195-smi-larb@  |3apbsmi|*!tlarb@16015000mediatek,mt8195-smi-larbP  {3apbsmi|*!clock-controller@1604f000mediatek,mt8195-camsys_rawa}clock-controller@1606f000mediatek,mt8195-camsys_yuva~clock-controller@1608f000mediatek,mt8195-camsys_rawbclock-controller@160af000mediatek,mt8195-camsys_yuvb clock-controller@16140000mediatek,mt8195-camsys_mrawlarb@16141000mediatek,mt8195-smi-larb  {&& 3apbsmigals|*"larb@16142000mediatek,mt8195-smi-larb   |3apbsmi|*"sclock-controller@17200000mediatek,mt8195-ccusys larb@17201000mediatek,mt8195-smi-larb   |3apbsmi|*ovideo-codec@18000000mediatek,mt8195-vcodec-dec c v+ @"`video-codec@2000mediatek,mtk-vcodec-lat-soc  dd A3selvdeclattopiAy|*video-codec@10000mediatek,mtk-vcodec-latf0 vvvvvv A3selvdeclattopiAy|*video-codec@25000mediatek,mtk-vcodec-corePfP vvvvvvvvvv A3selvdeclattopiAy|*larb@1800d000mediatek,mt8195-smi-larb  u3apbsmi|*larb@1800e000mediatek,mt8195-smi-larb  3apbsmi|*rclock-controller@1800f000mediatek,mt8195-vdecsys_soclarb@1802e000mediatek,mt8195-smi-larb  u3apbsmi|*clock-controller@1802f000mediatek,mt8195-vdecsyslarb@1803e000mediatek,mt8195-smi-larb   3apbsmi|*qclock-controller@1803f000mediatek,mt8195-vdecsys_core1 clock-controller@190f3000mediatek,mt8195-apusys_pll0clock-controller@1a000000mediatek,mt8195-vencsys!larb@1a010000mediatek,mt8195-smi-larb  u!!3apbsmi|*video-codec@1a020000mediatek,mt8195-vcodec-encH v`vavbvcvdvvvwvxvyfU c! 3venc_seli@y|*+jpeg-decoder@1a040000mediatek,mt8195-jpgdec|*0 vmvnvrvsvtvu+0"jpgdec@0,0mediatek,mt8195-jpgdec-hw0 vmvnvrvsvtvufW!3jpgdec|*jpgdec@0,10000mediatek,mt8195-jpgdec-hw0 vmvnvrvsvtvufX!3jpgdec|*jpgdec@1,0mediatek,mt8195-jpgdec-hw0 ddddddf\"3jpgdec|*clock-controller@1b000000mediatek,mt8195-vencsys_core1"syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon  jpeg-encoder@1a030000mediatek,mt8195-jpgenc|* dddd+0"jpgenc@0,0mediatek,mt8195-jpgenc-hw vgvhvivlfV!3jpgenc|*jpgenc@1,0mediatek,mt8195-jpgenc-hw ddddf["3jpgenc|*larb@1b010000mediatek,mt8195-smi-larb  e""  3apbsmigals|*povl@1c000000mediatek,mt8195-disp-ovlf||* v ports+port@0endpointport@1endpoint 'rdma@1c002000mediatek,mt8195-disp-rdma f~|* v  ports+port@0endpoint 'port@1endpoint 'color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color0f|* 0ports+port@0endpoint 'port@1endpoint 'ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr@f|* @ports+port@0endpoint 'port@1endpoint 'aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aalPf|* Pports+port@0endpoint 'port@1endpoint 'gamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma`f|* `ports+port@0endpoint 'port@1endpoint 'dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-ditherpf|*  pports+port@0endpoint 'port@1endpointdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsif|**3enginedigitalhs dphy vdisableddsc@1c009000mediatek,mt8195-disp-dscf|* dsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi f|*+3enginedigitalhs dphy vdisabledmerge@1c014000mediatek,mt8195-disp-merge@f|* @dp-intf@1c015000mediatek,mt8195-dp-intfPf|*,3pixelenginepll vdisabledmutex@1c016000mediatek,mt8195-disp-mutex`f|* ` Ularb@1c018000mediatek,mt8195-smi-larb  u((  3apbsmigals|*larb@1c019000mediatek,mt8195-smi-larb  e(  3apbsmigals|*gsyscon@1c100000mediatek,mt8195-vdosys1syscon  z#smi@1c01b000mediatek,mt8195-smi-common-vdo %&)$3apbsmigals0gals1|*uiommu@1c01f000mediatek,mt8195-iommu-vdo8 fc'3bclk|*vmutex@1c101000mediatek,mt8195-disp-mutexf|*#  larb@1c102000mediatek,mt8195-smi-larb   u### 3apbsmigals|*larb@1c103000mediatek,mt8195-smi-larb0  e##  3apbsmigals|*hdma-controller@1c104000mediatek,mt8195-vdo1-rdma@f#|* v@ @ dma-controller@1c105000mediatek,mt8195-vdo1-rdmaPf#|* d` P dma-controller@1c106000mediatek,mt8195-vdo1-rdma`f#|* vA ` dma-controller@1c107000mediatek,mt8195-vdo1-rdmapf#|* da p dma-controller@1c108000mediatek,mt8195-vdo1-rdmaf#|* vB  dma-controller@1c109000mediatek,mt8195-vdo1-rdmaf#|* db  dma-controller@1c10a000mediatek,mt8195-vdo1-rdmaf#|* vC  dma-controller@1c10b000mediatek,mt8195-vdo1-rdmaf#|* dc  vpp-merge@1c10c000mediatek,mt8195-disp-mergef# #3mergemerge_async|*  7#vpp-merge@1c10d000mediatek,mt8195-disp-mergef# #3mergemerge_async|*  7#vpp-merge@1c10e000mediatek,mt8195-disp-mergef# #3mergemerge_async|*  7#vpp-merge@1c10f000mediatek,mt8195-disp-mergef# #3mergemerge_async|*  7#vpp-merge@1c110000mediatek,mt8195-disp-mergef# #3mergemerge_async|*  K#dpi@1c112000mediatek,mt8195-dpi #-##23pixelenginepllf|*# vdisabledports+port@0endpointport@1endpointdp-intf@1c113000mediatek,mt8195-dp-intf0f|*#/#3pixelenginepll vdisabledhdr-engine@1c114000mediatek,mt8195-disp-ethdrp@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp @Pph#%# ###!#$#"#1#&#'#(#)#*3mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top|* dddef(#3#4#5#6#7Evdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asynchdmi-tx@1c300000mediatek,mt8195-hdmi-tx0 QLM,3bushdcphdcp24mhdmi-splitiLyf|* hdmi vdisabledi2cmediatek,mt8195-hdmi-ddcports+port@0endpointport@1endpointedp-tx@1c500000mediatek,mt8195-edp-txPdp_calibration_data|*f b vdisableddp-tx@1c600000mediatek,mt8195-dp-tx`dp_calibration_data|*f b vdisabledthermal-zonescpu0-thermal s  tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu1-thermal s  tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu2-thermal s  tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu3-thermal s  tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu4-thermal s  tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu5-thermal s  tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu6-thermal s  tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu7-thermal s  tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 vpu0-thermal s  tripstrip-alert L passivetrip-crit   criticalvpu1-thermal s  tripstrip-alert L passivetrip-crit   criticalgpu-thermal s  tripstrip-alert L passivetrip-crit   criticalgpu1-thermal s  tripstrip-alert L passivetrip-crit   criticalvdec-thermal s  tripstrip-alert L passivetrip-crit   criticalimg-thermal s  tripstrip-alert L passivetrip-crit   criticalinfra-thermal s  tripstrip-alert L passivetrip-crit   criticalcam0-thermal s  tripstrip-alert L passivetrip-crit   criticalcam1-thermal s  tripstrip-alert L passivetrip-crit   criticalchosen serial0:921600n8firmwareopteelinaro,optee-tzsmcgpio-keys gpio-keysdefaultkey-0 j volume_up s memory@40000000memory@reserved-memory+"optee@43200000 C memory@50000000shared-dma-poolP memory@53000000shared-dma-poolS@memory@54600000 T` memory@60000000shared-dma-pool` memory@62000000shared-dma-poolb@ compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1gce0gce1hdmi0ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxdrive-strengthinput-enableoutput-highinput-disablebias-disablebias-pull-upbias-pull-down#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#sound-dai-cellsinterrupts-extended#io-channel-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#iommu-cells#mbox-cellspower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-namespinctrl-0nvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlesnps,reset-gpiosnps,reset-delays-uspinctrl-1mediatek,mac-wolsnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphyswakeup-sourcemediatek,syscon-wakeupvusb33-supplyvbus-supplybus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecd-gpioscap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104freq-table-hzmediatek,ufs-disable-mcqbus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapbits#phy-cellsrichtek,vinovp-microvoltLDO_VIN3-supplymediatek,ibiasmediatek,ibias_upoperating-points-v2power-domain-namesmediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathlabellinux,codedebounce-intervalno-map