.t8%(%p$mediatek,mt8195-evbmediatek,mt8195 +!7MediaTek MT8195 evaluation boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/mailbox@10320000Y/soc/mailbox@10330000^/soc/hdmi-tx@1c300000d/soc/hdr-engine@1c114000k/soc/mutex@1c016000r/soc/mutex@1c101000y/soc/vpp-merge@1c10c000/soc/vpp-merge@1c10d000/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55 psci.ec3@>4Qan@@ cpu@100cpuarm,cortex-a55 psci.ec3@>4Qan@@ cpu@200cpuarm,cortex-a55 psci.ec3@>4Qan@@ cpu@300cpuarm,cortex-a55 psci.ec3@>4Qan@@ cpu@400cpuarm,cortex-a78 psci.f>Qan@@ cpu@500cpuarm,cortex-a78 psci.f>Qan@@cpu@600cpuarm,cortex-a78 psci.f>Qan@@cpu@700cpuarm,cortex-a78 psci.f>Qan@@cpu-mapcluster0core0 core1 core2 core3 core4 core5core6core7idle-statespscicpu-retention-larm,idle-state 2+_;Dcpu-retention-barm,idle-state -+;cpu-off-larm,idle-state 7+;Hcpu-off-barm,idle-state 2+;l2-cache0cacheLcp@Xl2-cache1cacheLcp@Xl3-cachecacheLc p@Xdsu-pmu arm,dsu-pmuf q vfaildmic-codec dmic-codec}2mt8195-sound vdisabledfixed-factor-clock-13mfixed-factor-clockclk13m(oscillator-26m fixed-clock.clk26moscillator-32k fixed-clock.clk32kperformance-controller@11bc10mediatek,cpufreq-hw  0 opp-table-gpuoperating-points-v2Vopp-390000000 > hopp-410000000 p opp-431000000  opp-473000000 1h@ <opp-515000000 F <opp-556000000 !# Ҧopp-598000000 # opp-640000000 &% opp-670000000 'c opp-700000000 )' Lopp-730000000 + }opp-760000000 -L `opp-790000000 /q 4opp-820000000 05 opp-850000000 2 @opp-880000000 4s qpmu-a55arm,cortex-a55-pmu fpmu-a78arm,cortex-a78-pmu fpsci arm,psci-1.0smctimerarm,armv8-timer @f   soc+ simple-bus")interrupt-controller@c000000 arm,gic-v34E \    f ppi-partitionsinterrupt-partition-0q interrupt-partition-1q syscon@10000000 mediatek,mt8195-topckgensysconsyscon@10001000#mediatek,mt8195-infracfg_aosysconzsyscon@10003000mediatek,mt8195-pericfgsyscon07pinctrl@10005000mediatek,mt8195-pinctrlPBiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint\f4i2c0-pinsEpins ei2c1-pinsFpins  ei2c4-pinsGpinsei2c6-pinsCpinsei2c7-pinspinsenor-pinsApins0 pins1 uart0-pins.pinsbcsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+*power-domain@8+power-domain@9 mfgalt#+power-domain@10 power-domain@11 power-domain@12 power-domain@13 power-domain@14power-domain@15 @AK   vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18#+power-domain@168$%&'()Dvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5#+power-domain@17vppsys1vppsys1-0vppsys1-1#power-domain@22 $wepsys-0wepsys-1wepsys-2wepsys-3#power-domain@23vdec0-0#+power-domain@24vdec1-0#power-domain@25 vdec2-0#power-domain@26! venc0-larb#+power-domain@27" venc1-larb#power-domain@18 ###&vdosys1vdosys1-0vdosys1-1vdosys1-2#+power-domain@19#power-domain@20#power-domain@21Qhdmi_txpower-domain@28$$  img-0img-1#+power-domain@29power-domain@30$%ipeipe-0ipe-1#power-domain@31(&&&&&cam-0cam-1cam-2cam-3cam-4#+power-domain@32 power-domain@33!power-domain@34"power-domain@0#power-domain@1#power-domain@2power-domain@3power-domain@457csi_rx_topcsi_rx_top1power-domain@5' etherpower-domain@6Xn adspadsp1+#power-domain@7 g"n2audioaudio1audio2audio3#watchdog@10007000mediatek,mt8195-wdt5pz-syscon@1000c000"mediatek,mt8195-apmixedsyssyscontimer@10017000,mediatek,mt8195-timermediatek,mt6765-timerpf (pwrap@10024000mediatek,mt8195-pwrapsyscon@pwrapf spiwrapM$]spmi@10027000mediatek,mt8195-spmi p pmifspmimstE(pmif_sys_ckpmif_tmr_ckspmimst_clk_muxM$]infra-iommu@10315000mediatek,mt8195-iommu-infra1PPPft=mailbox@10320000mediatek,mt8195-gce2@fymailbox@10330000mediatek,mt8195-gce3@fWscp@10500000mediatek,mt8195-scp0Prpsramcfgl1tcmf vdisabledXclock-controller@10720000mediatek,mt8195-scp_adspr)dsp@10803000mediatek,mt8195-dsp 0 cfgsram,Xn)#Kadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h*rxtx+, vdisabledmailbox@10816000mediatek,mt8195-adsp-mbox`f+mailbox@10817000mediatek,mt8195-adsp-mboxpf,mt8195-afe-pcm@10890000mediatek,mt8195-audio*f6- audiosysg"#neabcd2)clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp vdisabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uartf  baudbusvokaydefault.serial@11001200*mediatek,mt8195-uartmediatek,mt6577-uartf  baudbus vdisabledserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uartf  baudbus vdisabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uartf  baudbus vdisabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uartf  baudbus vdisabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uartf  baudbus vdisabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc mainvokaysyscon@11003000"mediatek,mt8195-pericfg_aosyscon0'spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+fparent-clksel-clkspi-clk vdisabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap f/0$lvts-calib-data-1lvts-calib-data-2svs@1100bc00mediatek,mt8195-svsfmain1/(svs-calibration-datat-calibration-datasvs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmf*/*0mainmm vdisabledpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmf/+Nmainmm vdisabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+f3parent-clksel-clkspi-clk vdisabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ f4parent-clksel-clkspi-clk vdisabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+0f5parent-clksel-clkspi-clk vdisabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+f<parent-clksel-clkspi-clk vdisabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+f=parent-clksel-clkspi-clk vdisabledspi@1101d000mediatek,mt8195-spi-slavefRspiM] vdisabledspi@1101e000mediatek,mt8195-spi-slavefSspiM] vdisabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a@f:macirq.axiapbmac_mainptp_refrmii_internalmac_cg0''RST' MRST]*J[2k3~4 vdisabledmdiosnps,dwmac-mdio+stmmac-axi-config2rx-queues-config3queue0queue1queue2queue3tx-queues-config0F4queue0Xdqueue1Xdqueue2Xdqueue3Xdusb@11201000#mediatek,mt8195-mtu3mediatek,mtu3  - > macippc" ?+f/Bsys_ckref_ckmcu_ckr56w 7gvokayusb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimacfM,-]$/B$sys_ckref_ckmcu_ckdma_ckxhci_ckvokaymmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #fsourcehclksource_cg vdisabledmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc $f$sourcehclksource_cgM] vdisabledmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %f Isourcehclksource_cgM ] vdisabledufshci@11270000mediatek,mt8195-ufshci'#fr8@?@A678Z]Xufsufs_aesufs_tickunipro_sysclkunipro_tickunipro_mp_bclkufs_tx_symbolufs_mem_sub@ vdisabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu'f/0$lvts-calib-data-1lvts-calib-data-2usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ))> macippcfr9:M./]$''$sys_ckref_ckmcu_ckdma_ckxhci_ck 7hwvokayusb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 *-*> macippc"*?+fM0]''sys_ckref_ckmcu_ckr;w 7ivokayusb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimacfM1]'sys_ckvokayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 +-+> macippc"+?+fM2]'' sys_ckref_ckmcu_ckr<w 7jvokayusb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimacfM3]' sys_ckvokaypcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ pcie-macf8" =0V#&+K'/pl_250mtl_26mtl_96mtl_32kperi_26mperi_memMG]r> pcie-phy*4`???? vdisabledinterrupt-controller\4?pcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ pcie-macf8"$$ $ $ =(WXQ'/pl_250mtl_26mtl_96mtl_32kperi_26mperi_memMH]r: pcie-phy*4`@@@@ vdisabledinterrupt-controller\4@spi@1132c000(mediatek,mt8195-normediatek,mt8173-nor2f9o'' spisfaxi+vokaydefaultAflash@0jedec,spi-nor"efuse@11c10000%mediatek,mt8195-efusemediatek,efuse+usb3-tx-imp@184,14Musb3-rx-imp@184,24Lusb3-intr@1854Kusb3-tx-imp@186,14Jusb3-rx-imp@186,24Iusb3-intr@1874Husb2-intr-p0@188,14usb2-intr-p1@188,24usb2-intr-p2@189,14usb2-intr-p3@189,24pciephy-rx-ln1@190,14Tpciephy-tx-ln1-nmos@190,24Spciephy-tx-ln1-pmos@191,14Rpciephy-rx-ln0@191,24Qpciephy-tx-ln0-nmos@192,14Ppciephy-tx-ln0-pmos@192,24Opciephy-glb-intr@1934Ndp-data@1aclvts1-calib@1bc/lvts2-calib@1d080svs-calib@580d1socinfo-data1@7a0t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"vokayusb-phy@0ref9;t-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"vokayusb-phy@0ref9<dsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx0_pll9 vdisableddsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx1_pll9 vdisabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "fB; maindma+ vdisabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "fB; maindma+vokaydefaultC.i2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "fB; maindma+ vdisabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s0Bhdmi-phy@11d5f000mediatek,mt8195-hdmi-phy P  pll_ref26mpll1pll2 hdmi_txpll9D S vdisabledi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "fD; maindma+vokaydefaultE.i2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "fD; maindma+vokaydefaultF.i2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "fD; maindma+ vdisabledi2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 0"fD; maindma+ vdisabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c @"fD; maindma+vokaydefaultG.clock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wPDt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"*vokayusb-phy@0  refda_ref99usb-phy@700 refda_ref HIJintrrx_imptx_imp9:t-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+"vokayusb-phy@0  refda_ref95usb-phy@700 refda_ref KLMintrrx_imptx_imp96phy@11e80000mediatek,mt8195-pcie-physifNOPQRSTGglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1*9 vdisabled>ufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy unipromp9 vdisabled8gpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm@U0f :jobmmugpueV(* * * * *ycore0core1core2core3core4 vdisabledclock-controller@13fbf000mediatek,mt8195-mfgcfgUsyscon@14000000mediatek,mt8195-vppsys0sysconWdma-controller@14001000mediatek,mt8195-mdp3-rdmaW X*Y<W W WWWdisplay@14002000mediatek,mt8195-mdp3-fg W display@14003000mediatek,mt8195-mdp3-stitch0W0display@14004000mediatek,mt8195-mdp3-hdr@W@"display@14005000mediatek,mt8195-mdp3-aalPfFWP *display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz`W`% display@14007000mediatek,mt8195-mdp3-tdshppWp#display@14008000mediatek,mt8195-mdp3-colorfIW$*display@14009000mediatek,mt8195-mdp3-ovlfJW%*Ydisplay@1400a000mediatek,mt8195-mdp3-paddingW*display@1400b000mediatek,mt8195-mdp3-tccWdma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotW +Y*mutex@1400f000mediatek,mt8195-vpp-mutexfPW*smi@14010000mediatek,mt8195-smi-sub-commonapbsmigals0Z*[smi@14011000mediatek,mt8195-smi-sub-commonapbsmigals0Z*xsmi@14012000mediatek,mt8195-smi-common-vpp  apbsmigals0gals1*Zlarb@14013000mediatek,mt8195-smi-larb0[apbsmi*^iommu@14018000mediatek,mt8195-iommu-vpp8\]^_`abcdefghifRbclkt*Yclock-controller@14e00000mediatek,mt8195-wpesysclock-controller@14e02000mediatek,mt8195-wpesys_vpp0 clock-controller@14e03000mediatek,mt8195-wpesys_vpp10larb@14e04000mediatek,mt8195-smi-larb@japbsmi*larb@14e05000mediatek,mt8195-smi-larbPZ apbsmigals*`syscon@14f00000mediatek,mt8195-vppsys1sysconW mutex@14f01000mediatek,mt8195-vpp-mutexf{W '*larb@14f02000mediatek,mt8195-smi-larb j apbsmigals*larb@14f03000mediatek,mt8195-smi-larb0[ apbsmigals*_display@14f06000mediatek,mt8195-mdp3-split`W `+,*display@14f07000mediatek,mt8195-mdp3-tccpW pdma-controller@14f08000mediatek,mt8195-mdp3-rdmaW k*dma-controller@14f09000mediatek,mt8195-mdp3-rdmaW  k*dma-controller@14f0a000mediatek,mt8195-mdp3-rdmaW  Y*display@14f0b000mediatek,mt8195-mdp3-fgW  display@14f0c000mediatek,mt8195-mdp3-fgW  display@14f0d000mediatek,mt8195-mdp3-fgW  display@14f0e000mediatek,mt8195-mdp3-hdrW display@14f0f000mediatek,mt8195-mdp3-hdrW display@14f10000mediatek,mt8195-mdp3-hdrW  display@14f11000mediatek,mt8195-mdp3-aalfiW *display@14f12000mediatek,mt8195-mdp3-aal fjW *display@14f13000mediatek,mt8195-mdp3-aal0fkW 0!*display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz@W @display@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszPW P$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz`W `%display@14f17000mediatek,mt8195-mdp3-tdshppW pdisplay@14f18000mediatek,mt8195-mdp3-tdshpW (display@14f19000mediatek,mt8195-mdp3-tdshpW )display@14f1a000mediatek,mt8195-mdp3-mergeW *display@14f1b000mediatek,mt8195-mdp3-mergeW *display@14f1c000mediatek,mt8195-mdp3-colorftW *display@14f1d000mediatek,mt8195-mdp3-colorW fu*display@14f1e000mediatek,mt8195-mdp3-colorfvW *display@14f1f000mediatek,mt8195-mdp3-ovlfwW *kdisplay@14f20000mediatek,mt8195-mdp3-paddingW *display@14f21000mediatek,mt8195-mdp3-paddingW *display@14f22000mediatek,mt8195-mdp3-padding W *dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot0W 0k*dma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot@W @k*dma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotPW PY*clock-controller@15000000mediatek,mt8195-imgsys$larb@15001000mediatek,mt8195-smi-larb l$$$  apbsmigals*smi@15002000mediatek,mt8195-smi-sub-common $$apbsmigals0Z*osmi@15003000mediatek,mt8195-smi-sub-common0$$$ apbsmigals0j*lclock-controller@15110000 mediatek,mt8195-imgsys1_dip_topmlarb@15120000mediatek,mt8195-smi-larb l$mapbsmi*clock-controller@15130000mediatek,mt8195-imgsys1_dip_nrclock-controller@15220000mediatek,mt8195-imgsys1_wpe"nlarb@15230000mediatek,mt8195-smi-larb# l$napbsmi*clock-controller@15330000mediatek,mt8195-ipesys3%larb@15340000mediatek,mt8195-smi-larb4 o%%apbsmi*aclock-controller@16000000mediatek,mt8195-camsys&larb@16001000mediatek,mt8195-smi-larb p&&& apbsmigals*larb@16002000mediatek,mt8195-smi-larb q&&apbsmi*bsmi@16004000mediatek,mt8195-smi-sub-common@&&&apbsmigals0j*psmi@16005000mediatek,mt8195-smi-sub-commonP&&apbsmigals0Z*qlarb@16012000mediatek,mt8195-smi-larb qrrapbsmi* clarb@16013000mediatek,mt8195-smi-larb0pssapbsmi* larb@16014000mediatek,mt8195-smi-larb@qttapbsmi*!ilarb@16015000mediatek,mt8195-smi-larbPpuuapbsmi*!clock-controller@1604f000mediatek,mt8195-camsys_rawarclock-controller@1606f000mediatek,mt8195-camsys_yuvasclock-controller@1608f000mediatek,mt8195-camsys_rawbtclock-controller@160af000mediatek,mt8195-camsys_yuvb uclock-controller@16140000mediatek,mt8195-camsys_mrawvlarb@16141000mediatek,mt8195-smi-larbp&v& apbsmigals*"larb@16142000mediatek,mt8195-smi-larb qvvapbsmi*"hclock-controller@17200000mediatek,mt8195-ccusys wlarb@17201000mediatek,mt8195-smi-larb qwwapbsmi*dvideo-codec@18000000mediatek,mt8195-vcodec-decXk+ @"`video-codec@2000mediatek,mtk-vcodec-lat-soc YY AselvdeclattopMA]*video-codec@10000mediatek,mtk-vcodec-latf0kkkkkk AselvdeclattopMA]*video-codec@25000mediatek,mtk-vcodec-corePfPkkkkkkkkkk AselvdeclattopMA]*larb@1800d000mediatek,mt8195-smi-larbjapbsmi*larb@1800e000mediatek,mt8195-smi-larbxapbsmi*gclock-controller@1800f000mediatek,mt8195-vdecsys_soclarb@1802e000mediatek,mt8195-smi-larbjapbsmi*clock-controller@1802f000mediatek,mt8195-vdecsyslarb@1803e000mediatek,mt8195-smi-larbx apbsmi*fclock-controller@1803f000mediatek,mt8195-vdecsys_core1 clock-controller@190f3000mediatek,mt8195-apusys_pll0clock-controller@1a000000mediatek,mt8195-vencsys!larb@1a010000mediatek,mt8195-smi-larbj!!apbsmi*video-codec@1a020000mediatek,mt8195-vcodec-encHk`kakbkckdkvkwkxkyfUX! venc_selM@]*+jpeg-decoder@1a040000mediatek,mt8195-jpgdec*0kmknkrksktku+0"jpgdec@0,0mediatek,mt8195-jpgdec-hw0kmknkrksktkufW!jpgdec*jpgdec@0,10000mediatek,mt8195-jpgdec-hw0kmknkrksktkufX!jpgdec*jpgdec@1,0mediatek,mt8195-jpgdec-hw0YYYYYYf\"jpgdec*clock-controller@1b000000mediatek,mt8195-vencsys_core1"syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon yyjpeg-encoder@1a030000mediatek,mt8195-jpgenc* YYYY+0"jpgenc@0,0mediatek,mt8195-jpgenc-hw kgkhkiklfV!jpgenc*jpgenc@1,0mediatek,mt8195-jpgenc-hw YYYYf["jpgenc*larb@1b010000mediatek,mt8195-smi-larbZ""  apbsmigals*eovl@1c000000mediatek,mt8195-disp-ovlf|*kyports+port@0endpointport@1endpointz{rdma@1c002000mediatek,mt8195-disp-rdma f~*ky ports+port@0endpoint{zport@1endpoint|}color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color0f*y0ports+port@0endpoint}|port@1endpoint~ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr@f*y@ports+port@0endpoint~port@1endpointaal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aalPf*yPports+port@0endpointport@1endpointgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma`f*y`ports+port@0endpointport@1endpointdither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-ditherpf* ypports+port@0endpointport@1endpointdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsif**enginedigitalhsrdphy vdisableddsc@1c009000mediatek,mt8195-disp-dscf*ydsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi f*+enginedigitalhsrdphy vdisabledmerge@1c014000mediatek,mt8195-disp-merge@f*y@dp-intf@1c015000mediatek,mt8195-dp-intfPf*,pixelenginepll vdisabledmutex@1c016000mediatek,mt8195-disp-mutex`f*y`Ularb@1c018000mediatek,mt8195-smi-larbj((  apbsmigals*larb@1c019000mediatek,mt8195-smi-larbZ(  apbsmigals*\syscon@1c100000mediatek,mt8195-vdosys1syscon yyz#smi@1c01b000mediatek,mt8195-smi-common-vdo %&)$apbsmigals0gals1*jiommu@1c01f000mediatek,mt8195-iommu-vdo8ft'bclk*kmutex@1c101000mediatek,mt8195-disp-mutexf*#ylarb@1c102000mediatek,mt8195-smi-larb j### apbsmigals*larb@1c103000mediatek,mt8195-smi-larb0Z##  apbsmigals*]dma-controller@1c104000mediatek,mt8195-vdo1-rdma@f#*k@y@dma-controller@1c105000mediatek,mt8195-vdo1-rdmaPf#*Y`yPdma-controller@1c106000mediatek,mt8195-vdo1-rdma`f#*kAy`dma-controller@1c107000mediatek,mt8195-vdo1-rdmapf#*Yaypdma-controller@1c108000mediatek,mt8195-vdo1-rdmaf#*kBydma-controller@1c109000mediatek,mt8195-vdo1-rdmaf#*Ybydma-controller@1c10a000mediatek,mt8195-vdo1-rdmaf#*kCydma-controller@1c10b000mediatek,mt8195-vdo1-rdmaf#*Ycyvpp-merge@1c10c000mediatek,mt8195-disp-mergef# #mergemerge_async*y#vpp-merge@1c10d000mediatek,mt8195-disp-mergef# #mergemerge_async*y#vpp-merge@1c10e000mediatek,mt8195-disp-mergef# #mergemerge_async*y#vpp-merge@1c10f000mediatek,mt8195-disp-mergef# #mergemerge_async*y#vpp-merge@1c110000mediatek,mt8195-disp-mergef# #mergemerge_async*y(#dpi@1c112000mediatek,mt8195-dpi #-##2pixelenginepllf*# vdisabledports+port@0endpointport@1endpointdp-intf@1c113000mediatek,mt8195-dp-intf0f*#/#pixelenginepll vdisabledhdr-engine@1c114000mediatek,mt8195-disp-ethdrp@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dspy@yPypyyyyh#%# ###!#$#"#1#&#'#(#)#*mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top*YdYef(#3#4#5#6#7Evdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asynchdmi-tx@1c300000mediatek,mt8195-hdmi-tx?0 QLM,bushdcphdcp24mhdmi-splitML]f*rhdmi vdisabledi2cmediatek,mt8195-hdmi-ddcports+port@0endpointport@1endpointedp-tx@1c500000mediatek,mt8195-edp-txPdp_calibration_data*fP vdisableddp-tx@1c600000mediatek,mt8195-dp-tx`dp_calibration_data*fP vdisabledthermal-zonescpu0-thermalaotripstrip-alertLpassivetrip-crit criticalcooling-mapsmap00 cpu1-thermalaotripstrip-alertLpassivetrip-crit criticalcooling-mapsmap00 cpu2-thermalaotripstrip-alertLpassivetrip-crit criticalcooling-mapsmap00 cpu3-thermalaotripstrip-alertLpassivetrip-crit criticalcooling-mapsmap00 cpu4-thermalaotripstrip-alertLpassivetrip-crit criticalcooling-mapsmap00 cpu5-thermalaotripstrip-alertLpassivetrip-crit criticalcooling-mapsmap00 cpu6-thermalaotripstrip-alertLpassivetrip-crit criticalcooling-mapsmap00 cpu7-thermalaotripstrip-alertLpassivetrip-crit criticalcooling-mapsmap00 vpu0-thermalaotripstrip-alertLpassivetrip-crit criticalvpu1-thermalao tripstrip-alertLpassivetrip-crit criticalgpu-thermalao tripstrip-alertLpassivetrip-crit criticalgpu1-thermalao tripstrip-alertLpassivetrip-crit criticalvdec-thermalao tripstrip-alertLpassivetrip-crit criticalimg-thermalao tripstrip-alertLpassivetrip-crit criticalinfra-thermalaotripstrip-alertLpassivetrip-crit criticalcam0-thermalaotripstrip-alertLpassivetrip-crit criticalcam1-thermalaotripstrip-alertLpassivetrip-crit criticalchosenserial0:921600n8memory@40000000memory@ compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1gce0gce1hdmi0ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-updrive-strengthdrive-strength-microampbias-pull-down#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellspower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-namespinctrl-0#io-channel-cellsnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphyswakeup-sourcemediatek,syscon-wakeupfreq-table-hzmediatek,ufs-disable-mcqusb2-lpm-disablebus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapspi-max-frequencybits#phy-cellsmediatek,ibiasmediatek,ibias_upoperating-points-v2power-domain-namesmediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-en#sound-dai-cellsmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-path