.D8!( h!4grinn,genio-510-sbcmediatek,mt8370mediatek,mt8188 + 7embeddedDGrinn GenioSBC-510aliasesJ/soc/dp-intf@1c015000S/soc/dp-intf@1c113000\/soc/dpi@1c112000a/soc/dsc@1c009000f/soc/ethdr@1c114000m/soc/mailbox@10320000r/soc/mailbox@10330000w/soc/merge0@1c014000~/soc/merge@1c10c000/soc/merge@1c10d000/soc/merge@1c10e000/soc/merge@1c10f000/soc/merge@1c110000/soc/mutex@1c016000/soc/mutex@1c101000/soc/padding@1c11d000/soc/padding@1c11e000/soc/padding@1c11f000/soc/padding@1c120000/soc/padding@1c121000/soc/padding@1c122000/soc/padding@1c123000/soc/padding@1c124000/soc/rdma@1c104000/soc/rdma@1c105000 /soc/rdma@1c106000/soc/rdma@1c107000#/soc/rdma@1c108000./soc/rdma@1c1090009/soc/rdma@1c10a000D/soc/rdma@1c10b000O/soc/i2c@11e00000T/soc/mmc@11230000Y/soc/ethernet@11021000c/soc/i2c@11280000h/soc/i2c@11281000m/soc/i2c@11282000r/soc/i2c@11ec0000w/soc/i2c@11ec1000|/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55psciw5@@ ->Ra cpu@100cpuarm,cortex-a55psciw5@@ ->Ra cpu@200cpuarm,cortex-a55psciw5@@ ->Ra cpu@300cpuarm,cortex-a55psciw5@@ ->Ra cpu@600cpuarm,cortex-a78psci!V@@ ->Ra cpu@700cpuarm,cortex-a78psci!V@@ ->Racpu-mapcluster0core0i core1i core2i core3i core6i core7iidle-statesmpscicpu-off-larm,idle-statez2_Dacpu-off-barm,idle-statez-acluster-off-larm,idle-statez7Hacluster-off-barm,idle-statez2al2-cache0cache@-al2-cache1cache@-al3-cachecache @aoscillator-13m fixed-clock]@clk13ma5oscillator-26m fixed-clockclk26ma7oscillator-32k fixed-clockclk32kopp-table-gpuoperating-points-v2agopp-390000000> .opp-431000000 .opp-4730000001h@ '.opp-515000000F X.opp-556000000!# h.opp-598000000# <.opp-640000000&% .opp-670000000'c .opp-700000000)' L.opp-730000000+ }.opp-760000000-L `.opp-790000000/q 4.opp-8350000001 (r.opp-8800000004s q.opp-9150000006 X.opp-915000000-56 .0opp-915000000-66 q.popp-9500000008ـ 5.opp-950000000-58ـ X.0opp-950000000-68ـ q.ppmu-a55arm,cortex-a55-pmu ?pmu-a78arm,cortex-a78-pmu ?psci arm,psci-1.0smcsoundJ\okay6mediatek,mt8390-mt6359-evkmediatek,mt8188-mt6359-evb Dmt8390-evkcdefaultqt{HeadphoneHeadphone LHeadphoneHeadphone RAP DMICAUDGLBAP DMICMIC_BIAS_0AP DMICMIC_BIAS_2DMIC_INPUTAP DMICthermal-zonescpu-little0-thermaltripstrip-alert0L?passiveatrip-alert1s?hottrip-crit ?criticalcooling-mapsmap00 cpu-little1-thermaltripstrip-alert0L?passiveatrip-alert1s?hottrip-crit ?criticalcooling-mapsmap00 cpu-little2-thermaltripstrip-alert0L?passiveatrip-alert1s?hottrip-crit ?criticalcooling-mapsmap00 cpu-little3-thermaltripstrip-alert0L?passiveatrip-alert1s?hottrip-crit ?criticalcooling-mapsmap00 cpu-big0-thermaldtripstrip-alert0L?passiveatrip-alert1s?hottrip-crit ?criticalcooling-mapsmap0 cpu-big1-thermaldtripstrip-alert0L?passiveatrip-alert1s?hottrip-crit ?criticalcooling-mapsmap0 apu-thermaltripstrip-alert0L?passivetrip-alert1s?hottrip-crit ?criticalgpu-thermaltripstrip-alert0L?passiveatrip-alert1s?hottrip-crit ?criticalcooling-mapsmap0 gpu1-thermaltripstrip-alert0L?passiveatrip-alert1s?hottrip-crit ?criticalcooling-mapsmap0 adsp-thermaltripstrip-alert0L?passivetrip-alert1s?hottrip-crit ?criticalvdo-thermaltripstrip-alert0L?passivetrip-alert1s?hottrip-crit ?criticalinfra-thermaltripstrip-alert0L?passivetrip-alert1s?hottrip-crit ?criticalcam1-thermaltripstrip-alert0L?passivetrip-alert1s?hottrip-crit ?criticalcam2-thermaltripstrip-alert0L?passivetrip-alert1s?hottrip-crit ?criticaltimerarm,armv8-timer @?   ]@soc+ simple-busperformance-controller@11bc10mediatek,cpufreq-hw  0 ainterrupt-controller@c000000 arm,gic-v3, C    ? appi-partitionsinterrupt-partition-0X ainterrupt-partition-1X asyscon@10000000 mediatek,mt8188-topckgensyscona#syscon@10001000#mediatek,mt8188-infracfg-aosysconaa$syscon@10003000mediatek,mt8188-pericfgsyscon0aFpinctrl@10005000mediatek,mt8188-pinctrl`P0niocfg0iocfg_rmiocfg_ltiocfg_lmiocfg_rteintx C?RPI_GPIO0RPI_GPIO1RPI_GPIO4RPI_GPIO6RPI_GPIO9RPI_GPIO10RPI_GPIO11RPI_GPIO21RPI_GPIO23RPI_GPIO30RPI_GPIO35RPI_GPIO36RPI_GPIO55RPI_GPIO56RPI_GPIO59RPI_GPIO60RPI_GPIO69RPI_GPIO72RPI_GPIO73RPI_GPIO74RPI_GPIO79RPI_GPIO80RPI_GPIO81RPI_GPIO82RPI_GPIO121RPI_GPIO122RPI_GPIO123RPI_GPIO124a i2c1-pinsaapins:9mmc0-default-pinsaQpins-clkfpins-cmd-dat$epins-rstemmc0-uhs-pinsaRpins-clkfpins-cmd-dat$epins-dsfpins-rstei2c0-pinsaVpins87i2c2-pinsaWpins<;i2c3-pinsaXpins>=i2c5-pinsacpinsBAi2c6-pinsadpinsDCuart0-pinsa?pins uart1-pinsa@pinsVWuart2-pinsaApins#$pcie-defaulta_mux /01eth-default-pinsaOpins-ccpins-mdiopins-powerpins-rxdpins-txdeth-sleep-pinsaPpins-ccpins-mdio!pins-rxdpins-txdspi2-pinsaCpins-spiOPQR!audio-default-pinsapins-cmd-datyz{|usb-default-pinsa[pins-validUsyscon@10006000)mediatek,mt8188-scpsyssysconsimple-mfd`power-controller!mediatek,mt8188-power-controller+.a8power-domain@0+.B!power-domain@1P"#Wmfgaltc$+.B%power-domain@2.power-domain@3.power-domain@4.power-domain@15P#### #3#4#=##& & &&&&&&&&&&&&&&&&& Wtopcamccuimgvencvdecwpecfgckcfgxoss-sram-cmnss-sram-v0l0ss-sram-v0l1ss-sram-ve0ss-sram-ve1ss-sram-ifass-sram-camss-sram-v1l5ss-sram-v1l6ss-sram-rdrss-iommuss-imgcamss-emiss-subcmn-rdrss-rsiss-cmn-l4ss-vdec1ss-wpess-cvdo-ve1c$+.power-domain@16HP##'''''''AWcfgckcfgxoss-galsss-cmnss-emiss-iommuss-larbss-rsiss-busc$+.power-domain@200P##((((8Wcfgckcfgxoss-vpp1-g5ss-vpp1-g6ss-vpp1-l5ss-vpp1-l6c$.power-domain@22P)Wss-vdec1-soc-l1c$+.power-domain@23P* Wss-vdec2-l1c$.power-domain@29 P### #Wcamccubuscfgckc$+.power-domain@30(P+++++6Wss-cam-l13ss-cam-l14ss-cam-mm0ss-cam-mm1ss-camsysc$+.power-domain@32 P+,-$Wss-camb-subss-camb-rawss-camb-yuv.power-domain@31P+./$Wss-cama-subss-cama-rawss-cama-yuv.power-domain@17(P##000&Wcfgckcfgxoss-larb2ss-larb3ss-galsc$+.power-domain@9 P#@#? Wbushdcpc$.power-domain@18c$.power-domain@19c$.power-domain@24 P11110Wss-ve1-larbss-ve1-coress-ve1-galsss-ve1-sramc$.power-domain@21P22Wss-wpe-l7ss-wpe-l7pcec$.power-domain@5c$P3 Wss-pextp-fmem.power-domain@7P#0#1Wseninf0seninf1.power-domain@6.power-domain@10 P#E#D Wbusmainc$+.power-domain@11 c$+.power-domain@14P#FWasmc$.power-domain@13 P#S#4Wa1sysintbusadspckc$.power-domain@12 c$.power-domain@8P3  Wethermacc$.watchdog@10007000mediatek,mt8188-wdtpuaa9syscon@1000c000"mediatek,mt8188-apmixedsyssyscona"timer@10017000,mediatek,mt8188-timermediatek,mt6765-timerp? P5pwrap@100240003mediatek,mt8188-pwrapmediatek,mt8195-pwrapsyscon@npwrap?P$$ Wspiwrappmicmediatek,mt6359C ?  adcmediatek,mt6359-auxadcaudio-codecmediatek,mt6359-codecregulatorsmediatek,mt6359-regulatorbuck_vs1vs1 5!buck_vgpu11 dvdd_core73 Hbuck_vmodemvmodem3*buck_vpu dvdd_adsp73 Hbuck_vcore dvdd_proc_l 3 Hbuck_vs2vs2 5jbuck_vpavpa_pmu /M`,buck_vproc2vgpudp 53L H`%wja!buck_vproc1vproc173L Hbuck_vcore_sshub vcore_sshub7buck_vgpu11_sshub vgpu11_sshub7ldo_vaud18vaud18w@w@ldo_vsim1 vsim1_pmu/M`ldo_vibrvibrO2Zldo_vrf12va12_abb2_pmu ldo_vusbvusb--aGldo_vsram_proc2 vsram_proc2 3Lldo_vio18vio18ldo_vcamiovcamioldo_vcn18 vcn18_pmuw@w@ldo_vfe28vfe28**xldo_vcn13vcn13  ldo_vcn33_1_bt vcn33_1_bt*5gldo_vcn33_1_wifi vcn33_1_wifi*5gldo_vaux18vaux18w@w@ldo_vsram_others vsram_gpu q 53`!wja%ldo_vefusevefuseldo_vxo22vxo22w@!ldo_vrfckvrfck`ldo_vrfck_1vrfckjldo_vbif28vbif28**ldo_vio28vio28*2Zldo_vemcvemc,@ 2Zldo_vemc_1vemc&%2ZaSldo_vcn33_2_bt vcn33_2_pmu*5gldo_vcn33_2_wifi vcn33_2_wifi*5gldo_va12va12O ldo_va09va09 5Oldo_vrf18vrf18Pldo_vsram_md vsram_md 3*ldo_vufs vufs18_pmuaTldo_vm18vm18ldo_vbbckvbbckOldo_vsram_proc1 vsram_proc1 3Lldo_vsim2vsim2/M`ldo_vsram_others_sshubvsram_others_sshub rtcmediatek,mt6358-rtckeysmediatek,mt6359-keyspower-keytspmi@10027000*mediatek,mt8188-spmimediatek,mt8195-spmi p npmifspmimst#8#P$$#8(Wpmif_sys_ckpmif_tmr_ckspmimst_clk_muxiommu@10315000mediatek,mt8188-iommu-infra1P?a]mailbox@10320000mediatek,mt8188-gce2@?P$ahmailbox@10330000mediatek,mt8188-gce3@?P$ajscp@10720000mediatek,mt8188-scp-dualrncfg+P\okayscp@0mediatek,scp-core nsram?\okay6akscp@d0000mediatek,scp-core nsram? \disabledaudio-controller@10b10000mediatek,mt8188-afe#S#P7" " ######S## #E#Q#M#N#O#P4####T#RWclk26mapll1apll2apll12_div0apll12_div1apll12_div2apll12_div3apll12_div9top_a1sys_hptop_aud_intbustop_audio_htop_audio_local_bustop_dptxtop_i2so1top_i2so2top_i2si1top_i2si2adsp_audio_26mapll1_d4apll2_d4apll12_div4top_a2systop_aud_iec?6+8 99 @audiosysc$L#\okay:aadsp@10b80000mediatek,mt8188-dsp@ ncfgsramsecbus#DP#D#EWaudiodspadsp_bus^;<erxtx+8 \okay=>amailbox@10b861004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxa?a;mailbox@10b871004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxq?a<clock-controller@10b91100mediatek,mt8188-adsp-audio26ma4serial@11001100*mediatek,mt8188-uartmediatek,mt6577-uart? P7$ Wbaudbus\okaycdefaultq?serial@11001200*mediatek,mt8188-uartmediatek,mt6577-uart? P7$ Wbaudbus\okaycdefaultq@serial@11001300*mediatek,mt8188-uartmediatek,mt6577-uart? P7$ Wbaudbus\okaycdefaultqAserial@11001400*mediatek,mt8188-uartmediatek,mt6577-uart? P7$ Wbaudbus \disabledadc@11002000.mediatek,mt8188-auxadcmediatek,mt8173-auxadc P$Wmain \disabledsyscon@11003000"mediatek,mt8188-pericfg-aosyscon0a3spi@1100a000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+?P#y#$Wparent-clksel-clkspi-clk \disabledthermal-sensor@1100b000mediatek,mt8188-lvts-ap ?P$9$pB|lvts-calib-data-1apwm@1100e0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwmP#'$/Wmainmm? \disabledpwm@1100f0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwmP#($FWmainmm? \disabledspi@11010000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+?P#y#$2Wparent-clksel-clkspi-clk \disabledspi@11012000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+ ?P#y#$3Wparent-clksel-clkspi-clk\okaycdefaultqCspi@11013000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+0?P#y#$4Wparent-clksel-clkspi-clk \disabledspi@11018000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+?P#y#$8Wparent-clksel-clkspi-clk \disabledspi@11019000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+?P#y#$9Wparent-clksel-clkspi-clk \disabledusb@11201000#mediatek,mt8188-mtu3mediatek,mtu3  - > nmacippc ?+?#)#vP3 #3 Wsys_ckref_ckmcu_ckDE Fh\okayhost super-speedGusb@0'mediatek,mt8188-xhcimediatek,mtk-xhcinmac?#*#vP3 Wsys_ck\okay+Ghub@1 usb451,8027H  IaJhub@2 usb451,8025J  IaHethernet@11021000;mediatek,mt8188-gmacmediatek,mt8195-gmacsnps,dwmac-5.10a@?"macirq0P33#A#B#C3 .Waxiapbmac_mainptp_refrmii_internalmac_cg#A#B#C###+82$CKSLfMy\okay rgmii-idNcdefaultsleepqOP * @ mdiosnps,dwmac-mdio+ethernet-phy@3ethernet-phy-ieee802.3-c22   aNstmmac-axi-config , 6 FaKrx-queues-config V laLqueue0 } queue1 } queue2 } queue3 } tx-queues-config  aMqueue0 }  queue1 }  queue2 }  queue3 }  mmc@11230000(mediatek,mt8188-mmcmediatek,mt8183-mmc # P#$$$M!Wsourcehclksource_cgcrypto_clk\okaycdefaultstate_uhsqQR     # 2 ? P X ^H mS yT mmc@11240000(mediatek,mt8188-mmcmediatek,mt8183-mmc $P#$$$Wsourcehclksource_cg## \disabledmmc@11250000(mediatek,mt8188-mmcmediatek,mt8183-mmc %P#$$AWsourcehclksource_cg## \disabledthermal-sensor@11278000mediatek,mt8188-lvts-mcu'?P$9$pB|lvts-calib-data-1ai2c@11280000mediatek,mt8188-i2c ("? PU$7 Wmaindma+\okaycdefaultqVi2c@11281000mediatek,mt8188-i2c ("? PU$7 Wmaindma+\okaycdefaultqWi2c@11282000mediatek,mt8188-i2c ( "? PU$7 Wmaindma+\okaycdefaultqXclock-controller@11283000mediatek,mt8188-imp-iic-wrap-c(0aUusb@112a1000#mediatek,mt8188-mtu3mediatek,mtu3 *-*> nmacippc*?+?#-#vP3#3Wsys_ckref_ckmcu_ckY Fp\okayhost high-speedGusb@0'mediatek,mt8188-xhcimediatek,mtk-xhcinmac?#.#vP3Wsys_ck\okay+Ghub@1microchip,usb2513biIusb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 +-+> nmacippc+?+?#,#vP3#3Wsys_ckref_ckmcu_ckZ F`\okay peripheralcdefaultq[Gusb@0'mediatek,mt8188-xhcimediatek,mtk-xhcinmac?#+#vP3Wsys_ck \disabledpcie@112f0000*mediatek,mt8188-pciemediatek,mt8192-pcie/  npcie-mac  pci +0P$L$#$&$+$C3 /Wpl_250mtl_26mtl_96mtl_32kperi_26mperi_mem?` \\\\  ] ^ pcie-phy+899@mac\okaycdefaultq_interrupt-controllerCa\spi@1132c000(mediatek,mt8188-normediatek,mt8186-nor2P#X33 Wspisfaxi#X?9+ \disabledt-phy@11c20700.mediatek,mt8188-tphymediatek,generic-tphy-v3++8\okaypcie-phy@0P#Wref a^hdmi-phy@11d5f0002mediatek,mt8188-hdmi-phymediatek,mt8195-hdmi-phyP$Wpll_ref hdmi_txpll     \disabledadsi-phy@11c800000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-txP7 mipi_tx0_pll  \disabledadsi-phy@11c900000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-txP7 mipi_tx0_pll  \disabledai2c@11e00000mediatek,mt8188-i2c "? P`$7 Wmaindma+\okaycdefaultqai2c@11e01000mediatek,mt8188-i2c "? P`$7 Wmaindma+ \disabledclock-controller@11e02000mediatek,mt8188-imp-iic-wrap-w a`t-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+\okayusb-phy@0P#" Wrefda_ref aZt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+\okayusb-phy@0P#" Wrefda_ref aDusb-phy@700 P"7 Wrefda_ref aEt-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+\okayusb-phy@0P#" Wrefda_ref aYi2c@11ec0000mediatek,mt8188-i2c "? Pb$7 Wmaindma+\okaycdefaultqci2c@11ec1000mediatek,mt8188-i2c "? Pb$7 Wmaindma+\okaycdefaultqdclock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-en abefuse@11f20000,mediatek,mt8188-efusemediatek,mt8186-efuse+dp-calib@1a0 alvts1-calib@1ac@aBgpu-speedbin@581 )afsocinfo-data1@7a0socinfo-data2@7e0gpu@13000000)mediatek,mt8370-maliarm,mali-valhall-jm@Pe0?~} "jobmmugpupf |speed-bin .g+88 Bcore0core1R\okay U!aclock-controller@13fbf000mediatek,mt8188-mfgcfgaesyscon@14000000mediatek,mt8188-vppsys0syscona&dma-controller@14001000mediatek,mt8188-mdp3-rdma aP&<^h hhhh li+8 sj   kdisplay@140020000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg P& sj display@140040002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr@P&" sj@display@140050002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aalP?FP& +8 sjPdisplay@140060002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz`P&  sj` %display@140070006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshppP&# sjpdisplay@140080006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color?IP&$+8 sjdisplay@140090002mediatek,mt8188-mdp3-ovlmediatek,mt8195-mdp3-ovl?JP&%+8 sj lidisplay@1400a000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-paddingP&+8 sjdisplay@1400b0002mediatek,mt8188-mdp3-tccmediatek,mt8195-mdp3-tccP& sjdisplay@1400c0004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot aP& li+8 sj  +mutex@1400f000mediatek,mt8188-vpp-mutex?PP&+8 sjsmi@14012000mediatek,mt8188-smi-common-vpp P&&Wapbsmi+8alsmi@14013000mediatek,mt8188-smi-larb0P&&Wapbsmi+8  laoiommu@14018000mediatek,mt8188-iommu-vppPP&Wbclk?R+8 mnopqraidma-controller@14f09000mediatek,mt8188-mdp3-rdma aP(  ls+8 sj  dma-controller@14f0a000mediatek,mt8188-mdp3-rdma aP(  li+8 sj  display@14f0c0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fgP(  sj display@14f0d0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fgP(  sj display@14f0f0002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdrP(" sj display@14f100002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdrP($ sj display@14f120002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal ?jP(#+8 sj display@14f130002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal0?kP(%+8 sj 0display@14f150002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rszPP( sj P display@14f160002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz`P( sj ` display@14f180006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshpP( sj display@14f190006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshpP( sj display@14f1a0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-mergeP(+8 sj display@14f1b0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-mergeP(+8 sj display@14f1d0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color?uP(+8 sj display@14f1e0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color?vP(+8 sj display@14f21000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-paddingP(+8 sj display@14f22000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding P(+8 sj display@14f240004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot@ aP( ls+8 sj @ display@14f250004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrotP aP( li+8 sj P clock-controller@14e00000mediatek,mt8188-wpesysa2clock-controller@14e02000mediatek,mt8188-wpesys-vpp0 smi@14e04000mediatek,mt8188-smi-larb@P22Wapbsmi+8  laqsyscon@14f00000mediatek,mt8188-vppsys1syscona(mutex@14f01000mediatek,mt8188-vpp-mutex?{P(&+8 sj smi@14f02000mediatek,mt8188-smi-larb P((Wapbsmi+8  tasmi@14f03000mediatek,mt8188-smi-larb0P((Wapbsmi+8  lapclock-controller@15000000mediatek,mt8188-imgsysclock-controller@15110000 mediatek,mt8188-imgsys1-dip-topaclock-controller@15130000mediatek,mt8188-imgsys1-dip-nraclock-controller@15220000mediatek,mt8188-imgsys-wpe1"aclock-controller@15330000mediatek,mt8188-ipesys3aclock-controller@15520000mediatek,mt8188-imgsys-wpe2Raclock-controller@15620000mediatek,mt8188-imgsys-wpe3baclock-controller@16000000mediatek,mt8188-camsysa+clock-controller@1604f000mediatek,mt8188-camsys-rawaaa.clock-controller@1606f000mediatek,mt8188-camsys-yuvaaa/clock-controller@1608f000mediatek,mt8188-camsys-rawbaa,clock-controller@160af000mediatek,mt8188-camsys-yuvb aa-clock-controller@17200000mediatek,mt8188-ccusys video-decoder@18000000mediatek,mt8188-vcodec-dec @` li+ kvideo-codec@10000mediatek,mtk-vcodec-lat#4#x P#4))#xWselvdeclattop?H liiiiiiiii+8video-codec@25000mediatek,mtk-vcodec-coreP#4#x P#4**#xWselvdeclattop?X lsssssssssss+8smi@1800d000mediatek,mt8188-smi-larbP))Wapbsmi+8  larclock-controller@1800f000mediatek,mt8188-vdecsys-soca)smi@1802e000mediatek,mt8188-smi-larbP**Wapbsmi+8  taclock-controller@1802f000mediatek,mt8188-vdecsysa*clock-controller@1a000000mediatek,mt8188-vencsysa1smi@1a010000mediatek,mt8188-smi-larbP11Wapbsmi+8  tavideo-encoder@1a020000mediatek,mt8188-vcodec-enc+#3#pP1 Wvenc_sel?aX lsssssssssss+8 kjpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgencP1Wjpgenc?b lssss+8jpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdecP11Wjpgdec-smijpgdec?c0 lssssss+8ovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovlP'?| ls+8 shports+port@0endpointport@1endpoint uavrdma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdma P'?~ li +8 sh ports+port@0endpoint vauport@1endpoint waxcolor@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-color0P'?+8 sh0ports+port@0endpoint xawport@1endpoint yazccorr@1c0040006mediatek,mt8188-disp-ccorrmediatek,mt8192-disp-ccorr@P'?+8 sh@ports+port@0endpoint zayport@1endpoint {a|aal@1c0050002mediatek,mt8188-disp-aalmediatek,mt8183-disp-aalPP' ?+8 shPports+port@0endpoint |a{port@1endpoint }a~gamma@1c0060006mediatek,mt8188-disp-gammamediatek,mt8195-disp-gamma`P'?+8 sh`ports+port@0endpoint ~a}port@1endpointdither@1c0070008mediatek,mt8188-disp-dithermediatek,mt8183-disp-ditherpP'?+8 shpports+port@0endpointport@1endpointdsi@1c008000mediatek,mt8188-dsiP''Wenginedigitalhs? dphy+89' \disableddsc@1c0090002mediatek,mt8188-disp-dscmediatek,mt8195-disp-dscP' ?+8 shdsi@1c012000mediatek,mt8188-dsi P' 'Wenginedigitalhs? dphy+89'  \disabledmerge0@1c0140006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge@P' 0Wmergemerge_async?+8 sh@dp-intf@1c015000mediatek,mt8188-dp-intfPP' ' "Wpixelenginepll?+8 \disabledmutex@1c016000mediatek,mt8188-disp-mutex`P'?+8 sh` >postmask@1c01a000<mediatek,mt8188-disp-postmaskmediatek,mt8192-disp-postmaskP'?+8 shports+port@0endpointport@1endpointsyscon@1c01d000mediatek,mt8188-vdosys0syscona ^h sha'smi@1c022000mediatek,mt8188-smi-larb P''Wapbsmi+8  tasmi@1c023000mediatek,mt8188-smi-larb0P''Wapbsmi+8  lamsmi@1c024000mediatek,mt8188-smi-common-vdo@P''Wapbsmi+8atiommu@1c028000mediatek,mt8188-iommu-vdoPP'Wbclk?+8 assyscon@1c100000mediatek,mt8188-vdosys1syscona ^h sha0mutex@1c101000mediatek,mt8188-disp-mutexP0?+8 sh smi@1c102000mediatek,mt8188-smi-larb P00Wapbsmi+8  tasmi@1c103000mediatek,mt8188-smi-larb0P00Wapbsmi+8  lanrdma@1c1040004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma@P0? ls@+8 a sh@rdma@1c1050004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaPP0? li`+8 a shPrdma@1c1060004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma`P0? lsA+8 a sh`rdma@1c1070004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmapP0? lia+8 a shprdma@1c1080004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaP0? lsB+8 a shrdma@1c1090004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaP0? lib+8 a shrdma@1c10a0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaP0? lsC+8 a shrdma@1c10b0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaP0? lic+8 a shmerge@1c10c0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergeP0 0Wmergemerge_async?+890 sh merge@1c10d0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergeP0 0Wmergemerge_async?+890 sh merge@1c10e0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergeP0 0Wmergemerge_async?+890 sh merge@1c10f0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergeP0 0Wmergemerge_async?+890 sh merge@1c1100006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergeP0 0Wmergemerge_async?+890 sh dpi@1c112000(mediatek,mt8188-dpimediatek,mt8195-dpi P0800=Wpixelenginepll? +890 \disabledports+port@0endpointport@1endpointdp-intf@1c113000mediatek,mt8188-dp-intf0P0:0"Wpixelenginepll?+8 \disabledethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrp@Pp4nmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dshP000+0.0,0/0-0<0102030405#Wmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top?6 lidie+8(90102030405p sh@hPhphhhhpadding@1c11d000mediatek,mt8188-disp-paddingP0+8 shpadding@1c11e000mediatek,mt8188-disp-paddingP0 +8 shpadding@1c11f000mediatek,mt8188-disp-paddingP0!+8 shpadding@1c120000mediatek,mt8188-disp-paddingP0"+8 shpadding@1c121000mediatek,mt8188-disp-paddingP0#+8 shpadding@1c122000mediatek,mt8188-disp-padding P0$+8 sh padding@1c123000mediatek,mt8188-disp-padding0P0%+8 sh0padding@1c124000mediatek,mt8188-disp-padding@P0&+8 sh@hdmi@1c300000mediatek,mt8188-hdmi-tx0 P#@#>#?(.Wbushdcphdcp24mhdmi-split#>#s?+8  hdmi \disabledi2c2mediatek,mt8188-hdmi-ddcmediatek,mt8195-hdmi-ddcP7ports+port@0endpointport@1endpointedp-tx@1c500000mediatek,mt8188-edp-txP?p|dp_calibration_data+8  \disableddp-tx@1c600000mediatek,mt8188-dp-tx`?p|dp_calibration_data+8  \disabledchosen %serial0:921600n8firmwareopteelinaro,optee-tzsmcreserved-memory+optee@43200000 1C memory@50000000shared-dma-poolP 1a6memory@54600000 1T` memory@55000000shared-dma-poolU@memory@57000000shared-dma-poolW@memory@60000000shared-dma-pool` 1a>memory@60f00000shared-dma-pool` 1a:memory@61000000shared-dma-poola 1a=regulator-vsysregulator-fixedvsys 8aregulator-0regulator-fixed fixed-5v0LK@LK@ J ]regulator-1regulator-fixed fixed-4v2@@@@ J ]regulator-2regulator-fixed fixed-3v32Z2Z J ]aImemory@40000000memory@ compatibleinterrupt-parent#address-cells#size-cellschassis-typemodeldp-intf0dp-intf1dpi1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7i2c1mmc0ethernet0i2c0i2c2i2c3i2c5i2c6serial0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspinctrl-namespinctrl-0audio-routingmediatek,adsppolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxbias-pull-updrive-strength-microampdrive-strengthbias-pull-downinput-enableoutput-highinput-disablebias-disable#power-domain-cellsdomain-supplyclocksclock-namesmediatek,infracfgmediatek,disable-extrst#sound-dai-cellsinterrupts-extended#io-channel-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadmediatek,long-press-modepower-off-time-seclinux,keycodeswakeup-sourceassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellsmemory-regionpower-domainsresetsreset-namesmediatek,topckgenmboxesmbox-namesnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsmediatek,pad-selectphysmediatek,syscon-wakeupdr_modemaximum-speedvusb33-supplypeer-hubreset-gpiosvdd-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlepinctrl-1mediatek,mac-wolmediatek,tx-delay-pssnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpioeee-broken-1000tsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqecap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removableclock-divbus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-names#phy-cellsmediatek,ibiasmediatek,ibias_upbitsoperating-points-v2power-domain-namesmali-supply#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzstdout-pathno-mapregulator-boot-onenable-active-highvin-supply