PS8B (GA=ezurio,mt8370-tungsten-smarcmediatek,mt8370mediatek,mt8188 +"7Ezurio Tungsten510 SMARC (MT8370)aliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/dsc@1c009000Y/soc/ethdr@1c114000`/soc/mailbox@10320000e/soc/mailbox@10330000j/soc/merge0@1c014000q/soc/merge@1c10c000x/soc/merge@1c10d000/soc/merge@1c10e000/soc/merge@1c10f000/soc/merge@1c110000/soc/mutex@1c016000/soc/mutex@1c101000/soc/padding@1c11d000/soc/padding@1c11e000/soc/padding@1c11f000/soc/padding@1c120000/soc/padding@1c121000/soc/padding@1c122000/soc/padding@1c123000/soc/padding@1c124000/soc/rdma@1c104000/soc/rdma@1c105000/soc/rdma@1c106000 /soc/rdma@1c107000/soc/rdma@1c108000!/soc/rdma@1c109000,/soc/rdma@1c10a0007/soc/rdma@1c10b000B/soc/dsi@1c008000G/soc/ethernet@11021000Q/soc/i2c@11280000V/soc/i2c@11e00000[/soc/i2c@11281000`/soc/i2c@11282000e/soc/i2c@11e01000j/soc/i2c@11ec0000o/soc/i2c@11ec1000t/soc/mmc@11230000y/soc/mmc@11240000~/soc/mmc@11250000*/soc/i2c@11280000/i2c-mux@73/i2c@0/rtc@52/soc/pwrap@10024000/pmic/rtc/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55psciw5@@1>Ocr} cpu@100cpuarm,cortex-a55psciw5@@1>Ocr} cpu@200cpuarm,cortex-a55psciw5@@1>Ocr} cpu@300cpuarm,cortex-a55psciw5@@1>Ocr}cpu@600cpuarm,cortex-a78psci!V@@1> Ocr }cpu@700cpuarm,cortex-a78psci!V@@1> Ocr }cpu-mapcluster0core0 core1 core2 core3core6core7idle-statespscicpu-off-larm,idle-state2_D}cpu-off-barm,idle-state-}cluster-off-larm,idle-state7H}cluster-off-barm,idle-state2}l2-cache0cache@>}l2-cache1cache@>} l3-cachecache @}oscillator-13m fixed-clock ]@clk13m}6oscillator-26m fixed-clock clk26m}8oscillator-32k fixed-clock clk32kopp-table-gpuoperating-points-v2*}opp-3900000005><Jopp-4310000005<Jopp-47300000051h@< 'Jopp-5150000005F< XJopp-5560000005!#< hJopp-5980000005#< <Jopp-6400000005&%< Jopp-6700000005'c< Jopp-7000000005)'< LJopp-7300000005+< }Jopp-7600000005-L< `Jopp-7900000005/q< 4Jopp-83500000051< (rJopp-88000000054s< qJopp-91500000056< XJopp-915000000-556< J0opp-915000000-656< qJpopp-95000000058ـ< 5Jopp-950000000-558ـ< XJ0opp-950000000-658ـ< qJppmu-a55arm,cortex-a55-pmu [pmu-a78arm,cortex-a78-pmu [psci arm,psci-1.0smcsoundf xdisabledthermal-zonescpu-little0-thermaltripstrip-alert0Lpassive}trip-alert1shottrip-crit criticalcooling-mapsmap00 cpu-little1-thermaltripstrip-alert0Lpassive}trip-alert1shottrip-crit criticalcooling-mapsmap00 cpu-little2-thermaltripstrip-alert0Lpassive}trip-alert1shottrip-crit criticalcooling-mapsmap00 cpu-little3-thermaltripstrip-alert0Lpassive}trip-alert1shottrip-crit criticalcooling-mapsmap00 cpu-big0-thermaldtripstrip-alert0Lpassive}trip-alert1shottrip-crit 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}#syscon@10001000#mediatek,mt8188-infracfg-aosyscon I}$syscon@10003000mediatek,mt8188-pericfgsyscon0 }Ipinctrl@10005000mediatek,mt8188-pinctrl`P0Viocfg0iocfg_rmiocfg_ltiocfg_lmiocfg_rteint`p| +[} audio-pinspins-aud-pmicefghijpins-pcm-wifiyz{|pins-i2swpxqndisp-pwm0-pins}Epinsdsi0-sn65dsi84-pins}mpins-irqpins-enableeth-default-pins}Qpins-txdpins-cc pins-rxdfpins-mdiopins-powerpins-intrfeth-sleep-pins}Rpins-txdpins-ccpins-rxdpins-mdiogpio-keys-pinspins-keys ABhd3ss3320-pins}epins-irq-ehdmi-vreg-pinspins-pwr2hdmi-pinspins-hotplug3pins-cec4pins-ddc56 i2c0-pins}bpins-bus87i2c0-mux-pins}cpins-reseti2c1-pins}pins-bus:9i2c2-pins}kpins-bus<;i2c3-pins}qpins-bus>=i2c4-pins}pins-bus@?i2c-mux-smarc-lcd-pins}lpins-resetmmc0-default-pins}Spins-cmd-dat$epins-clkfpins-rstemmc0-uhs-pins}Tpins-cmd-dat$epins-clkfpins-dsfpins-rstemmc1-default-pins}Wpins-cmd-datepins-pwropins-pullup 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:baudbusxokay~@pdefaultserial@11001200*mediatek,mt8188-uartmediatek,mt6577-uart[ 38$ :baudbusxokay~Apdefaultserial@11001300*mediatek,mt8188-uartmediatek,mt6577-uart[ 38$ :baudbusxokay~Bpdefaultserial@11001400*mediatek,mt8188-uartmediatek,mt6577-uart[ 38$ :baudbus xdisabledadc@11002000.mediatek,mt8188-auxadcmediatek,mt8173-auxadc 3$:main xdisabledsyscon@11003000"mediatek,mt8188-pericfg-aosyscon0 }3spi@1100a000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+[3#y#$:parent-clksel-clkspi-clkxokay~Cpdefaultthermal-sensor@1100b000mediatek,mt8188-lvts-ap [3$$Dlvts-calib-data-1 }pwm@1100e0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwm3#'$/:mainmm[ xokaypdefault~E}pwm@1100f0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwm3#($F:mainmm[  xdisabledspi@11010000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+[3#y#$2:parent-clksel-clkspi-clkxokay~Fpdefaultspi@11012000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+ [3#y#$3:parent-clksel-clkspi-clk xdisabledspi@11013000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+0[3#y#$4:parent-clksel-clkspi-clk xdisabledspi@11018000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+[3#y#$8:parent-clksel-clkspi-clk xdisabledspi@11019000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+[3#y#$9:parent-clksel-clkspi-clk xdisabledusb@11201000#mediatek,mt8188-mtu3mediatek,mtu3  - > Vmacippc ?+[#)"#v33 #3 :sys_ckref_ckmcu_ck+GH 0IhxokayGhostOJ~Kpdefaultusb@0'mediatek,mt8188-xhcimediatek,mtk-xhciVmac[#*"#v33 :sys_ckxokay]LOJethernet@11021000;mediatek,mt8188-gmacmediatek,mt8195-gmacsnps,dwmac-5.10a@[imacirq0333#A#B#C3 .:axiapbmac_mainptp_refrmii_internalmac_cg#A#B#C"###9y$MNOxokay rgmii-idPpdefaultsleep~QR    " 8*mdiosnps,dwmac-mdio+ethernet-phy@7ethernet-phy-ieee802.3-c22  }Pstmmac-axi-config M W g}Mrx-queues-config w }Nqueue0  queue1  queue2  queue3  tx-queues-config  }Oqueue0   queue1   queue2   queue3   mmc@11230000(mediatek,mt8188-mmcmediatek,mt8183-mmc # 3#$$$M!:sourcehclksource_cgcrypto_clkxokay   ' 8H G  U d s   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:maindma+xokaypdefault~qclock-controller@11283000mediatek,mt8188-imp-iic-wrap-c(0 }ausb@112a1000#mediatek,mt8188-mtu3mediatek,mtu3 *-*> Vmacippc*?+[#-"#v33#3:sys_ckref_ckmcu_ck+r 0IpxokayGhost high-speedOJusb@0'mediatek,mt8188-xhcimediatek,mtk-xhciVmac[#."#v33:sys_ckxokay]sOJ+ethernet@1 usb424,7850+mdio+ethernet-phy@1 usb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 +-+> Vmacippc+?+[#,"#v33#3:sys_ckref_ckmcu_ck+t 0I`xokayGotg high-speed OJ~updefaultusb@0'mediatek,mt8188-xhcimediatek,mtk-xhciVmac[#+"#v33:sys_ckxokay]vOJconnectorusb-c-connector USB-C dualports+port@0endpoint ?w}yport@1endpoint ?x}fports+port@0endpoint ?y}wport@1endpoint ?z}gpcie@112f0000*mediatek,mt8188-pciemediatek,mt8192-pcie/  Vpcie-mac  )pci 3+03$L$#$&$+$C3 /:pl_250mtl_26mtl_96mtl_32kperi_26mperi_mem[` D{{{{ R e| o+} ~pcie-phy9:macxokaypdefault~~interrupt-controller+}{spi@1132c000(mediatek,mt8188-normediatek,mt8186-nor23#X33 :spisfaxi#X[9+ xdisabledt-phy@11c20700.mediatek,mt8188-tphymediatek,generic-tphy-v3+9xokaypcie-phy@03#:ref }}hdmi-phy@11d5f0002mediatek,mt8188-hdmi-phymediatek,mt8195-hdmi-phy3$:pll_ref hdmi_txpll     xdisabled}dsi-phy@11c800000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx38 mipi_tx0_pll  xokay}dsi-phy@11c900000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx38 mipi_tx0_pll   xdisabled}i2c@11e00000mediatek,mt8188-i2c "[ )3$7 :maindma+xokaypdefault~i2c@11e01000mediatek,mt8188-i2c "[ )3$7 :maindma+xokaypdefault~clock-controller@11e02000mediatek,mt8188-imp-iic-wrap-w  }t-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+xokayusb-phy@03#" :refda_ref xokay}tt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+xokayusb-phy@03#" :refda_ref xokay}Gusb-phy@700 3"8 :refda_ref xokay}Ht-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+xokayusb-phy@03#" :refda_ref xokay}ri2c@11ec0000mediatek,mt8188-i2c "[ )3$7 :maindma+ xdisabledi2c@11ec1000mediatek,mt8188-i2c "[ )3$7 :maindma+ xdisabledclock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-en  }efuse@11f20000,mediatek,mt8188-efusemediatek,mt8186-efuse+dp-calib@1a0 }lvts1-calib@1ac@}Dgpu-speedbin@581 }socinfo-data1@7a0socinfo-data2@7e0gpu@13000000)mediatek,mt8370-maliarm,mali-valhall-jm@30[~} ijobmmugpu speed-bin 99 core0core1cxokay !}clock-controller@13fbf000mediatek,mt8188-mfgcfg }syscon@14000000mediatek,mt8188-vppsys0syscon }&dma-controller@14001000mediatek,mt8188-mdp3-rdma 3&<  9    *display@140020000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg 3& display@140040002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr@3&" @display@140050002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aalP[F3& 9 Pdisplay@140060002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz`3&  ` %display@140070006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshpp3&# pdisplay@140080006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color[I3&$9 display@140090002mediatek,mt8188-mdp3-ovlmediatek,mt8195-mdp3-ovl[J3&%9  display@1400a000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding3&9 display@1400b0002mediatek,mt8188-mdp3-tccmediatek,mt8195-mdp3-tcc3& display@1400c0004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot 3& 9   +mutex@1400f000mediatek,mt8188-vpp-mutex[P3&9 smi@14012000mediatek,mt8188-smi-common-vpp 3&&:apbsmi9}smi@14013000mediatek,mt8188-smi-larb03&&:apbsmi9 7 H}iommu@14018000mediatek,mt8188-iommu-vppP3&:bclk[R9m U}dma-controller@14f09000mediatek,mt8188-mdp3-rdma 3(  9  dma-controller@14f0a000mediatek,mt8188-mdp3-rdma 3(  9  display@14f0c0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg3(  display@14f0d0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg3(  display@14f0f0002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr3(" display@14f100002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr3($ display@14f120002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal [j3(#9 display@14f130002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal0[k3(%9 0display@14f150002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rszP3( P display@14f160002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz`3( ` display@14f180006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp3( display@14f190006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp3( display@14f1a0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge3(9 display@14f1b0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge3(9 display@14f1d0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color[u3(9 display@14f1e0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color[v3(9 display@14f21000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding3(9 display@14f22000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding 3(9 display@14f240004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot@ 3( 9 @ display@14f250004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrotP 3( 9 P clock-controller@14e00000mediatek,mt8188-wpesys }2clock-controller@14e02000mediatek,mt8188-wpesys-vpp0  smi@14e04000mediatek,mt8188-smi-larb@322:apbsmi9 7 H}syscon@14f00000mediatek,mt8188-vppsys1syscon }(mutex@14f01000mediatek,mt8188-vpp-mutex[{3(&9 smi@14f02000mediatek,mt8188-smi-larb 3((:apbsmi9 7 H}smi@14f03000mediatek,mt8188-smi-larb03((:apbsmi9 7 H}clock-controller@15000000mediatek,mt8188-imgsys clock-controller@15110000 mediatek,mt8188-imgsys1-dip-top Iclock-controller@15130000mediatek,mt8188-imgsys1-dip-nr Iclock-controller@15220000mediatek,mt8188-imgsys-wpe1" Iclock-controller@15330000mediatek,mt8188-ipesys3 Iclock-controller@15520000mediatek,mt8188-imgsys-wpe2R Iclock-controller@15620000mediatek,mt8188-imgsys-wpe3b Iclock-controller@16000000mediatek,mt8188-camsys }+clock-controller@1604f000mediatek,mt8188-camsys-rawa I}.clock-controller@1606f000mediatek,mt8188-camsys-yuva I}/clock-controller@1608f000mediatek,mt8188-camsys-rawb I},clock-controller@160af000mediatek,mt8188-camsys-yuvb  I}-clock-controller@17200000mediatek,mt8188-ccusys  video-decoder@18000000mediatek,mt8188-vcodec-dec @` + *video-codec@10000mediatek,mtk-vcodec-lat#4"#x 3#4))#x:selvdeclattop[H 9video-codec@25000mediatek,mtk-vcodec-coreP#4"#x 3#4**#x:selvdeclattop[X 9smi@1800d000mediatek,mt8188-smi-larb3)):apbsmi9 7 H}clock-controller@1800f000mediatek,mt8188-vdecsys-soc })smi@1802e000mediatek,mt8188-smi-larb3**:apbsmi9 7 H}clock-controller@1802f000mediatek,mt8188-vdecsys }*clock-controller@1a000000mediatek,mt8188-vencsys }1smi@1a010000mediatek,mt8188-smi-larb311:apbsmi9 7 H}video-encoder@1a020000mediatek,mt8188-vcodec-enc+#3"#p31 :venc_sel[aX 9 *jpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgenc31:jpgenc[b 9jpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdec311:jpgdec-smijpgdec[c0 9ovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovl3'[| 9 ports+port@0endpoint ?}port@1endpoint ?}rdma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdma 3'[~ 9  ports+port@0endpoint ?}port@1endpoint ?}color@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-color03'[9 0ports+port@0endpoint ?}port@1endpoint ?}ccorr@1c0040006mediatek,mt8188-disp-ccorrmediatek,mt8192-disp-ccorr@3'[9 @ports+port@0endpoint ?}port@1endpoint ?}aal@1c0050002mediatek,mt8188-disp-aalmediatek,mt8183-disp-aalP3' [9 Pports+port@0endpoint ?}port@1endpoint ?}gamma@1c0060006mediatek,mt8188-disp-gammamediatek,mt8195-disp-gamma`3'[9 `ports+port@0endpoint ?}port@1endpoint ?}dither@1c0070008mediatek,mt8188-disp-dithermediatek,mt8183-disp-ditherp3'[9 pports+port@0endpoint ?}port@1endpoint ?}dsi@1c008000mediatek,mt8188-dsi3'':enginedigitalhs[+ ~dphy9'xokay+ports+port@0endpoint ?}port@1endpoint ?}ndsc@1c0090002mediatek,mt8188-disp-dscmediatek,mt8195-disp-dsc3' [9 dsi@1c012000mediatek,mt8188-dsi 3' ':enginedigitalhs[+ ~dphy9'  xdisabledmerge0@1c0140006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge@3' 0:mergemerge_async[9 @dp-intf@1c015000mediatek,mt8188-dp-intfP3' ' ":pixelenginepll[9 xdisabledmutex@1c016000mediatek,mt8188-disp-mutex`3'[9 ` >postmask@1c01a000<mediatek,mt8188-disp-postmaskmediatek,mt8192-disp-postmask3'[9 ports+port@0endpoint ?}port@1endpoint ?}syscon@1c01d000mediatek,mt8188-vdosys0syscon I  }'port+endpoint@0 ?}smi@1c022000mediatek,mt8188-smi-larb 3'':apbsmi9 7 H}smi@1c023000mediatek,mt8188-smi-larb03'':apbsmi9 7 H}smi@1c024000mediatek,mt8188-smi-common-vdo@3'':apbsmi9}iommu@1c028000mediatek,mt8188-iommu-vdoP3':bclk[9m U}syscon@1c100000mediatek,mt8188-vdosys1syscon I  }0mutex@1c101000mediatek,mt8188-disp-mutex30[9  smi@1c102000mediatek,mt8188-smi-larb 300:apbsmi9 7 H}smi@1c103000mediatek,mt8188-smi-larb0300:apbsmi9 7 H}rdma@1c1040004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma@30[ @9  @rdma@1c1050004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaP30[ `9  Prdma@1c1060004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma`30[ A9  `rdma@1c1070004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmap30[ a9  prdma@1c1080004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma30[ B9  rdma@1c1090004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma30[ b9  rdma@1c10a0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma30[ C9  rdma@1c10b0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma30[ c9  merge@1c10c0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge30 0:mergemerge_async[90  dmerge@1c10d0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge30 0:mergemerge_async[90  dmerge@1c10e0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge30 0:mergemerge_async[90  dmerge@1c10f0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge30 0:mergemerge_async[90  dmerge@1c1100006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge30 0:mergemerge_async[90  xdpi@1c112000(mediatek,mt8188-dpimediatek,mt8195-dpi 30800=:pixelenginepll[ 90 xdisabledports+port@0endpointport@1endpointdp-intf@1c113000mediatek,mt8188-dp-intf030:0":pixelenginepll[9 xdisabledethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrp@Pp4Vmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsh3000+0.0,0/0-0<0102030405#:mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top[6 de9(0102030405p @Pppadding@1c11d000mediatek,mt8188-disp-padding309 padding@1c11e000mediatek,mt8188-disp-padding30 9 padding@1c11f000mediatek,mt8188-disp-padding30!9 padding@1c120000mediatek,mt8188-disp-padding30"9 padding@1c121000mediatek,mt8188-disp-padding30#9 padding@1c122000mediatek,mt8188-disp-padding 30$9  padding@1c123000mediatek,mt8188-disp-padding030%9 0padding@1c124000mediatek,mt8188-disp-padding@30&9 @hdmi@1c300000mediatek,mt8188-hdmi-tx0 3#@#>#?(.:bushdcphdcp24mhdmi-split#>"#s[9 + ~hdmi xdisabledi2c2mediatek,mt8188-hdmi-ddcmediatek,mt8195-hdmi-ddc38ports+port@0endpointport@1endpointedp-tx@1c500000mediatek,mt8188-edp-txP[dp_calibration_data9  xdisableddp-tx@1c600000mediatek,mt8188-dp-tx`[dp_calibration_data9  xdisabledbacklight-lcd0pwm-backlight     u0}chosen serial0:115200n8firmwareopteelinaro,optee-tzsmcmemory@40000000memory@panel-dsi0tianma,tm070jdhg30  jportendpoint ?}oreserved-memory+optee@43200000 C memory@50000000shared-dma-poolP }7memory@54600000 T` memory@55000000shared-dma-poolU@memory@57000000shared-dma-poolW@memory@60000000shared-dma-pool` }?memory@60f00000shared-dma-pool` };memory@61000000shared-dma-poola }>regulator-efuseregulator-outputregulator-1v8regulator-fixedreg_1v8w@w@B}hregulator-3v3regulator-fixedreg_3v32Z2ZB}iregulator-5vregulator-fixedreg_5vLK@LK@B}jregulator-sdcard-enregulator-fixedBsdcard_en_3v32Z2Z  o}Zregulator-usb-p0-vbusregulator-fixedvbus_p0LK@LK@  T}vregulator-usb-p1-vbusregulator-fixedpdefault~vbus_p1w@w@  }Lregulator-usb-p2-vbusregulator-fixedpdefault~vbus_p2w@w@  P}swifi-pwrseqmmc-pwrseq-simplepdefault~0 3 Y}` compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7dsi0ethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6mmc0mmc1mmc2rtc0rtc1serial0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellscpu-supplyphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-downinput-enabledrive-strengthbias-pull-upoutput-highinput-disablebias-disabledrive-strength-microampoutput-low#power-domain-cellsdomain-supplyclocksclock-namesmediatek,infracfgmediatek,disable-extrstpinctrl-namespinctrl-0#sound-dai-cellsinterrupts-extended#io-channel-cellsmediatek,mic-type-0mediatek,mic-type-1regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-boot-onregulator-coupled-withregulator-coupled-max-spreadmediatek,long-press-modepower-off-time-seclinux,keycodeswakeup-sourceassigned-clocksassigned-clock-parentsregulator-on-in-suspendregulator-suspend-microvolt#iommu-cells#mbox-cellsmemory-regionpower-domainsresetsreset-namesmediatek,topckgenmboxesmbox-namesmediatek,pad-selectnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsphysmediatek,syscon-wakeupdr_modevusb33-supplyvbus-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlepinctrl-1mediatek,mac-wolsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ussnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymax-frequencymmc-hs200-1_8vmmc-hs400-1_8vnon-removableno-sdno-sdiosupports-cqevmmc-supplyvqmmc-supplycap-sd-highspeedsd-uhs-sdr104sd-uhs-sdr50cd-gpioscap-sdio-irqkeep-power-in-suspendno-mmcpinctrl-2mmc-pwrseqclock-divreset-gpiosremote-endpointAVDD-supplyCPVDD-supplyDBVDD-supplyDCVDD-supplyMICVDD-supplyPLLVDD-supplySPKVDD1-supplySPKVDD2-supplygpio-cfgenable-gpiosdata-lanesirq-gpiosmaximum-speedmicrochip,led-modesusb-role-switchlabeldata-rolebus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-names#phy-cellsmediatek,ibiasmediatek,ibias_upbitsoperating-points-v2power-domain-namesmali-supply#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzbrightness-levelsdefault-brightness-levelnum-interpolated-stepspwmsstdout-pathbacklightpower-supplyno-mapvout-supplyenable-active-highpost-power-on-delay-ms