U8G,(WF4mediatek,mt8390-evkmediatek,mt8390mediatek,mt8188 +7MediaTek Genio-700 EVKaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/dsc@1c009000Y/soc/ethdr@1c114000`/soc/mailbox@10320000e/soc/mailbox@10330000j/soc/merge0@1c014000q/soc/merge@1c10c000x/soc/merge@1c10d000/soc/merge@1c10e000/soc/merge@1c10f000/soc/merge@1c110000/soc/mutex@1c016000/soc/mutex@1c101000/soc/padding@1c11d000/soc/padding@1c11e000/soc/padding@1c11f000/soc/padding@1c120000/soc/padding@1c121000/soc/padding@1c122000/soc/padding@1c123000/soc/padding@1c124000/soc/rdma@1c104000/soc/rdma@1c105000/soc/rdma@1c106000 /soc/rdma@1c107000/soc/rdma@1c108000!/soc/rdma@1c109000,/soc/rdma@1c10a0007/soc/rdma@1c10b000B/soc/dsi@1c008000G/soc/ethernet@11021000Q/soc/i2c@11280000V/soc/i2c@11e00000[/soc/i2c@11281000`/soc/i2c@11282000e/soc/i2c@11e01000j/soc/i2c@11ec0000o/soc/i2c@11ec1000t/soc/mmc@11230000y/soc/mmc@11240000~/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55psciw5@@"/@Tc cpu@100cpuarm,cortex-a55psciw5@@"/@Tc cpu@200cpuarm,cortex-a55psciw5@@"/@Tc cpu@300cpuarm,cortex-a55psciw5@@"/@Tc cpu@400cpuarm,cortex-a55psciw5@@"/@Tc cpu@500cpuarm,cortex-a55psciw5@@"/@Tccpu@600cpuarm,cortex-a78psci@@"/@Tccpu@700cpuarm,cortex-a78psci@@"/@Tccpu-mapcluster0core0k core1k core2k core3k core4k core5kcore6kcore7kidle-statesopscicpu-off-larm,idle-state|2_Dccpu-off-barm,idle-state|-ccluster-off-larm,idle-state|7Hccluster-off-barm,idle-state|2cl2-cache0cache@/cl2-cache1cache@/cl3-cachecache @coscillator-13m fixed-clock]@clk13mc:oscillator-26m fixed-clockclk26mc<oscillator-32k fixed-clockclk32kopp-table-gpuoperating-points-v2copp-390000000>"0opp-431000000"0opp-4730000001h@" '0opp-515000000F" X0opp-556000000!#" h0opp-598000000#" <0opp-640000000&%" 0opp-670000000'c" 0opp-700000000)'" L0opp-730000000+" }0opp-760000000-L" `0opp-790000000/q" 40opp-8350000001" (r0opp-8800000004s" q0opp-9150000006" X0opp-915000000-56" 00opp-915000000-66" q0popp-9500000008ـ" 50opp-950000000-58ـ" X00opp-950000000-68ـ" q0ppmu-a55arm,cortex-a55-pmu Apmu-a78arm,cortex-a78-pmu Apsci arm,psci-1.0smcsoundL^okay6mediatek,mt8390-mt6359-evkmediatek,mt8188-mt6359-evb 7mt8390-evkedefaultst}HeadphoneHeadphone LHeadphoneHeadphone RDMIC_INPUTAP DMICAP DMICAUDGLBAP DMICMIC_BIAS_0AP DMICMIC_BIAS_2dai-link-0 DL_SRC_BEcodecdai-link-1DMIC_BEcodecdai-link-2 ETDM3_OUT_BEcodecthermal-zonescpu-little0-thermaltripstrip-alert0Lpassivectrip-alert1shottrip-crit criticalcooling-mapsmap0H cpu-little1-thermaltripstrip-alert0Lpassivectrip-alert1shottrip-crit criticalcooling-mapsmap0H cpu-little2-thermaltripstrip-alert0Lpassivectrip-alert1shottrip-crit criticalcooling-mapsmap0H cpu-little3-thermaltripstrip-alert0Lpassivectrip-alert1shottrip-crit criticalcooling-mapsmap0H cpu-big0-thermaldtripstrip-alert0Lpassivectrip-alert1shottrip-crit criticalcooling-mapsmap0cpu-big1-thermaldtripstrip-alert0Lpassivec trip-alert1shottrip-crit criticalcooling-mapsmap0 apu-thermal!tripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalgpu-thermal!tripstrip-alert0Lpassivec"trip-alert1shottrip-crit criticalcooling-mapsmap0" #gpu1-thermal!tripstrip-alert0Lpassivec$trip-alert1shottrip-crit criticalcooling-mapsmap0$ #adsp-thermal!tripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalvdo-thermal!tripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalinfra-thermal!tripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalcam1-thermal!tripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalcam2-thermal!tripstrip-alert0Lpassivetrip-alert1shottrip-crit criticaltimerarm,armv8-timer @A   ]@soc+ simple-bus performance-controller@11bc10mediatek,cpufreq-hw  0 cinterrupt-controller@c000000 arm,gic-v31B Y    A cppi-partitionsinterrupt-partition-0n cinterrupt-partition-1ncsyscon@10000000 mediatek,mt8188-topckgensysconc(syscon@10001000#mediatek,mt8188-infracfg-aosysconwc)syscon@10003000mediatek,mt8188-pericfgsyscon0cLpinctrl@10005000mediatek,mt8188-pinctrl`P0iocfg0iocfg_rmiocfg_ltiocfg_lmiocfg_rteint%YA1c%audio-default-pinscpins-cmd-datXefghijklmnrstuvyz|}~disp-pwm1-pinscHpins-pwmdptx-pinspins-cmd-dat.edp-panel-3v3-en-pinscpins1eth-default-pinscXpins-ccpins-mdiopins-powerpins-rxdpins-txdeth-sleep-pinscYpins-ccpins-mdiopins-rxdpins-txdhdmi-vreg-pinsctpins-pwr2hdmi-pinscpins-hotplug3 pins-cec4pins-ddc56 i2c0-pinsccpins87i2c1-pinscvpins:9i2c2-pinscgpins<;i2c3-pinschpins>=i2c4-pinscypins@?i2c5-pinscpinsBAi2c6-pinscpinsDCgpio-key-pinspins *+,mmc0-default-pinscZpins-clk fpins-cmd-dat$epins-rstemmc0-uhs-pinsc[pins-clk fpins-cmd-dat$epins-ds fpins-rstemmc1-default-pinsc^pins-clk fpins-cmd-datepins-insertmmc1-uhs-pinsc_pins-clk fpins-cmd-datemmc2-default-pinspins-clk fpins-cmd-datepins-pcm{mmc2-uhs-pinspins-clk fpins-cmd-datemmc2-eint-pinspins-dat1emmc2-dat1-pinspins-dat1edsi0-vreg-en-pinscpins-pwr-eno4panel-default-pinscpins-rst4pins-en-4pcie-default-pinscspins /01rt1715-int-pinspins_cmd0_dat spi0-pinspins-spiEFGHspi1-pinspins-spiKLMNspi2-pinscIpins-spiOPQRtouch-avdd-pinscpins-powerxtouch-pinscfpins-irqpins-resettcpci-int-pinsczpins-int-n uart0-pinscDpins uart1-pinscEpins!"uart2-pinscFpins#$usb-default-pinscnpins-iddigSpins-validUpins-vbusTusb1-default-pinscNpins-validXpins-usb-hub-3v3-enpusb2-default-pinscjpins-iddigYwifi-pwrseq-pinspins-wifi-enable4syscon@10006000)mediatek,mt8188-scpsyssysconsimple-mfd`power-controller!mediatek,mt8188-power-controller+?c=power-domain@0+?S&power-domain@1a'(hmfgaltt)+?S*power-domain@2?power-domain@3?power-domain@4?power-domain@15a(((( (3(4(=((+ + +++++++++++++++++ htopcamccuimgvencvdecwpecfgckcfgxoss-sram-cmnss-sram-v0l0ss-sram-v0l1ss-sram-ve0ss-sram-ve1ss-sram-ifass-sram-camss-sram-v1l5ss-sram-v1l6ss-sram-rdrss-iommuss-imgcamss-emiss-subcmn-rdrss-rsiss-cmn-l4ss-vdec1ss-wpess-cvdo-ve1t)+?power-domain@16Ha((,,,,,,,Ahcfgckcfgxoss-galsss-cmnss-emiss-iommuss-larbss-rsiss-bust)+?power-domain@200a((----8hcfgckcfgxoss-vpp1-g5ss-vpp1-g6ss-vpp1-l5ss-vpp1-l6t)?power-domain@22a.hss-vdec1-soc-l1t)+?power-domain@23a/ hss-vdec2-l1t)?power-domain@29 a((( (hcamccubuscfgckt)+?power-domain@30(a000006hss-cam-l13ss-cam-l14ss-cam-mm0ss-cam-mm1ss-camsyst)+?power-domain@32 a012$hss-camb-subss-camb-rawss-camb-yuv?power-domain@31a034$hss-cama-subss-cama-rawss-cama-yuv?power-domain@17(a((555&hcfgckcfgxoss-larb2ss-larb3ss-galst)+?power-domain@9 a(@(? hbushdcpt)?power-domain@18t)?power-domain@19t)?power-domain@24 a66660hss-ve1-larbss-ve1-coress-ve1-galsss-ve1-sramt)?power-domain@21a77hss-wpe-l7ss-wpe-l7pcet)?power-domain@5t)a8 hss-pextp-fmem?power-domain@7a(0(1hseninf0seninf1?power-domain@6?power-domain@10 a(E(D hbusmaint)+?power-domain@11 t)+?power-domain@14a(Fhasmt)?power-domain@13 a(S(9ha1sysintbusadspckt)?power-domain@12 t)?power-domain@8a8  hethermact)?watchdog@10007000mediatek,mt8188-wdtpwc>syscon@1000c000"mediatek,mt8188-apmixedsyssysconc'timer@10017000,mediatek,mt8188-timermediatek,mt6765-timerpA a:pwrap@100240003mediatek,mt8188-pwrapmediatek,mt8195-pwrapsyscon@pwrapAa)) hspiwrappmicmediatek,mt6359Y1 %Acadcmediatek,mt6359-auxadcaudio-codecmediatek,mt6359-codecregulatorsmediatek,mt6359-regulatorbuck_vs1vs1 5!(Dbuck_vgpu11 dvdd_core7X( mDbuck_vmodemvmodemX*(buck_vpu dvdd_adsp7X( mDbuck_vcore dvdd_proc_l X( mDbuck_vs2vs2 5j(Dbuck_vpavpa_pmu /M`(,c`buck_vproc2vgpudp 5XL( m*jc&buck_vproc1vproc17XL( mbuck_vcore_sshub vcore_sshub7buck_vgpu11_sshub vgpu11_sshub7ldo_vaud18vaud18w@w@(ldo_vsim1 vsim1_pmu/M`(caldo_vibrvibrO2Zldo_vrf12va12_abb2_pmu Dldo_vusbvusb--(DcMldo_vsram_proc2 vsram_proc2 XL(Dldo_vio18vio18(Dceldo_vcamiovcamioldo_vcn18 vcn18_pmuw@w@(Dldo_vfe28vfe28**(xldo_vcn13vcn13  ldo_vcn33_1_bt vcn33_1_bt*5gcwldo_vcn33_1_wifi vcn33_1_wifi*5gldo_vaux18vaux18w@w@(Dldo_vsram_others vsram_gpu q 5X(&jc*ldo_vefusevefuseldo_vxo22vxo22w@!Dldo_vrfckvrfck`ldo_vrfck_1vrfckjldo_vbif28vbif28**(ldo_vio28vio28*2ZDldo_vemcvemc,@ 2Zldo_vemc_1vemc&%2Zc\ldo_vcn33_2_bt vcn33_2_pmu*5gDldo_vcn33_2_wifi vcn33_2_wifi*5gldo_va12va12O Dldo_va09va09 5Oldo_vrf18vrf18Pldo_vsram_md vsram_md X*(ldo_vufs vufs18_pmuDc]ldo_vm18vm18Dldo_vbbckvbbckODldo_vsram_proc1 vsram_proc1 XL(Dldo_vsim2vsim2/M`ldo_vsram_others_sshubvsram_others_sshub rtcmediatek,mt6358-rtckeysmediatek,mt6359-keyspower-keythomefspmi@10027000*mediatek,mt8188-spmimediatek,mt8195-spmi p pmifspmimst(8(a))(8(hpmif_sys_ckpmif_tmr_ckspmimst_clk_muxiommu@10315000mediatek,mt8188-iommu-infra1PA)cqmailbox@10320000mediatek,mt8188-gce2@A6a)cmailbox@10330000mediatek,mt8188-gce3@A6a)cscp@10720000mediatek,mt8188-scp-dualrcfg+P^okayscp@0mediatek,scp-core sramA^okayB;cscp@d0000mediatek,scp-core sramA ^disabledaudio-controller@10b10000mediatek,mt8188-afe(S(a<' ' ((((((S(( (E(Q(M(N(O(P9((((T(Rhclk26mapll1apll2apll12_div0apll12_div1apll12_div2apll12_div3apll12_div9top_a1sys_hptop_aud_intbustop_audio_htop_audio_local_bustop_dptxtop_i2so1top_i2so2top_i2si1top_i2si2adsp_audio_26mapll1_d4apll2_d4apll12_div4top_a2systop_aud_iecA6P= ^> eaudiosyst)q(^okayB?cadsp@10b80000mediatek,mt8188-dsp@ cfgsramsecbus(Da(D(Ehaudiodspadsp_bus@ArxtxP= ^okayBBCcmailbox@10b861004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxaA6c@mailbox@10b871004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxqA6cAclock-controller@10b91100mediatek,mt8188-adsp-audio26mc9serial@11001100*mediatek,mt8188-uartmediatek,mt6577-uartA a<) hbaudbus^okaysDedefaultserial@11001200*mediatek,mt8188-uartmediatek,mt6577-uartA a<) hbaudbus^okaysEedefaultserial@11001300*mediatek,mt8188-uartmediatek,mt6577-uartA a<) hbaudbus^okaysFedefaultserial@11001400*mediatek,mt8188-uartmediatek,mt6577-uartA a<) hbaudbus ^disabledadc@11002000.mediatek,mt8188-auxadcmediatek,mt8173-auxadc a)hmain ^disabledsyscon@11003000"mediatek,mt8188-pericfg-aosyscon0c8spi@1100a000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+Aa(y()hparent-clksel-clkspi-clk ^disabledthermal-sensor@1100b000mediatek,mt8188-lvts-ap Aa)^)Glvts-calib-data-1c!pwm@1100e0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwma(')/hmainmmA ^disabledpwm@1100f0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwma(()FhmainmmA^okayedefaultsHcspi@11010000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+Aa(y()2hparent-clksel-clkspi-clk ^disabledspi@11012000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+ Aa(y()3hparent-clksel-clkspi-clk^okaysIedefaultspi@11013000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+0Aa(y()4hparent-clksel-clkspi-clk ^disabledspi@11018000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+Aa(y()8hparent-clksel-clkspi-clk ^disabledspi@11019000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+Aa(y()9hparent-clksel-clkspi-clk ^disabledusb@11201000#mediatek,mt8188-mtu3mediatek,mtu3  - > macippc ?+A()(va8 (8 hsys_ckref_ckmcu_ckJK Lh^okayotg MsNedefaultusb@0'mediatek,mt8188-xhcimediatek,mtk-xhcimacA(*(va8 hsys_ck^okayM+hub@1 usb451,8025)O 2%>PcQhub@2 usb451,8027)Q 2%>PcOportendpointIRc}portendpointISc|ethernet@11021000;mediatek,mt8188-gmacmediatek,mt8195-gmacsnps,dwmac-5.10a@AYmacirq0a88(A(B(C8 .haxiapbmac_mainptp_refrmii_internalmac_cg(A(B(C(((P=i)zTUV^okay rgmii-idWedefaultsleepsXY % ''mdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916cWstmmac-axi-config ' 1 AcTrx-queues-config Q gcUqueue0 x queue1 x queue2 x queue3 x tx-queues-config  cVqueue0 x  queue1 x  queue2 x  queue3 x  mmc@11230000(mediatek,mt8188-mmcmediatek,mt8183-mmc #  a()))M!hsourcehclksource_cgcrypto_clk^okayedefaultstate_uhssZ[     # 2 A N _ g mH |\ ] mmc@11240000(mediatek,mt8188-mmcmediatek,mt8183-mmc $ a())$hsourcehclksource_cg((^okayedefaultstate_uhss^_        _ % |` ammc@11250000(mediatek,mt8188-mmcmediatek,mt8183-mmc % a())Ahsourcehclksource_cg(( ^disabledthermal-sensor@11278000mediatek,mt8188-lvts-mcu'Aa)^)Glvts-calib-data-1ci2c@11280000mediatek,mt8188-i2c ("A ab)7 hmaindma+^okayedefaultsctouchscreen@5dgoodix,gt9271] % % % 2% d eedefaultsfi2c@11281000mediatek,mt8188-i2c ("A ab)7 hmaindma+^okayedefaultsgi2c@11282000mediatek,mt8188-i2c ( "A ab)7 hmaindma+^okayedefaultshclock-controller@11283000mediatek,mt8188-imp-iic-wrap-c(0cbusb@112a1000#mediatek,mt8188-mtu3mediatek,mtu3 *-*> macippc*?+A(-(va8(8hsys_ckref_ckmcu_cki Lp^okayotg high-speed host Medefaultsjusb@0'mediatek,mt8188-xhcimediatek,mtk-xhcimacA(.(va8hsys_ck^okayM 5kconnector%gpio-usb-b-connectorusb-b-connectormicro A%Y 5lusb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 +-+> macippc+?+A(,(va8(8hsys_ckref_ckmcu_ckm L`^okayotg high-speed Msnedefaultusb@0'mediatek,mt8188-xhcimediatek,mtk-xhcimacA(+(va8hsys_ck^okayconnector%gpio-usb-b-connectorusb-b-connectormicro A%S 5opcie@112f0000*mediatek,mt8188-pciemediatek,mt8192-pcie/  pcie-mac  Jpci T+0a)L)#)&)+)C8 /hpl_250mtl_26mtl_96mtl_32kperi_26mperi_mem1A` epppp s q r pcie-phyP=^>emac^okayedefaultssinterrupt-controller1Ycpspi@1132c000(mediatek,mt8188-normediatek,mt8186-nor2a(X88 hspisfaxi(XA9+ ^disabledt-phy@11c20700.mediatek,mt8188-tphymediatek,generic-tphy-v3+P=^okaypcie-phy@0a(href crhdmi-phy@11d5f0002mediatek,mt8188-hdmi-phymediatek,mt8195-hdmi-phya)hpll_ref hdmi_txpll   ^okayedefaultstcdsi-phy@11c800000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-txa< mipi_tx0_pll ^okaycdsi-phy@11c900000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-txa< mipi_tx0_pll  ^disabledci2c@11e00000mediatek,mt8188-i2c "A au)7 hmaindma+^okayedefaultsvtypec-mux@48 ite,it5205H   wportendpointIxc~i2c@11e01000mediatek,mt8188-i2c "A au)7 hmaindma+^okayedefaultsyB@rt1715@4erichtek,rt1715N % edefaultsz 5{connectorusb-c-connector USB-C dual  !dual ,sink ; G" Q"altmodesdisplayport ] bGports+port@0endpointI|cSport@1endpointI}cRport@2endpointI~cxclock-controller@11e02000mediatek,mt8188-imp-iic-wrap-w cut-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+^okayusb-phy@0a(' hrefda_ref cmt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+^okayusb-phy@0a(' hrefda_ref cJusb-phy@700 a'< hrefda_ref cKt-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+^okayusb-phy@0a(' hrefda_ref cii2c@11ec0000mediatek,mt8188-i2c "A a)7 hmaindma+^okayedefaultsi2c@11ec1000mediatek,mt8188-i2c "A a)7 hmaindma+^okayedefaultsclock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-en cefuse@11f20000,mediatek,mt8188-efusemediatek,mt8186-efuse+dp-calib@1a0 clvts1-calib@1ac@cGgpu-speedbin@581 fcsocinfo-data1@7a0socinfo-data2@7e0gpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jm@a0A~} Yjobmmugpu speed-bin kP=== core0core1core2T^okay &c#clock-controller@13fbf000mediatek,mt8188-mfgcfgcsyscon@14000000mediatek,mt8188-vppsys0sysconc+dma-controller@14001000mediatek,mt8188-mdp3-rdma a+<  P=    display@140020000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg a+ display@140040002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr@a+" @display@140050002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aalPAFa+ P= Pdisplay@140060002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz`a+  ` %display@140070006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshppa+# pdisplay@140080006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-colorAIa+$P= display@140090002mediatek,mt8188-mdp3-ovlmediatek,mt8195-mdp3-ovlAJa+%P=  display@1400a000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-paddinga+P= display@1400b0002mediatek,mt8188-mdp3-tccmediatek,mt8195-mdp3-tcca+ display@1400c0004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot a+ P=   +mutex@1400f000mediatek,mt8188-vpp-mutexAPa+P= smi@14012000mediatek,mt8188-smi-common-vpp a++hapbsmiP=csmi@14013000mediatek,mt8188-smi-larb0a++hapbsmiP=  ciommu@14018000mediatek,mt8188-iommu-vppPa+hbclkARP=) cdma-controller@14f09000mediatek,mt8188-mdp3-rdma a-  P=  dma-controller@14f0a000mediatek,mt8188-mdp3-rdma a-  P=  display@14f0c0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fga-  display@14f0d0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fga-  display@14f0f0002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdra-" display@14f100002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdra-$ display@14f120002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal Aja-#P= display@14f130002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal0Aka-%P= 0display@14f150002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rszPa- P display@14f160002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz`a- ` display@14f180006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshpa- display@14f190006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshpa- display@14f1a0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-mergea-P= display@14f1b0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-mergea-P= display@14f1d0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-colorAua-P= display@14f1e0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-colorAva-P= display@14f21000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-paddinga-P= display@14f22000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding a-P= display@14f240004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot@ a- P= @ display@14f250004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrotP a- P= P clock-controller@14e00000mediatek,mt8188-wpesysc7clock-controller@14e02000mediatek,mt8188-wpesys-vpp0 smi@14e04000mediatek,mt8188-smi-larb@a77hapbsmiP=  csyscon@14f00000mediatek,mt8188-vppsys1sysconc-mutex@14f01000mediatek,mt8188-vpp-mutexA{a-&P= smi@14f02000mediatek,mt8188-smi-larb a--hapbsmiP=  csmi@14f03000mediatek,mt8188-smi-larb0a--hapbsmiP=  cclock-controller@15000000mediatek,mt8188-imgsysclock-controller@15110000 mediatek,mt8188-imgsys1-dip-topwclock-controller@15130000mediatek,mt8188-imgsys1-dip-nrwclock-controller@15220000mediatek,mt8188-imgsys-wpe1"wclock-controller@15330000mediatek,mt8188-ipesys3wclock-controller@15520000mediatek,mt8188-imgsys-wpe2Rwclock-controller@15620000mediatek,mt8188-imgsys-wpe3bwclock-controller@16000000mediatek,mt8188-camsysc0clock-controller@1604f000mediatek,mt8188-camsys-rawawc3clock-controller@1606f000mediatek,mt8188-camsys-yuvawc4clock-controller@1608f000mediatek,mt8188-camsys-rawbwc1clock-controller@160af000mediatek,mt8188-camsys-yuvb wc2clock-controller@17200000mediatek,mt8188-ccusys video-decoder@18000000mediatek,mt8188-vcodec-dec @` + video-codec@10000mediatek,mtk-vcodec-lat(4(x a(4..(xhselvdeclattopAH P=video-codec@25000mediatek,mtk-vcodec-coreP(4(x a(4//(xhselvdeclattopAX P=smi@1800d000mediatek,mt8188-smi-larba..hapbsmiP=  cclock-controller@1800f000mediatek,mt8188-vdecsys-socc.smi@1802e000mediatek,mt8188-smi-larba//hapbsmiP=  cclock-controller@1802f000mediatek,mt8188-vdecsysc/clock-controller@1a000000mediatek,mt8188-vencsysc6smi@1a010000mediatek,mt8188-smi-larba66hapbsmiP=  cvideo-encoder@1a020000mediatek,mt8188-vcodec-enc+(3(pa6 hvenc_selAaX P= jpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgenca6hjpgencAb P=jpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdeca66hjpgdec-smijpgdecAc0 P=ovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovla,A| P= ports+port@0endpointIcport@1endpointIcrdma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdma a,A~ P=  ports+port@0endpointIcport@1endpointIccolor@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-color0a,AP= 0ports+port@0endpointIcport@1endpointIcccorr@1c0040006mediatek,mt8188-disp-ccorrmediatek,mt8192-disp-ccorr@a,AP= @ports+port@0endpointIcport@1endpointIcaal@1c0050002mediatek,mt8188-disp-aalmediatek,mt8183-disp-aalPa, AP= Pports+port@0endpointIcport@1endpointIcgamma@1c0060006mediatek,mt8188-disp-gammamediatek,mt8195-disp-gamma`a,AP= `ports+port@0endpointIcport@1endpointIcdither@1c0070008mediatek,mt8188-disp-dithermediatek,mt8183-disp-ditherpa,AP= pports+port@0endpointIcport@1endpointIcdsi@1c008000mediatek,mt8188-dsia,,henginedigitalhsA dphyP=^,^okay+panel@0#startek,kd070fhfid078himax,hx8279  %- 2% ->edefaultsportendpointIcports+port@0endpointIcport@1endpointIcdsc@1c0090002mediatek,mt8188-disp-dscmediatek,mt8195-disp-dsca, AP= dsi@1c012000mediatek,mt8188-dsi a, ,henginedigitalhsA dphyP=^,  ^disabledmerge0@1c0140006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge@a, 5hmergemerge_asyncAP= @dp-intf@1c015000mediatek,mt8188-dp-intfPa, , 'hpixelenginepllAP= ^disabledmutex@1c016000mediatek,mt8188-disp-mutex`a,AP= ` >postmask@1c01a000<mediatek,mt8188-disp-postmaskmediatek,mt8192-disp-postmaska,AP= ports+port@0endpointIcport@1endpointIcsyscon@1c01d000mediatek,mt8188-vdosys0sysconw  c,port+endpoint@0Icsmi@1c022000mediatek,mt8188-smi-larb a,,hapbsmiP=  csmi@1c023000mediatek,mt8188-smi-larb0a,,hapbsmiP=  csmi@1c024000mediatek,mt8188-smi-common-vdo@a,,hapbsmiP=ciommu@1c028000mediatek,mt8188-iommu-vdoPa,hbclkAP=) csyscon@1c100000mediatek,mt8188-vdosys1sysconw  c5port+endpoint@1Icmutex@1c101000mediatek,mt8188-disp-mutexa5AP=  smi@1c102000mediatek,mt8188-smi-larb a55hapbsmiP=  csmi@1c103000mediatek,mt8188-smi-larb0a55hapbsmiP=  crdma@1c1040004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma@a5A @P=  @rdma@1c1050004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaPa5A `P=  Prdma@1c1060004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma`a5A AP=  `rdma@1c1070004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmapa5A aP=  prdma@1c1080004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaa5A BP=  rdma@1c1090004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaa5A bP=  rdma@1c10a0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaa5A CP=  rdma@1c10b0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaa5A cP=  merge@1c10c0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergea5 5hmergemerge_asyncAP=^5  :merge@1c10d0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergea5 5hmergemerge_asyncAP=^5  :merge@1c10e0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergea5 5hmergemerge_asyncAP=^5  :merge@1c10f0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergea5 5hmergemerge_asyncAP=^5  :merge@1c1100006mediatek,mt8188-disp-mergemediatek,mt8195-disp-mergea5 5hmergemerge_asyncAP=^5  Nports+port@0+endpoint@1Icport@1+endpoint@1Icdpi@1c112000(mediatek,mt8188-dpimediatek,mt8195-dpi a5855=hpixelenginepllA P=^5^okayports+port@0endpointIcport@1endpointIcdp-intf@1c113000mediatek,mt8188-dp-intf0a5:5'hpixelenginepllAP= ^disabledethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrp@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsha505+5.5,5/5-5<5152535455(hmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_topA6 deP=(^5152535455p @Ppports+port@0+endpoint@1Icport@1+endpoint@1Icpadding@1c11d000mediatek,mt8188-disp-paddinga5P= padding@1c11e000mediatek,mt8188-disp-paddinga5 P= padding@1c11f000mediatek,mt8188-disp-paddinga5!P= padding@1c120000mediatek,mt8188-disp-paddinga5"P= padding@1c121000mediatek,mt8188-disp-paddinga5#P= padding@1c122000mediatek,mt8188-disp-padding a5$P=  padding@1c123000mediatek,mt8188-disp-padding0a5%P= 0padding@1c124000mediatek,mt8188-disp-padding@a5&P= @hdmi@1c300000mediatek,mt8188-hdmi-tx0 a(@(>(?-.hbushdcphdcp24mhdmi-split(>(sAP=  hdmi^okayedefaultsci2c2mediatek,mt8188-hdmi-ddcmediatek,mt8195-hdmi-ddca<cports+port@0endpointIcport@1endpointIcedp-tx@1c500000mediatek,mt8188-edp-txPAdp_calibration_dataP= e ^disableddp-tx@1c600000mediatek,mt8188-dp-tx`Adp_calibration_dataP= e ^disabledbacklight-lcm1pwm-backlight v @    cchosen serial0:921600n8dmic-codec dmic-codec  cconnectorhdmi-connector hdmia  portendpointIcfirmwareopteelinaro,optee-tzsmcreserved-memory+optee@43200000C memory@50000000shared-dma-poolPc;memory@54600000T` memory@55000000shared-dma-poolU@memory@57000000shared-dma-poolW@memory@60000000shared-dma-pool`cCmemory@60f00000shared-dma-pool`c?memory@61000000shared-dma-poolacBregulator-0regulator-fixedvdd_5vLK@LK@ % D)regulator-1regulator-fixed vedp_3v32Z2Z %edefaults)regulator-2regulator-fixedext_3v32Z2Z % D)regulator-vsysregulator-fixedvsysD4cregulator-3regulator-fixed vio18_connw@w@Dregulator-4regulator-fixed wifi_3v32Z2Z %JD)ckregulator-5regulator-fixed vio33_tp12Z2Z %w)edefaultscdregulator-6regulator-fixed vhub_3v32Z2Z %pF')cPregulator-7regulator-fixedvbus_p0LK@LK@ %T)coregulator-8regulator-fixedvbus_p1LK@LK@ %W)c{regulator-9regulator-fixedvbus_p2LK@LK@clregulator-vio18-lcm1regulator-fixed vio18_lcm1w@w@ %oedefaults)cregulator-vsys-lcm1regulator-fixed vsys_lcm1@@@@D4)cmemory@40000000memory@ compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7dsi0ethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6mmc0mmc1serial0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspinctrl-namespinctrl-0audio-routingmediatek,adsplink-namesound-daipolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-upoutput-highdrive-strengthinput-enableinput-disablebias-disablebias-pull-downdrive-strength-microampoutput-low#power-domain-cellsdomain-supplyclocksclock-namesmediatek,infracfgmediatek,disable-extrst#sound-dai-cells#io-channel-cellsmediatek,mic-type-0mediatek,mic-type-1regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadmediatek,long-press-modepower-off-time-seclinux,keycodeswakeup-sourceassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellsmemory-regionpower-domainsresetsreset-namesmediatek,topckgenmboxesmbox-namesnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsmediatek,pad-selectphysmediatek,syscon-wakeupdr_modeusb-role-switchvusb33-supplypeer-hubreset-gpiosvdd-supplyremote-endpointinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlepinctrl-1mediatek,mac-wolsnps,reset-gpiosnps,reset-delays-ussnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightinterrupts-extendedbus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqecap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmccd-gpiosclock-divirq-gpiosAVDD28-supplyVDDIO-supplymaximum-speedrole-switch-default-modevbus-supplyid-gpiosbus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-names#phy-cellsmediatek,ibiasmediatek,ibias_upmode-switchorientation-switchvcc-supplylabeldata-roleop-sink-microwattpower-roletry-power-rolepd-revisionsink-pdossource-pdossvidvdobitsoperating-points-v2power-domain-namesmali-supply#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsbacklightenable-gpiosiovcc-supplymediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzbrightness-levelsdefault-brightness-levelnum-interpolated-stepspower-supplypwmsstdout-pathnum-channelswakeup-delay-msddc-i2c-bushdmi-pwr-supplyno-mapenable-active-highvin-supplyregulator-boot-onstartup-delay-us