w8i( h4mediatek,mt8395-evkmediatek,mt8395mediatek,mt8195 +"7MediaTek Genio 1200 EVK-P1V2-EMMCaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/mailbox@10320000Y/soc/mailbox@10330000^/soc/hdmi-tx@1c300000d/soc/hdr-engine@1c114000k/soc/mutex@1c016000r/soc/mutex@1c101000y/soc/vpp-merge@1c10c000/soc/vpp-merge@1c10d000/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/serial@11001100/soc/ethernet@11021000cpus+cpu@0cpuarm,cortex-a55psci$8ec3@H4[kx@@ cpu@100cpuarm,cortex-a55psci$8ec3@H4[kx@@ cpu@200cpuarm,cortex-a55psci$8ec3@H4[kx@@ cpu@300cpuarm,cortex-a55psci$8ec3@H4[kx@@cpu@400cpuarm,cortex-a78psci$8fH[kx@@  cpu@500cpuarm,cortex-a78psci$8fH[kx@@  cpu@600cpuarm,cortex-a78psci$8fH[kx@@  cpu@700cpuarm,cortex-a78psci$8fH[kx@@  cpu-mapcluster0core0 core1 core2 core3core4core5core6core7idle-statespscicpu-retention-larm,idle-state/2@_PDcpu-retention-barm,idle-state/-@Pcpu-off-larm,idle-state/7@PHcpu-off-barm,idle-state/2@Pl2-cache0cacheamz@ml2-cache1cacheamz@m l3-cachecacheam z@mdsu-pmu arm,dsu-pmu{  faildmic-codec dmic-codecmt8195-soundokaymediatek,mt8195_mt6359 7mt8395-evkdefault,HeadphoneHeadphone LHeadphoneHeadphone Rheadphone-dai-link DL_SRC_BEcodechdmi-dai-link ETDM3_OUT_BEcodecfixed-factor-clock-13mfixed-factor-clock '2clk13m0oscillator-26m fixed-clock 82clk26moscillator-32k fixed-clock 82clk32kperformance-controller@11bc10mediatek,cpufreq-hw  0 Eopp-table-gpuoperating-points-v2_opp-390000000j>q hopp-410000000jpq opp-431000000jq opp-473000000j1h@q <opp-515000000jFq <opp-556000000j!#q Ҧopp-598000000j#q opp-640000000j&%q opp-670000000j'cq opp-700000000j)'q Lopp-730000000j+q }opp-760000000j-Lq `opp-790000000j/qq 4opp-820000000j05q opp-850000000j2q @opp-880000000j4sq qpmu-a55arm,cortex-a55-pmu {pmu-a78arm,cortex-a78-pmu {psci arm,psci-1.0smctimerarm,armv8-timer @{   soc+ simple-businterrupt-controller@c000000 arm,gic-v3     { ppi-partitionsinterrupt-partition-0 interrupt-partition-1syscon@10000000 mediatek,mt8195-topckgensyscon syscon@10001000#mediatek,mt8195-infracfg_aosyscon  syscon@10003000mediatek,mt8195-pericfgsyscon0 Lpinctrl@10005000mediatek,mt8195-pinctrlPBiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint {audio-default-pinspins-cmd-dat4=>ABCDEFGHIJKdisp-pwm1-default-pinspins1hedp-panel-12v-en-pinspins1`edp-panel-3v3-en-pinspins1eth-default-pinsHpins-ccUVWX)pins-mdioYZ8pins-power[\pins-rxdQRSTpins-txdMNOP)eth-sleep-pinsIpins-ccUVWXpins-mdioYZESpins-rxdQRSTpins-txdMNOPgpio-keys-pinspinsj`8hdmi-vreg-pinslpins-pwrShdmi-pinspins-hotplug mpins-ddc"#) pins-cec!Si2c0-pinsnpins `|i2c1-pinsopins  `|i2c2-pinsrpins  `)i2c6-pinsfpins`mmc0-default-pinsQpins-clkz)mfpins-cmd-dat$~}|{wvuty8)`epins-rstx)`emmc0-uhs-pinsRpins-clkz)mfpins-cmd-dat$~}|{wvuty8)`epins-ds)mfpins-rstx)`emmc1-default-pinsUpins-clko)mfpins-cmd-datnpqrs8)`emmc1-uhs-pinsVpins-clko)mfpins-cmd-datnpqrs8)`emt6360-pinsgpins8`dsi0-vreg-en-pinspins-pwr-en/panel-default-pinspins-rstlpins-en0pcie0-default-pinsapins `pcie0-idle-pinsbpinsSpcie1-default-pinsdpins `disp-pwm0-pins?pins-disp-pwmaspi1-pins@pinsSspi-pinsCpinsStouch-pinsqpins-irq8Spins-resetu3-p0-vbus-default-pinsMpins-vbus?8uart0-pins:pinsbcuart1-pins;pinsdefgsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+3power-domain@8+power-domain@9 mfgalt +!power-domain@10 power-domain@11 power-domain@12 power-domain@13 power-domain@14power-domain@15 @AK" " """"""""""""""""" vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18 +power-domain@168#$#%#&#'#(#)Dvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5 +power-domain@17$$vppsys1vppsys1-0vppsys1-1 power-domain@22 %%%%$wepsys-0wepsys-1wepsys-2wepsys-3 power-domain@23&vdec0-0 +power-domain@24'vdec1-0 power-domain@25(vdec2-0 power-domain@26) venc0-larb +power-domain@27* venc1-larb power-domain@18 +++&vdosys1vdosys1-0vdosys1-1vdosys1-2 +power-domain@19 power-domain@20 power-domain@21Qhdmi_txpower-domain@28,,  img-0img-1 +power-domain@29power-domain@30,-ipeipe-0ipe-1 power-domain@31(.....cam-0cam-1cam-2cam-3cam-4 +power-domain@32 power-domain@33!power-domain@34"power-domain@0 power-domain@1 power-domain@2power-domain@3power-domain@457csi_rx_topcsi_rx_top1power-domain@5/ etherpower-domain@6Xn adspadsp1+ power-domain@7 g"n 2audioaudio1audio2audio3 watchdog@10007000mediatek,mt8195-wdtp8syscon@1000c000"mediatek,mt8195-apmixedsyssyscon timer@10017000,mediatek,mt8195-timermediatek,mt6765-timerp{ 0pwrap@10024000mediatek,mt8195-pwrapsyscon@pwrap{   spiwrap$pmicmediatek,mt6359 /adcmediatek,mt6359-auxadcCaudio-codecmediatek,mt6359-codecUi}regulatorsmediatek,mt6359-regulatorbuck_vs1vs1 5!buck_vgpu11vgpu117 buck_vmodemvmodem*buck_vpuvpu7 buck_vcorevcore  buck_vs2vs2 5jbuck_vpavpa 7,buck_vproc2vproc27L buck_vproc1vproc17L buck_vcore_sshub vcore_sshub7buck_vgpu11_sshub vgpu11_sshub7ldo_vaud18vaud18w@w@ldo_vsim1vsim1/M`ldo_vibrvibrO2Zsldo_vrf12vrf12 ldo_vusbvusb--Nldo_vsram_proc2 vsram_proc2 Lldo_vio18vio18ldo_vcamiovcamioldo_vcn18vcn18w@w@ldo_vfe28vfe28**xldo_vcn13vcn13  ldo_vcn33_1_bt vcn33_1_bt*5gldo_vcn33_1_wifi vcn33_1_wifi*5gldo_vaux18vaux18w@w@ldo_vsram_others vsram_others q q!ldo_vefusevefuseldo_vxo22vxo22w@!ldo_vrfckvrfck`ldo_vrfck_1vrfckjldo_vbif28vbif28**ldo_vio28vio28*2Zldo_vemcvemc,@ 2Zldo_vemc_1vemc&%2ZSldo_vcn33_2_bt vcn33_2_bt2Z2ZBldo_vcn33_2_wifi vcn33_2_wifi*5gldo_va12va12O ldo_va09va09 5Oldo_vrf18vrf18Pldo_vsram_md vsram_md *ldo_vufsvufsTldo_vm18vm18ldo_vbbckvbbckOldo_vsram_proc1 vsram_proc1 Lldo_vsim2vsim2/M`ldo_vsram_others_sshubvsram_others_sshub rtcmediatek,mt6358-rtckeysmediatek,mt6359-keys-Fpower-keyYthhomeYfspmi@10027000mediatek,mt8195-spmi p pmifspmimst  E(pmif_sys_ckpmif_tmr_ckspmimst_clk_mux$+pmic@6mediatek,mt6315-regulatorregulatorsvbuck1Vbcpu7  pmic@7mediatek,mt6315-regulatorregulatorsvbuck1VgpuT 8 infra-iommu@10315000mediatek,mt8195-iommu-infra1PPP{v^mailbox@10320000mediatek,mt8195-gce2@{ mailbox@10330000mediatek,mt8195-gce3@{ scp@10500000mediatek,mt8195-scp0Prpsramcfgl1tcm{okay1mediatek/mt8195/scp.imgclock-controller@10720000mediatek,mt8195-scp_adspr 2dsp@10803000mediatek,mt8195-dsp 0 cfgsram,Xn2#Kadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h3rxtx45okay67mailbox@10816000mediatek,mt8195-adsp-mbox`{4mailbox@10817000mediatek,mt8195-adsp-mboxp{5mt8195-afe-pcm@10890000mediatek,mt8195-audio3{68 audiosysg"#neabcd 22clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodspokay9serial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart{   baudbusokay:defaultserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart{   baudbusokay;defaultserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart{   baudbus disabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart{   baudbus disabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart{   baudbus disabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart{   baudbus disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc  mainC disabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon0 /spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+{ parent-clksel-clkspi-clk disabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap {  <=$lvts-calib-data-1lvts-calib-data-2 svs@1100bc00mediatek,mt8195-svs{ main><(svs-calibration-datat-calibration-data svs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm{3#* 0mainmmokaydefault?pwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm{#+ Nmainmm disabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+{ 3parent-clksel-clkspi-clkokay@default. B@can@0microchip,mcp2518fdAK1- /]BhBspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ { 4parent-clksel-clkspi-clkokayCdefault.spi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+0{ 5parent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+{ <parent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+{ =parent-clksel-clkspi-clk disabledspi@1101d000mediatek,mt8195-spi-slave{ Rspi disabledspi@1101e000mediatek,mt8195-spi-slave{ Sspi disabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a@{wmacirq.axiapbmac_mainptp_refrmii_internalmac_cg0//RST/ RST3 DEFokay rgmii-rxidG ] ''*?defaultsleepHPImdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916Gstmmac-axi-configZjzDrx-queues-configEqueue0queue1queue2queue3tx-queues-configFqueue0 queue1 queue2 queue3 usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3  - > macippc ?+{ / Bsys_ckref_ckmcu_ck JKh Lgokay 4otgdefaultM < LNusb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimac{,-$ / B$sys_ckref_ckmcu_ckdma_ckxhci_ckokayports+port@0endpoint ZOiport@1endpoint ZPjmmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #{  sourcehclksource_cgokaydefaultstate_uhsQPR jO  t      L S T mmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc ${  $sourcehclksource_cgokaydefaultstate_uhsUPV jO     %  W X mmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %{  Isourcehclksource_cg  disabledufshci@11270000mediatek,mt8195-ufshci'#{ Y@ ? @ A 6 7 8 Z ]Xufsufs_aesufs_tickunipro_sysclkunipro_tickunipro_mp_bclkufs_tx_symbolufs_mem_sub@ , : disabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu'{  <=$lvts-calib-data-1lvts-calib-data-2 usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ))> macippc{ Z[./$//$sys_ckref_ckmcu_ckdma_ckxhci_ck Lhhokay LNusb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 *-*> macippc*?+{0//sys_ckref_ckmcu_ck \h Liokay LNusb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimac{1/sys_ckokayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 +-+> macippc+?+{2// sys_ckref_ckmcu_ck ]h Ljokay LNusb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimac{3/ sys_ckokaypcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ pcie-mac{ S8  ]^ g0 V # & + K//pl_250mtl_26mtl_96mtl_32kperi_26mperi_memG _ vpcie-phy3 ` ````okay defaultidleaPbinterrupt-controller`pcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ pcie-mac{ S8$$ $ $  ]^ g( W X Q//pl_250mtl_26mtl_96mtl_32kperi_26mperi_memH [ vpcie-phy3 ` cccc disableddefaultdinterrupt-controllercspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor2{9o// spisfaxi+ disabledefuse@11c10000%mediatek,mt8195-efusemediatek,efuse+usb3-tx-imp@184,1 zusb3-rx-imp@184,2 yusb3-intr@185 xusb3-tx-imp@186,1 wusb3-rx-imp@186,2 vusb3-intr@187 uusb2-intr-p0@188,1 usb2-intr-p1@188,2 usb2-intr-p2@189,1 usb2-intr-p3@189,2 pciephy-rx-ln1@190,1 pciephy-tx-ln1-nmos@190,2 pciephy-tx-ln1-pmos@191,1 pciephy-rx-ln0@191,2 ~pciephy-tx-ln0-nmos@192,1 }pciephy-tx-ln0-pmos@192,2 |pciephy-glb-intr@193 {dp-data@1aclvts1-calib@1bc<lvts2-calib@1d08=svs-calib@580d>socinfo-data1@7a0t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0ref \t-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0ref ]dsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx 2mipi_tx0_pll  okaydsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx 2mipi_tx1_pll   disabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "{e ; maindma+ disabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "{e ; maindma+okay8fdefaultpmic@34mediatek,mt63604 {wIRQBgchargermediatek,mt6360-chg @usb-otg-vbus-regulator usb-otg-vbusC(Xregulatormediatek,mt6360-regulator hbuck1 emi_vdd2  buck2 emi_vddq  hldo1 tp1_p3v02Z2Zpldo2 panel1_p1v8w@w@ldo3vmc_pmuO6Xldo5 vmch_pmu)26Wldo6 mt6360_ldo1  ldo7 emi_vmddr_en  tcpcmediatek,mt6360-tcpc /wPD_IRQBconnectorusb-c-connector USB-C dual  dual sink "d "" ,altmodesdisplayport 8 =Fports+port@0endpoint ZiOport@1endpoint ZjPport@2endpoint Zkti2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "{e ; maindma+ disabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s0 ehdmi-phy@11d5f000mediatek,mt8195-hdmi-phy P   pll_ref26mpll1pll2 2hdmi_txpll   A  Pokaydefaultli2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "{m ; maindma+okay8ndefaulti2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "{m ; maindma+okay8odefaulttouchscreen@5dgoodix,gt9271] / b l xpdefaultqi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "{m ; maindma+okay8rdefaulttypec-mux@48 ite,it5205H s  okayportendpoint Ztki2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 0"{m ; maindma+ disabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c @"{m ; maindma+ disabledclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wP mt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+3okayusb-phy@0  refda_ref Zusb-phy@700 refda_ref uvwintrrx_imptx_imp  [t-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0  refda_ref Jusb-phy@700 refda_ref xyzintrrx_imptx_imp Kphy@11e80000mediatek,mt8195-pcie-physif{|}~Gglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln13 okay_ufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy unipromp  disabledYgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm@0{ wjobmmugpu (3 3 3 3 3 core0core1core2core3core4okay clock-controller@13fbf000mediatek,mt8195-mfgcfg syscon@14000000mediatek,mt8195-vppsys0syscon  "dma-controller@14001000mediatek,mt8195-mdp3-rdma    #3 0"<   7display@14002000mediatek,mt8195-mdp3-fg  "display@14003000mediatek,mt8195-mdp3-stitch0 0"display@14004000mediatek,mt8195-mdp3-hdr@ @""display@14005000mediatek,mt8195-mdp3-aalP{F P" 3display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz` ` %" display@14007000mediatek,mt8195-mdp3-tdshpp p"#display@14008000mediatek,mt8195-mdp3-color{I "$3display@14009000mediatek,mt8195-mdp3-ovl{J "%3 0display@1400a000mediatek,mt8195-mdp3-padding "3display@1400b000mediatek,mt8195-mdp3-tcc "dma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot   +" 03 7mutex@1400f000mediatek,mt8195-vpp-mutex{P "3smi@14010000mediatek,mt8195-smi-sub-common"""apbsmigals0 B3smi@14011000mediatek,mt8195-smi-sub-common"""apbsmigals0 B3smi@14012000mediatek,mt8195-smi-common-vpp  """"apbsmigals0gals13larb@14013000mediatek,mt8195-smi-larb0 O B""apbsmi3iommu@14018000mediatek,mt8195-iommu-vpp8 `{R"bclkv3clock-controller@14e00000mediatek,mt8195-wpesys %clock-controller@14e02000mediatek,mt8195-wpesys_vpp0  clock-controller@14e03000mediatek,mt8195-wpesys_vpp10 larb@14e04000mediatek,mt8195-smi-larb@ O B%%apbsmi3larb@14e05000mediatek,mt8195-smi-larbP O B%%" apbsmigals3syscon@14f00000mediatek,mt8195-vppsys1syscon  $mutex@14f01000mediatek,mt8195-vpp-mutex{{ $'3larb@14f02000mediatek,mt8195-smi-larb  O B$$" apbsmigals3larb@14f03000mediatek,mt8195-smi-larb0 O B$$" apbsmigals3display@14f06000mediatek,mt8195-mdp3-split` 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