i8]D( I] 6kontron,3-5-sbc-i1200mediatek,mt8395mediatek,mt8195 +7Kontron 3.5"-SBC-i1200aliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/mailbox@10320000Y/soc/mailbox@10330000^/soc/hdmi-tx@1c300000d/soc/hdr-engine@1c114000k/soc/mutex@1c016000r/soc/mutex@1c101000y/soc/vpp-merge@1c10c000/soc/vpp-merge@1c10d000/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/mmc@11230000/soc/mmc@11240000/soc/serial@11001200/soc/serial@11001300/soc/serial@11001400/soc/serial@11001500/soc/serial@11001100cpus+cpu@0&cpuarm,cortex-a5526psciDXec3@h4{@@ cpu@100&cpuarm,cortex-a5526psciDXec3@h4{@@ cpu@200&cpuarm,cortex-a5526psciDXec3@h4{@@ cpu@300&cpuarm,cortex-a5526psciDXec3@h4{@@ cpu@400&cpuarm,cortex-a7826psciDXfh{@@ cpu@500&cpuarm,cortex-a7826psciDXfh{@@cpu@600&cpuarm,cortex-a7826psciDXfh{@@cpu@700&cpuarm,cortex-a7826psciDXfh{@@cpu-mapcluster0core0 core1 core2 core3 core4 core5 core6 core7 idle-statespscicpu-retention-larm,idle-state3D2U_eDcpu-retention-barm,idle-state3D-Uecpu-off-larm,idle-state3D7UeHcpu-off-barm,idle-state3D2Uel2-cache0cachev@l2-cache1cachev@l3-cachecachev @dsu-pmu arm,dsu-pmu  faildmic-codec dmic-codec2mt8195-sound disabledfixed-factor-clock-13mfixed-factor-clockclk13m(oscillator-26m fixed-clockXclk26moscillator-32k fixed-clockXclk32kperformance-controller@11bc10mediatek,cpufreq-hw 2 0 opp-table-gpuoperating-points-v2,nopp-3900000007>> hopp-4100000007p> opp-4310000007> opp-47300000071h@> <opp-5150000007F> <opp-5560000007!#> Ҧopp-5980000007#> opp-6400000007&%> opp-6700000007'c> opp-7000000007)'> Lopp-7300000007+> }opp-7600000007-L> `opp-7900000007/q> 4opp-820000000705> opp-85000000072> @opp-88000000074s> qpmu-a55arm,cortex-a55-pmu pmu-a78arm,cortex-a78-pmu psci arm,psci-1.0=smctimerarm,armv8-timer @   soc+ simple-busLSinterrupt-controller@c000000 arm,gic-v3^o  2    ppi-partitionsinterrupt-partition-0 interrupt-partition-1 syscon@10000000 mediatek,mt8195-topckgensyscon2syscon@10001000#mediatek,mt8195-infracfg_aosyscon2syscon@10003000mediatek,mt8195-pericfgsyscon20Apinctrl@10005000mediatek,mt8195-pinctrl2PBiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint^eth-default-pins=pins-txdMNOPpins-rxdQRSTpins-ccUVWXpins-mdioYZpins-power[\pins-reset]pins-interrupt^eth-sleep-pins>pins-txdMNOPpins-ccUXWVpins-rxdQRSTpins-mdioYZ gpio-keys-pinspinsji2c0-pins[pins -:i2c1-pins\pins  -:i2c2-default-pins]pins-bus  -:i2c3-pins^pins-:i2c4-pins_pins-:i2c6-pinsXpins-:mmc0-default-pinsCpins-clkzRfpins-cmd-dat$~}|{wvuty-epins-rstx-emmc0-uhs-pinsDpins-clkzRfpins-cmd-dat$~}|{wvuty-epins-dsRfpins-rstx-emmc1-default-pinsGpins-clkoRfpins-cmd-datnpqrs-emmc1-detect-pinsHpins-insert-nor-default-pinsVpins-ck-io Rpins-cs-pcie0-default-pinsRpins-bus -pcie1-default-pinsUpins-bus -eled-pinspins-power-enkspi0-default-pins4pins-cs-mosi-clk  pins-misoRspi1-default-pins8pins-cs-mosi-clk  pins-misoRuart0-pins/pins-rxc-pins-txbuart1-pins0pins-rxg-pins-txfpins-rtsdpins-ctseuart2-pins1pins-rxD-pins-txCpins-rtsBpins-ctsAuart3-pins2pins-rx-epins-txuart4-pins3pins-rx-pins-txsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd2`power-controller!mediatek,mt8195-power-controller+a+power-domain@82+apower-domain@92 umfgalt+apower-domain@102 apower-domain@112 apower-domain@122 apower-domain@132 apower-domain@142apower-domain@152 @AK   uvppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18+apower-domain@1628$%&'()Duvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5+apower-domain@172uvppsys1vppsys1-0vppsys1-1apower-domain@222 $uwepsys-0wepsys-1wepsys-2wepsys-3apower-domain@232uvdec0-0+apower-domain@242uvdec1-0apower-domain@252 uvdec2-0apower-domain@262! uvenc0-larb+apower-domain@272" uvenc1-larbapower-domain@182 ###&uvdosys1vdosys1-0vdosys1-1vdosys1-2+apower-domain@192apower-domain@202apower-domain@212Quhdmi_txapower-domain@282$$  uimg-0img-1+apower-domain@292apower-domain@302$%uipeipe-0ipe-1apower-domain@312(&&&&&ucam-0cam-1cam-2cam-3cam-4+apower-domain@322 apower-domain@332!apower-domain@342"apower-domain@02apower-domain@12apower-domain@22apower-domain@32apower-domain@4257ucsi_rx_topcsi_rx_top1apower-domain@52' uetherapower-domain@62Xn uadspadsp1+apower-domain@72 g"n2uaudioaudio1audio2audio3awatchdog@10007000mediatek,mt8195-wdt2p.syscon@1000c000"mediatek,mt8195-apmixedsyssyscon2timer@10017000,mediatek,mt8195-timermediatek,mt6765-timer2p (pwrap@10024000mediatek,mt8195-pwrapsyscon2@pwrap uspiwrap$pmicmediatek,mt6359^ adcmediatek,mt6359-auxadcaudio-codecmediatek,mt6359-codecregulatorsmediatek,mt6359-regulatorbuck_vs1 vs1 50!Hdbuck_vgpu11 vgpu1107xH dbuck_vmodem vmodem0x*Hbuck_vpu vpu07xH dbuck_vcore vcore0 xH dbuck_vs2 vs2 50jHdbuck_vpa vpa 07H,buck_vproc2 vproc207xLH dbuck_vproc1 vproc107xLH dbuck_vcore_sshub  vcore_sshub07buck_vgpu11_sshub  vgpu11_sshub07ldo_vaud18 vaud18w@0w@Hldo_vsim1 vsim10/M`ldo_vibr vibrO02Zldo_vrf12 vrf120 dldo_vusb vusb-0-HdBldo_vsram_proc2  vsram_proc2 0xLHdldo_vio18 vio180Hdldo_vcamio vcamio0ldo_vcn18 vcn18w@0w@Hldo_vfe28 vfe28*0*Hxldo_vcn13 vcn13 0 ldo_vcn33_1_bt  vcn33_1_bt*05gldo_vcn33_1_wifi  vcn33_1_wifi*05gldo_vaux18 vaux18w@0w@Hdldo_vsram_others  vsram_others 0xHdldo_vefuse vefuse0ldo_vxo22 vxo22w@0!dldo_vrfck vrfck`0ldo_vrfck_1 vrfck0jldo_vbif28 vbif28*0*Hldo_vio28 vio28*02Zdldo_vemc vemc,@ 02Zldo_vemc_1 vemc&%02ZEldo_vcn33_2_bt  vcn33_2_bt*05gldo_vcn33_2_wifi  vcn33_2_wifi*05gldo_va12 va12O0 dldo_va09 va09 50Oldo_vrf18 vrf180Pldo_vsram_md  vsram_md 0x*Hdldo_vufs vufs0Fldo_vm18 vm180dldo_vbbck vbbck0Odldo_vsram_proc1  vsram_proc1 0xLHdldo_vsim2 vsim20/M`ldo_vsram_others_sshub vsram_others_sshub 0rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi 2p pmifspmimstE(upmif_sys_ckpmif_tmr_ckspmimst_clk_mux$+mt6315@6mediatek,mt6315-regulator2regulatorsvbuck1 Vbcpu07Hxj dmt6315@7mediatek,mt6315-regulator2regulatorsvbuck1 Vgpu h07Hxj doinfra-iommu@10315000mediatek,mt8195-iommu-infra21PPPOmailbox@10320000mediatek,mt8195-gce22@mailbox@10330000mediatek,mt8195-gce23@pscp@10500000mediatek,mt8195-scp02Prpsramcfgl1tcmokay)mediatek/mt8195/scp.imgqclock-controller@10720000mediatek,mt8195-scp_adsp2r*dsp@10803000mediatek,mt8195-dsp 20 cfgsram,Xn*#Kuadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h+rxtx,- disabledmailbox@10816000mediatek,mt8195-adsp-mbox2`,mailbox@10817000mediatek,mt8195-adsp-mbox2p-mt8195-afe-pcm@10890000mediatek,mt8195-audio2+6 . audiosysg"#neabcd2*uclk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp disabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart2  ubaudbusokaydefault-/serial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart2  ubaudbusokaydefault-07serial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart2  ubaudbusokaydefault-17serial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart2  ubaudbusokaydefault-2serial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart2  ubaudbusokaydefault-3serial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart2  ubaudbus disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc2 umainokaysyscon@11003000"mediatek,mt8195-pericfg_aosyscon20'spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+2uparent-clksel-clkspi-clkokaydefault-4Gtpm@0!infineon,slb9670tcg,tpm_tis-spi2[Ithermal-sensor@1100b000mediatek,mt8195-lvts-ap2  m56$ylvts-calib-data-1lvts-calib-data-2svs@1100bc00mediatek,mt8195-svs2umainm75(ysvs-calibration-datat-calibration-data svs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm2+*0umainmm disabledpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm2+Numainmm disabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+23uparent-clksel-clkspi-clkokaydefault-8Gspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+2 4uparent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+205uparent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+2<uparent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+2=uparent-clksel-clkspi-clk disabledspi@1101d000mediatek,mt8195-spi-slave2Ruspi disabledspi@1101e000mediatek,mt8195-spi-slave2Suspi disabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a2@macirq.uaxiapbmac_mainptp_refrmii_internalmac_cg0''RST' RST+9:; okay %rgmii-id.<defaultsleep-=9>Cmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c9162 ^T'd8 v]<stmmac-axi-config9rx-queues-config:queue0queue1queue2queue3tx-queues-config;queue0&2queue1&2queue2&2queue3&2usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3 2 - > macippcL ?+/Busys_ckref_ckmcu_ck@?@E SAgokayjhostrBusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci2mac,-$/B$usys_ckref_ckmcu_ckdma_ckxhci_ckokaymmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc 2#usourcehclksource_cgokaydefaultstate_uhs-C9D_ LE Fmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc 2$$usourcehclksource_cgokaydefaultstate_uhs-GH9G _   ) 6 DI Jmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc 2% Iusourcehclksource_cg  disabledufshci@11270000mediatek,mt8195-ufshci2'#@K@?@A678Z]Xuufsufs_aesufs_tickunipro_sysclkunipro_tickunipro_mp_bclkufs_tx_symbolufs_mem_sub@ K Y disabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu2' m56$ylvts-calib-data-1lvts-calib-data-2usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci 2))> macippc@L./$''$usys_ckref_ckmcu_ckdma_ckxhci_ck SAhEokayrB rusb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 2*-*> macippcL*?+0''usys_ckref_ckmcu_ck@ME SAiokayrBusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci2mac1'usys_ckokayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 2+-+> macippcL+?+2'' usys_ckref_ckmcu_ck@NE SAjokayrBusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci2mac3' usys_ckokaypcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pcie&pci+2/@ pcie-mac 8L  O 0V#&+K'/upl_250mtl_26mtl_96mtl_32kperi_26mperi_memG@P pcie-phy+^ ` QQQQokaydefault-Rinterrupt-controller^Qpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pcie&pci+2/@ pcie-mac 8L$$ $ $  O (WXQ'/upl_250mtl_26mtl_96mtl_32kperi_26mperi_memH@S pcie-phy+^ ` TTTTokaydefault-Uinterrupt-controller^Tspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor229o'' uspisfaxi+okaydefault-Vflash@0jedec,spi-nor2[u  efuse@11c10000%mediatek,mt8195-efusemediatek,efuse2+usb3-tx-imp@184,12 eusb3-rx-imp@184,22 dusb3-intr@1852 cusb3-tx-imp@186,12 busb3-rx-imp@186,22 ausb3-intr@1872 `usb2-intr-p0@188,12 usb2-intr-p1@188,22 usb2-intr-p2@189,12 usb2-intr-p3@189,22 pciephy-rx-ln1@190,12 lpciephy-tx-ln1-nmos@190,22 kpciephy-tx-ln1-pmos@191,12 jpciephy-rx-ln0@191,22 ipciephy-tx-ln0-nmos@192,12 hpciephy-tx-ln0-pmos@192,22 gpciephy-glb-intr@1932 fdp-data@1ac2lvts1-calib@1bc25lvts2-calib@1d0286svs-calib@5802d7socinfo-data1@7a02t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Lokayusb-phy@02uref Mt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Lokayusb-phy@02uref Ndsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx2 mipi_tx0_pll  disableddsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx2 mipi_tx1_pll  disabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2"W; umaindma+ disabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2"W; umaindma+okayX-Xdefaultpmic@34mediatek,mt636024 eIRQB^regulatormediatek,mt6360-regulator Y Y 'Ybuck1  emi_vdd2 '0w@ dbuck2  emi_vddq0  dldo1  mt6360_ldo1O06ldo2  panel1_p1v8w@0w@ldo3 vmc_pmuw@02ZJldo5  vmch_pmu2Z02ZIldo6  mt6360_ldo6 0 ldo7  emi_vmddr_enw@0w@di2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2 "W; umaindma+ disabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s20Whdmi-phy@11d5f000mediatek,mt8195-hdmi-phy2 P  upll_ref26mpll1pll2 hdmi_txpll  7  F disabledi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2"Z; umaindma+okaydefault-[Xi2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2"Z; umaindma+okaydefault-\Xi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2 "Z; umaindma+okaydefault-]Xi2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 20"Z; umaindma+okaydefault-^Xi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c 2@"Z; umaindma+okayX-_defaultclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_w2PZt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+L+okayusb-phy@02  urefda_ref Lusb-phy@7002 urefda_ref m`abyintrrx_imptx_imp St-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Lokayusb-phy@02  urefda_ref ?usb-phy@7002 urefda_ref mcdeyintrrx_imptx_imp @phy@11e80000mediatek,mt8195-pcie-phy2sifmfghijklGyglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1+ okayPufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy2 uunipromp  disabledKgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm2@m0 jobmmugpu Xn(+ + + + + lcore0core1core2core3core4okay oclock-controller@13fbf000mediatek,mt8195-mfgcfg2msyscon@14000000mediatek,mt8195-vppsys0syscon2 pdma-controller@14001000mediatek,mt8195-mdp3-rdma2 p   q+ r<p p ppp display@14002000mediatek,mt8195-mdp3-fg2  p display@14003000mediatek,mt8195-mdp3-stitch20 p0display@14004000mediatek,mt8195-mdp3-hdr2@ p@"display@14005000mediatek,mt8195-mdp3-aal2PF pP +display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz2` p` % display@14007000mediatek,mt8195-mdp3-tdshp2p pp#display@14008000mediatek,mt8195-mdp3-color2I p$+display@14009000mediatek,mt8195-mdp3-ovl2J p%+ rdisplay@1400a000mediatek,mt8195-mdp3-padding2 p+display@1400b000mediatek,mt8195-mdp3-tcc2 pdma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot2 p  + r+ mutex@1400f000mediatek,mt8195-vpp-mutex2P p+smi@14010000mediatek,mt8195-smi-sub-common2uapbsmigals0 s+tsmi@14011000mediatek,mt8195-smi-sub-common2uapbsmigals0 s+smi@14012000mediatek,mt8195-smi-common-vpp2  uapbsmigals0gals1+slarb@14013000mediatek,mt8195-smi-larb20  tuapbsmi+wiommu@14018000mediatek,mt8195-iommu-vpp28 uvwxyz{|}~Rubclk+rclock-controller@14e00000mediatek,mt8195-wpesys2clock-controller@14e02000mediatek,mt8195-wpesys_vpp02 clock-controller@14e03000mediatek,mt8195-wpesys_vpp120larb@14e04000mediatek,mt8195-smi-larb2@  uapbsmi+larb@14e05000mediatek,mt8195-smi-larb2P  s uapbsmigals+ysyscon@14f00000mediatek,mt8195-vppsys1syscon2 p mutex@14f01000mediatek,mt8195-vpp-mutex2{ p '+larb@14f02000mediatek,mt8195-smi-larb2    uapbsmigals+larb@14f03000mediatek,mt8195-smi-larb20  t uapbsmigals+xdisplay@14f06000mediatek,mt8195-mdp3-split2` p `+,+display@14f07000mediatek,mt8195-mdp3-tcc2p p pdma-controller@14f08000mediatek,mt8195-mdp3-rdma2 p   + dma-controller@14f09000mediatek,mt8195-mdp3-rdma2 p    + dma-controller@14f0a000mediatek,mt8195-mdp3-rdma2 p    r+ display@14f0b000mediatek,mt8195-mdp3-fg2 p  display@14f0c000mediatek,mt8195-mdp3-fg2 p  display@14f0d000mediatek,mt8195-mdp3-fg2 p  display@14f0e000mediatek,mt8195-mdp3-hdr2 p display@14f0f000mediatek,mt8195-mdp3-hdr2 p display@14f10000mediatek,mt8195-mdp3-hdr2 p  display@14f11000mediatek,mt8195-mdp3-aal2i p +display@14f12000mediatek,mt8195-mdp3-aal2 j p +display@14f13000mediatek,mt8195-mdp3-aal20k p 0!+display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz2@ p @ display@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz2P p P $display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz2` p ` %display@14f17000mediatek,mt8195-mdp3-tdshp2p p pdisplay@14f18000mediatek,mt8195-mdp3-tdshp2 p (display@14f19000mediatek,mt8195-mdp3-tdshp2 p )display@14f1a000mediatek,mt8195-mdp3-merge2 p +display@14f1b000mediatek,mt8195-mdp3-merge2 p +display@14f1c000mediatek,mt8195-mdp3-color2t p +display@14f1d000mediatek,mt8195-mdp3-color2 p u+display@14f1e000mediatek,mt8195-mdp3-color2v p +display@14f1f000mediatek,mt8195-mdp3-ovl2w p + display@14f20000mediatek,mt8195-mdp3-padding2 p +display@14f21000mediatek,mt8195-mdp3-padding2 p +display@14f22000mediatek,mt8195-mdp3-padding2  p +dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot20 p 0  + dma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot2@ p @  + dma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot2P p P  r+ clock-controller@15000000mediatek,mt8195-imgsys2$larb@15001000mediatek,mt8195-smi-larb2  $$$  uapbsmigals+smi@15002000mediatek,mt8195-smi-sub-common2 $$uapbsmigals0 s+smi@15003000mediatek,mt8195-smi-sub-common20$$$ uapbsmigals0 +clock-controller@15110000 mediatek,mt8195-imgsys1_dip_top2larb@15120000mediatek,mt8195-smi-larb2  $uapbsmi+clock-controller@15130000mediatek,mt8195-imgsys1_dip_nr2clock-controller@15220000mediatek,mt8195-imgsys1_wpe2"larb@15230000mediatek,mt8195-smi-larb2#  $uapbsmi+clock-controller@15330000mediatek,mt8195-ipesys23%larb@15340000mediatek,mt8195-smi-larb24  %%uapbsmi+zclock-controller@16000000mediatek,mt8195-camsys2&larb@16001000mediatek,mt8195-smi-larb2  &&& uapbsmigals+larb@16002000mediatek,mt8195-smi-larb2   &&uapbsmi+{smi@16004000mediatek,mt8195-smi-sub-common2@&&&uapbsmigals0 +smi@16005000mediatek,mt8195-smi-sub-common2P&&uapbsmigals0 s+larb@16012000mediatek,mt8195-smi-larb2   uapbsmi+ |larb@16013000mediatek,mt8195-smi-larb20  uapbsmi+ larb@16014000mediatek,mt8195-smi-larb2@  uapbsmi+!larb@16015000mediatek,mt8195-smi-larb2P  uapbsmi+!clock-controller@1604f000mediatek,mt8195-camsys_rawa2clock-controller@1606f000mediatek,mt8195-camsys_yuva2clock-controller@1608f000mediatek,mt8195-camsys_rawb2clock-controller@160af000mediatek,mt8195-camsys_yuvb2 clock-controller@16140000mediatek,mt8195-camsys_mraw2larb@16141000mediatek,mt8195-smi-larb2  && uapbsmigals+"larb@16142000mediatek,mt8195-smi-larb2   uapbsmi+"clock-controller@17200000mediatek,mt8195-ccusys2 larb@17201000mediatek,mt8195-smi-larb2   uapbsmi+}video-codec@18000000mediatek,mt8195-vcodec-dec q + 2@L`video-codec@2000mediatek,mtk-vcodec-lat-soc2  rr AuselvdeclattopA+video-codec@10000mediatek,mtk-vcodec-lat20  AuselvdeclattopA+video-codec@25000mediatek,mtk-vcodec-core2PP  AuselvdeclattopA+larb@1800d000mediatek,mt8195-smi-larb2  uapbsmi+larb@1800e000mediatek,mt8195-smi-larb2  uapbsmi+clock-controller@1800f000mediatek,mt8195-vdecsys_soc2larb@1802e000mediatek,mt8195-smi-larb2  uapbsmi+clock-controller@1802f000mediatek,mt8195-vdecsys2larb@1803e000mediatek,mt8195-smi-larb2   uapbsmi+clock-controller@1803f000mediatek,mt8195-vdecsys_core12 clock-controller@190f3000mediatek,mt8195-apusys_pll20clock-controller@1a000000mediatek,mt8195-vencsys2!larb@1a010000mediatek,mt8195-smi-larb2  !!uapbsmi+video-codec@1a020000mediatek,mt8195-vcodec-enc2H `abcdvwxyU q! uvenc_sel@++jpeg-decoder@1a040000mediatek,mt8195-jpgdec+0 mnrstu+0Ljpgdec@0,0mediatek,mt8195-jpgdec-hw20 mnrstuW!ujpgdec+jpgdec@0,10000mediatek,mt8195-jpgdec-hw20 mnrstuX!ujpgdec+jpgdec@1,0mediatek,mt8195-jpgdec-hw20 rrrrrr\"ujpgdec+clock-controller@1b000000mediatek,mt8195-vencsys_core12"syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon2  jpeg-encoder@1a030000mediatek,mt8195-jpgenc+ rrrr+0Ljpgenc@0,0mediatek,mt8195-jpgenc-hw2 ghilV!ujpgenc+jpgenc@1,0mediatek,mt8195-jpgenc-hw2 rrrr["ujpgenc+larb@1b010000mediatek,mt8195-smi-larb2  s""  uapbsmigals+~ovl@1c000000mediatek,mt8195-disp-ovl2|+  ports+port@02endpointport@12endpoint rdma@1c002000mediatek,mt8195-disp-rdma2 ~+   ports+port@02endpoint port@12endpoint color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color20+ 0ports+port@02endpoint port@12endpoint ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr2@+ @ports+port@02endpoint port@12endpoint aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aal2P+ Pports+port@02endpoint port@12endpoint gamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma2`+ `ports+port@02endpoint port@12endpoint dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-dither2p+  pports+port@02endpoint port@12endpointdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsi2+*uenginedigitalhs@ dphy disableddsc@1c009000mediatek,mt8195-disp-dsc2+ dsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi2 ++uenginedigitalhs@ dphy disabledmerge@1c014000mediatek,mt8195-disp-merge2@+ @dp-intf@1c015000mediatek,mt8195-dp-intf2P+,upixelenginepll disabledmutex@1c016000mediatek,mt8195-disp-mutex2`+ ` Ularb@1c018000mediatek,mt8195-smi-larb2  ((  uapbsmigals+larb@1c019000mediatek,mt8195-smi-larb2  s(  uapbsmigals+usyscon@1c100000mediatek,mt8195-vdosys1syscon2  #smi@1c01b000mediatek,mt8195-smi-common-vdo2 %&)$uapbsmigals0gals1+iommu@1c01f000mediatek,mt8195-iommu-vdo28 'ubclk+mutex@1c101000mediatek,mt8195-disp-mutex2+#  larb@1c102000mediatek,mt8195-smi-larb2   ### uapbsmigals+larb@1c103000mediatek,mt8195-smi-larb20  s##  uapbsmigals+vdma-controller@1c104000mediatek,mt8195-vdo1-rdma2@#+ @ @ dma-controller@1c105000mediatek,mt8195-vdo1-rdma2P#+ r` P dma-controller@1c106000mediatek,mt8195-vdo1-rdma2`#+ A ` dma-controller@1c107000mediatek,mt8195-vdo1-rdma2p#+ ra p dma-controller@1c108000mediatek,mt8195-vdo1-rdma2#+ B  dma-controller@1c109000mediatek,mt8195-vdo1-rdma2#+ rb  dma-controller@1c10a000mediatek,mt8195-vdo1-rdma2#+ C  dma-controller@1c10b000mediatek,mt8195-vdo1-rdma2#+ rc  vpp-merge@1c10c000mediatek,mt8195-disp-merge2# #umergemerge_async+   #vpp-merge@1c10d000mediatek,mt8195-disp-merge2# #umergemerge_async+   #vpp-merge@1c10e000mediatek,mt8195-disp-merge2# #umergemerge_async+   #vpp-merge@1c10f000mediatek,mt8195-disp-merge2# #umergemerge_async+   #vpp-merge@1c110000mediatek,mt8195-disp-merge2# #umergemerge_async+  ' #dpi@1c112000mediatek,mt8195-dpi2 #-##2upixelenginepll+ # disabledports+port@02endpointport@12endpointdp-intf@1c113000mediatek,mt8195-dp-intf20+#/#upixelenginepll disabledhdr-engine@1c114000mediatek,mt8195-disp-ethdrp2@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp @Pph#%# ###!#$#"#1#&#'#(#)#*umixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top+ rdre( #3#4#5#6#7Evdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asynchdmi-tx@1c300000mediatek,mt8195-hdmi-tx20 QLM,ubushdcphdcp24mhdmi-splitL+@ hdmi disabledi2cmediatek,mt8195-hdmi-ddcports+port@02endpointport@12endpointedp-tx@1c500000mediatek,mt8195-edp-tx2Pmydp_calibration_data+ > disableddp-tx@1c600000mediatek,mt8195-dp-tx2`mydp_calibration_data+ > disabledthermal-zonescpu0-thermal O ] stripstrip-alert L -passivetrip-crit   -criticalcooling-mapsmap0 0 cpu1-thermal O ] stripstrip-alert L -passivetrip-crit   -criticalcooling-mapsmap0 0 cpu2-thermal O ] stripstrip-alert L -passivetrip-crit   -criticalcooling-mapsmap0 0 cpu3-thermal O ] stripstrip-alert L -passivetrip-crit   -criticalcooling-mapsmap0 0 cpu4-thermal O ] stripstrip-alert L -passivetrip-crit   -criticalcooling-mapsmap0 0 cpu5-thermal O ] stripstrip-alert L -passivetrip-crit   -criticalcooling-mapsmap0 0 cpu6-thermal O ] stripstrip-alert L -passivetrip-crit   -criticalcooling-mapsmap0 0 cpu7-thermal O ] stripstrip-alert L -passivetrip-crit   -criticalcooling-mapsmap0 0 vpu0-thermal O ] stripstrip-alert L -passivetrip-crit   -criticalvpu1-thermal O ] s tripstrip-alert L -passivetrip-crit   -criticalgpu-thermal O ] s tripstrip-alert L -passivetrip-crit   -criticalgpu1-thermal O ] s tripstrip-alert L -passivetrip-crit   -criticalvdec-thermal O ] s tripstrip-alert L -passivetrip-crit   -criticalimg-thermal O ] s tripstrip-alert L -passivetrip-crit   -criticalinfra-thermal O ] stripstrip-alert L -passivetrip-crit   -criticalcam0-thermal O ] stripstrip-alert L -passivetrip-crit   -criticalcam1-thermal O ] stripstrip-alert L -passivetrip-crit   -criticalcpu-thermal O ] stripstrip-alert L -passivetrip-crit s  -criticalpcb-top-thermal O ] stripstrip-alert $ -passivetrip-crit L  -criticalpcb-bottom-thermal O ] stripstrip-alert $ -passivetrip-crit L  -criticalchosen serial0:115200n8firmwareopteelinaro,optee-tz=smcgpio-keys gpio-keysdefault-key-0 |j volume_up sE leds gpio-ledsdefault-led-0 |k keep power memory@40000000&memory2@regulator-vsysregulator-fixed vsysd LK@0LK@Yreserved-memory+Loptee@43200000 2C memory@50000000shared-dma-pool2P )memory@53000000shared-dma-pool2S@memory@54600000 2T` memory@60000000shared-dma-pool2` memory@62000000shared-dma-pool2b@thermal-sensor-0generic-adc-thermal  sensor-channel 0X^hnxj'{:N aou0/@Pu`aQpD$980L)_#s(8H  X "6hIthermal-sensor-1generic-adc-thermal  sensor-channel 0X^hnxj'{:N aou0/@Pu`aQpD$980L)_#s(8H  X "6hIthermal-sensor-2generic-adc-thermal  sensor-channel 0X^hnxj'{:N aou0/@Pu`aQpD$980L)_#s(8H  X "6hI compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1gce0gce1hdmi0ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7mmc0mmc1serial0serial1serial2serial3serial4device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxdrive-strengthinput-enableoutput-highinput-disablebias-disablebias-pull-updrive-strength-microampbias-pull-down#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#sound-dai-cellsinterrupts-extended#io-channel-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#iommu-cells#mbox-cellsmemory-regionfirmware-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-namespinctrl-0uart-has-rtsctsmediatek,pad-selectspi-max-frequencynvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlepinctrl-1mediatek,mac-wolreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphyswakeup-sourcemediatek,syscon-wakeupdr_modevusb33-supplybus-widthhs400-ds-delaycap-mmc-highspeedcap-mmc-hw-resetmmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablevmmc-supplyvqmmc-supplycd-gpioscap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmcfreq-table-hzmediatek,ufs-disable-mcqmediatek,u3p-dis-mskbus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapspi-rx-bus-widthspi-tx-bus-widthbits#phy-cellsLDO_VIN1-supplyLDO_VIN2-supplyLDO_VIN3-supplymediatek,ibiasmediatek,ibias_upoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathlabellinux,codedebounce-intervaldefault-statefunctioncolorregulator-boot-onno-mapio-channelsio-channel-namestemperature-lookup-table