v8o(o)tronsmart,orion-r68-metarockchip,rk3368 +7Rockchip Orion R68aliases=/pinctrl/gpio@ff750000C/pinctrl/gpio@ff780000I/pinctrl/gpio@ff790000O/pinctrl/gpio@ff7a0000U/i2c@ff650000Z/i2c@ff660000_/i2c@ff140000d/i2c@ff150000i/i2c@ff160000n/i2c@ff170000s/serial@ff180000{/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/ethernet@ff290000/mmc@ff0c0000/mmc@ff0f0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53pscicpu@2cpuarm,cortex-a53pscicpu@3cpuarm,cortex-a53psci cpu@100cpuarm,cortex-a53pscicpu@101cpuarm,cortex-a53pscicpu@102cpuarm,cortex-a53pscicpu@103cpuarm,cortex-a53pscidisplay-subsystemrockchip,display-subsystem  disabledarm-pmuarm,cortex-a53-pmu`pqrstuvw  psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clock"n62xin24mEGmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @R `  D r vgbiuciuciu-driveciu-samples  ~ resetokay"default mmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @Rр `  E s wgbiuciuciu-driveciu-samples !~ reset disabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@Rр `  G u ygbiuciuciu-driveciu-samples #~ resetokay *default saradc@ff100000rockchip,saradc $8` I [gsaradcapb_pclk~ W saradc-apbokayJspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi` A Rgspiclkapb_pclk ,default+ disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi` B Sgspiclkapb_pclk -default+ disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi` C Tgspiclkapb_pclk )default !"+ disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >+gi2c` Ndefault# disabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?+gi2c` Odefault$ disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @+gi2c` Pdefault% disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A+gi2c` Qdefault& disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uart"n6` M Ugbaudclkapb_pclk 7V` disabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uart"n6` N Vgbaudclkapb_pclk 8V` disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uart"n6` P Xgbaudclkapb_pclk :V` disabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uart"n6` Q Ygbaudclkapb_pclk ;V`okaydefault'dma-controller@ff250000arm,pl330arm,primecell%@mx`  gapb_pclkthermal-zonescpu-thermald(tripscpu_alert0$passive)cpu_alert18passive*cpu_crits criticalcooling-mapsmap0)0map1*0 gpu-thermald(tripsgpu_alert08passive+gpu_crit8 criticalcooling-mapsmap0+0tsadc@ff280000rockchip,rk3368-tsadc( %` H Zgtsadcapb_pclk~  tsadc-apbinitdefaultsleep, -,3s disabled(ethernet@ff290000rockchip,rk3368-gmac) JmacirqZ.8`  f g c ]Mgstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac~ B stmmacethokayg w/input0rgmiidefault1 2  'B@0mdiosnps,dwmac-mdio+usb@ff500000 generic-ehciP ` okayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2X ` gotgotg%@@ okaydma-controller@ff600000arm,pl330arm,primecell`@mx`  gapb_pclkHi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2ce` Lgi2c <default3+okaysyr827@40silergy,syr827@4Qvdd_cpu`,| 4`@4rtc@51haoyu,hym8563QE2xin32ki2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =+gi2c` Mdefault5 disabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault6` _ disabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault7` _ disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh ` _ disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh0default8` _ disabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uarti` O Wgbaudclkapb_pclk 9default9V`okaymbox@ff6b0000rockchip,rk3368-mailboxk0` E gpclk_mailbox disabledpower-management@ff730000&rockchip,rk3368-pmusysconsimple-mfdspower-controller!rockchip,rk3368-power-controller +Kpower-domain@12 `       c h g n o r s f d d h i l k j n m$:;<=>?@AB power-domain@14 `  o p CDE power-domain@16` @F syscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfdsSio-domains&rockchip,rk3368-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-mode$+RB7RBERB URBclock-controller@ff760000rockchip,rk3368-cruv`Ggxin24mZ.Ea syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw.io-domains"rockchip,rk3368-io-voltage-domain disabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt` p Ookaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  B` a U gpclktimerspdif@ff880000rockchip,rk3368-spdif 6` S  gmclkhclknHstxdefaultI} disabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (gi2s_clki2s_hclk` T nHHstxrx} disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5gi2s_clki2s_hclk` R nHHstxrxdefaultJ} disablediommu@ff900800rockchip,iommu `  gaclkifaceK  disablediommu@ff914000rockchip,iommu @P `  gaclkifaceK  disabledvop@ff930000rockchip,rk3368-vop  g ׄ ` gaclk_vopdclk_vophclk_vopLK ~ d e f axiahbdclk disabledport+ endpoint@0MPendpoint@1NRiommu@ff930300rockchip,iommu `  gaclkifaceK  disabledLdsi@ff960000*rockchip,rk3368-mipi-dsisnps,dw-mipi-dsi@ ` dgpclkOdphyK ~ sapbZ. disabledports+port@0endpointPMport@1phy@ff968000rockchip,rk3368-dsi-dphy@` s grefpclk~ rapb disabledOhdmi@ff980000rockchip,rk3368-dw-hdmi g` h m ngiahbisfrcecdefaultQK `Z. disabledports+port@0endpointRNport@1iommu@ff9a0440rockchip,iommu @@@  `  gaclkiface disablediommu@ff9a0800rockchip,iommu  `  gaclkiface disabledqos@ffad0000rockchip,rk3368-qossyscon :qos@ffad0080rockchip,rk3368-qossyscon ;qos@ffad0100rockchip,rk3368-qossyscon <qos@ffad0180rockchip,rk3368-qossyscon =qos@ffad0200rockchip,rk3368-qossyscon >qos@ffad0280rockchip,rk3368-qossyscon ?qos@ffad0300rockchip,rk3368-qossyscon @qos@ffad0380rockchip,rk3368-qossyscon Aqos@ffad0400rockchip,rk3368-qossyscon Bqos@ffae0000rockchip,rk3368-qossyscon Cqos@ffae0100rockchip,rk3368-qossyscon Dqos@ffae0180rockchip,rk3368-qossyscon Eqos@ffaf0000rockchip,rk3368-qossyscon Fefuse@ffb00000rockchip,rk3368-efuse +` q gpclk_efusecpu-leakage@17temp-adjust@1finterrupt-controller@ffb71000 arm,gic-400 @ @ `   pinctrlrockchip,rk3368-pinctrlZ.0S+=gpio@ff750000rockchip,gpio-banku` @ QDT ]gpio@ff780000rockchip,gpio-bankx` A RDT gpio@ff790000rockchip,gpio-banky` B SDT [gpio@ff7a0000rockchip,gpio-bankz` C TDT 2pcfg-pull-up`Vpcfg-pull-downmYpcfg-pull-none|Wpcfg-pull-none-12ma| Xemmcemmc-clkTemmc-cmdUemmc-pwrVemmc-bus1Vemmc-bus4@VVVVemmc-bus8UUUUUUUUemmc-resetWZgmacrgmii-pinsWWWX X XXX XWWWWWW1rmii-pinsWWWX X XWWWWhdmihdmi-i2c-xfer WWQi2c0i2c0-xfer WW3i2c1i2c1-xfer WW5i2c2i2c2-xfer  WW#i2c3i2c3-xfer WW$i2c4i2c4-xfer WW%i2c5i2c5-xfer WW&i2si2s-8ch-bus W WWWWWWWWJpwm0pwm0-pinW6pwm1pwm1-pinW7pwm3pwm3-pinW8sdio0sdio0-bus1Vsdio0-bus4@VVVVsdio0-cmdVsdio0-clkWsdio0-cdVsdio0-wpVsdio0-pwrVsdio0-bkpwrVsdio0-intVsdmmcsdmmc-clk T sdmmc-cmd U sdmmc-cd Usdmmc-bus1Usdmmc-bus4@UUUUspdifspdif-txWIspi0spi0-clkVspi0-cs0Vspi0-cs1Vspi0-txVspi0-rxVspi1spi1-clkVspi1-cs0Vspi1-cs1Vspi1-rxVspi1-txVspi2spi2-clk Vspi2-cs0 V"spi2-rx V!spi2-tx V tsadcotp-pinW,otp-outW-uart0uart0-xfer VWuart0-ctsWuart0-rtsWuart1uart1-xfer VWuart1-ctsWuart1-rtsWuart2uart2-xfer VW9uart3uart3-xfer VWuart3-ctsWuart3-rtsWuart4uart4-xfer VW'uart4-ctsWuart4-rtsWpcfg-pull-none-drv-8ma|Tpcfg-pull-up-drv-8ma`Ukeyspwr-keyY\ledsstby-pwren W_led-ctlW^usbhost-vbus-drvW`chosenserial2:115200n8memory@0memoryemmc-pwrseqmmc-pwrseq-emmcZdefault [external-gmac-clock fixed-clockE"sY@ 2ext_gmac/gpio-keys gpio-keysdefault\key-power ] GPIO Powertgpio-leds gpio-ledsled-0 2orion:red:leddefault^onled-1 ] orion:blue:leddefault_offregulator-vcc18regulator-fixedQvcc_18|w@w@4regulator-vcc-hostregulator-fixed ]default` Qvcc_host4regulator-vcc-ioregulator-fixedQvcc_io|2Z2Z4aregulator-vcc-lanregulator-fixedQvcc_lan|2Z2Za0regulator-vcc-sdregulator-fixedQvcc_sd 2 |w@2Zaregulator-vcc-sysregulator-fixedQvcc_sys|LK@LK@4regulator-vcc-io-sdregulator-fixed Qvccio_sd|w@2Zaregulator-vccio-wlregulator-fixed Qvccio_wl|2Z2Zaregulator-vdd-10regulator-fixedQvdd_10|B@B@4 compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleportsstatusinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesbus-widthcap-sd-highspeedcard-detect-delaypinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-pwrseqmmc-hs200-1_2vmmc-hs200-1_8vnon-removable#io-channel-cellsvref-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supply#pwm-cells#mbox-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#sound-dai-cellspower-domains#iommu-cellsrockchip,disable-mmu-resetassigned-clock-ratesiommusremote-endpointphysphy-names#phy-cellsinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathreset-gpioswakeup-sourcelabellinux,codedefault-state