t78m(l.rockchip,px5-evbrockchip,px5rockchip,rk3368 +7Rockchip PX5 EVBaliases=/pinctrl/gpio@ff750000C/pinctrl/gpio@ff780000I/pinctrl/gpio@ff790000O/pinctrl/gpio@ff7a0000U/i2c@ff650000Z/i2c@ff660000_/i2c@ff140000d/i2c@ff150000i/i2c@ff160000n/i2c@ff170000s/serial@ff180000{/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/mmc@ff0c0000/mmc@ff0f0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53pscicpu@2cpuarm,cortex-a53pscicpu@3cpuarm,cortex-a53psci cpu@100cpuarm,cortex-a53pscicpu@101cpuarm,cortex-a53pscicpu@102cpuarm,cortex-a53pscicpu@103cpuarm,cortex-a53pscidisplay-subsystemrockchip,display-subsystem  disabledarm-pmuarm,cortex-a53-pmu`pqrstuvw  psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clockn6(xin24m;Gmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @Hр V  D r v]biuciuciu-driveciu-samplei t {resetokaydefault Z*mmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @Hр V  E s w]biuciuciu-driveciu-samplei !t {reset disabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@Hр V  G u y]biuciuciu-driveciu-samplei #t {resetokayр7FLdefault *saradc@ff100000rockchip,saradc $ZV I []saradcapb_pclkt W {saradc-apb disabledspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spiV A R]spiclkapb_pclk ,default+ disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spiV B S]spiclkapb_pclk -default+ disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spiV C T]spiclkapb_pclk )default !"+ disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >+]i2cV Ndefault#okaytouchscreen@40silead,gsl1680@ $ l$x i2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?+]i2cV Odefault% disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @+]i2cV Pdefault& disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A+]i2cV Qdefault' disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartn6V M U]baudclkapb_pclk 7 disabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartn6V N V]baudclkapb_pclk 8 disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartn6V P X]baudclkapb_pclk : disabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartn6V Q Y]baudclkapb_pclk ;okaydma-controller@ff250000arm,pl330arm,primecell%@V  ]apb_pclkthermal-zonescpu-thermald)(tripscpu_alert09$Epassive)cpu_alert198Epassive*cpu_crit9sE criticalcooling-mapsmap0P)0Umap1P*0U gpu-thermald)(tripsgpu_alert098Epassive+gpu_crit98E criticalcooling-mapsmap0P+0Utsadc@ff280000rockchip,rk3368-tsadc( %V H Z]tsadcapb_pclkt  {tsadc-apbinitdefaultsleep,d-n,xsokay(ethernet@ff290000rockchip,rk3368-gmac) macirq.8V  f g c ]M]stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mact B {stmmaceth disabledmdiosnps,dwmac-mdio+usb@ff500000 generic-ehciP V okayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2X V ]otgotg@@ okaydma-controller@ff600000arm,pl330arm,primecell`@V  ]apb_pclkHi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2ceV L]i2c <default/+okaypmic@1brockchip,rk808 0default12,D3P3\3h3t33333(xin32krk808-clkout2;regulatorsDCDC_REG1 ` `!vdd_cpuDCDC_REG2 ` `!vdd_logDCDC_REG3!vcc_ddrDCDC_REG42Z 2Z!vcc_ioLDO_REG1w@ w@ !vcc18_flashLDO_REG22Z 2Z!vcca_33LDO_REG3B@ B@!vdd_10LDO_REG42Z 2Z!avdd_33LDO_REG5w@ 2Z !vccio_sdLDO_REG6B@ B@ !vdd10_lcdLDO_REG7w@ w@!vcc_18LDO_REG8w@ w@ !vcc18_lcdSWITCH_REG1!vcc_sdSWITCH_REG2 !vcc33_lcdi2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =+]i2cV Mdefault4okayaccelerometer@18 bosch,bma250 5pwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmh0default6V _ disabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmh0default7V _ disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh 0V _ disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh00default8V _ disabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uartiV O W]baudclkapb_pclk 9default9 disabledmbox@ff6b0000rockchip,rk3368-mailboxk0V E ]pclk_mailbox; disabledpower-management@ff730000&rockchip,rk3368-pmusysconsimple-mfdspower-controller!rockchip,rk3368-power-controllerG+Kpower-domain@12 V       c h g n o r s f d d h i l k j n m$[:;<=>?@ABGpower-domain@14 V  o p [CDEGpower-domain@16V @[FGsyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfdsSio-domains&rockchip,rk3368-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-modebiRBuRBRB RBclock-controller@ff760000rockchip,rk3368-cruvVG]xin24m.; syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw.io-domains"rockchip,rk3368-io-voltage-domain disabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdtV p Ookaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  BV a U ]pclktimerspdif@ff880000rockchip,rk3368-spdif 6V S  ]mclkhclkHtxdefaultI disabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (]i2s_clki2s_hclkV T HHtxrx disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5]i2s_clki2s_hclkV R HHtxrxdefaultJ disablediommu@ff900800rockchip,iommu V  ]aclkifaceK  disablediommu@ff914000rockchip,iommu @P V  ]aclkifaceK  disabledvop@ff930000rockchip,rk3368-vop   ׄ V ]aclk_vopdclk_vophclk_vop'LK t d e f {axiahbdclk disabledport+ endpoint@0.MPendpoint@1.NRiommu@ff930300rockchip,iommu V  ]aclkifaceK  disabledLdsi@ff960000*rockchip,rk3368-mipi-dsisnps,dw-mipi-dsi@ V d]pclk>OCdphyK t s{apb. disabledports+port@0endpoint.PMport@1phy@ff968000rockchip,rk3368-dsi-dphy@V s ]refpclkMt r{apb disabledOhdmi@ff980000rockchip,rk3368-dw-hdmi gV h m n]iahbisfrcecdefaultQK . disabledports+port@0endpoint.RNport@1iommu@ff9a0440rockchip,iommu @@@ V  ]aclkiface disablediommu@ff9a0800rockchip,iommu  V  ]aclkiface disabledqos@ffad0000rockchip,rk3368-qossyscon :qos@ffad0080rockchip,rk3368-qossyscon ;qos@ffad0100rockchip,rk3368-qossyscon <qos@ffad0180rockchip,rk3368-qossyscon =qos@ffad0200rockchip,rk3368-qossyscon >qos@ffad0280rockchip,rk3368-qossyscon ?qos@ffad0300rockchip,rk3368-qossyscon @qos@ffad0380rockchip,rk3368-qossyscon Aqos@ffad0400rockchip,rk3368-qossyscon Bqos@ffae0000rockchip,rk3368-qossyscon Cqos@ffae0100rockchip,rk3368-qossyscon Dqos@ffae0180rockchip,rk3368-qossyscon Eqos@ffaf0000rockchip,rk3368-qossyscon Fefuse@ffb00000rockchip,rk3368-efuse +V q ]pclk_efusecpu-leakage@17temp-adjust@1finterrupt-controller@ffb71000 arm,gic-400Xm@ @ `   pinctrlrockchip,rk3368-pinctrl.~S+gpio@ff750000rockchip,gpio-bankuV @ QXm0gpio@ff780000rockchip,gpio-bankxV A RXmgpio@ff790000rockchip,gpio-bankyV B SXm5gpio@ff7a0000rockchip,gpio-bankzV C TXm$pcfg-pull-upUpcfg-pull-downpcfg-pull-noneTpcfg-pull-none-12ma Vemmcemmc-clkTemmc-cmdUemmc-pwrUemmc-bus1Uemmc-bus4@UUUUemmc-bus8UUUUUUUUgmacrgmii-pinsTTTV V VVV VTTTTTTrmii-pinsTTTV V VTTTThdmihdmi-i2c-xfer TTQi2c0i2c0-xfer TT/i2c1i2c1-xfer TT4i2c2i2c2-xfer  TT#i2c3i2c3-xfer TT%i2c4i2c4-xfer TT&i2c5i2c5-xfer TT'i2si2s-8ch-bus T TTTTTTTTJpwm0pwm0-pinT6pwm1pwm1-pinT7pwm3pwm3-pinT8sdio0sdio0-bus1Usdio0-bus4@UUUUsdio0-cmdUsdio0-clkTsdio0-cdUsdio0-wpUsdio0-pwrUsdio0-bkpwrUsdio0-intUsdmmcsdmmc-clk T sdmmc-cmd U sdmmc-cd Usdmmc-bus1Usdmmc-bus4@UUUUspdifspdif-txTIspi0spi0-clkUspi0-cs0Uspi0-cs1Uspi0-txUspi0-rxUspi1spi1-clkUspi1-cs0Uspi1-cs1Uspi1-rxUspi1-txUspi2spi2-clk Uspi2-cs0 U"spi2-rx U!spi2-tx U tsadcotp-pinT,otp-outT-uart0uart0-xfer UTuart0-ctsTuart0-rtsTuart1uart1-xfer UTuart1-ctsTuart1-rtsTuart2uart2-xfer UT9uart3uart3-xfer UTuart3-ctsTuart3-rtsTuart4uart4-xfer UTuart4-ctsTuart4-rtsTkeyspwr-keyTWpmicpmic-sleepT2pmic-intU1chosenserial4:115200n8memory@0@memorygpio-keys gpio-keysdefaultWkey-power r0 GPIO Powertregulator-vcc-sysregulator-fixed!vcc_sysLK@ LK@3 compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleportsstatusinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delayno-sdiosd-uhs-sdr12sd-uhs-sdr25pinctrl-namespinctrl-0rockchip,default-sample-phasevmmc-supplyvqmmc-supplymmc-hs200-1_8vno-sdnon-removable#io-channel-cellspower-gpiostouchscreen-size-xtouchscreen-size-ysilead,max-fingersreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizesystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-name#pwm-cells#mbox-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#sound-dai-cellspower-domains#iommu-cellsrockchip,disable-mmu-resetassigned-clocksassigned-clock-ratesiommusremote-endpointphysphy-names#phy-cellsinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathlabellinux,codewakeup-source