m8~(~Xarmsom,sige1rockchip,rk3528 + 7ArmSoM Sige1aliases=/pinctrl/gpio@ff610000C/pinctrl/gpio@ffaf0000I/pinctrl/gpio@ffb00000O/pinctrl/gpio@ffb10000U/pinctrl/gpio@ffb20000[/soc/ethernet@ffbe0000e/soc/i2c@ffa50000j/soc/mmc@ffbf0000o/soc/mmc@ffc30000t/soc/mmc@ffc10000y/soc/serial@ff9f0000/soc/serial@ffa00000cpus+cpu-mapcluster0core0core1core2core3cpu@0arm,cortex-a53cpupscicpu@1arm,cortex-a53cpupscicpu@2arm,cortex-a53cpupscicpu@3arm,cortex-a53cpupscifirmwarescmi arm,scmi-smcق +protocol@14opp-table-cpuoperating-points-v2opp-1200000000G  Y Y@opp-1416000000Tfr  HH@opp-1608000000_"  @opp-1800000000kI  ԼԼ@opp-2016000000x)  @opp-table-gpuoperating-points-v22opp-300000000  Y YB@(opp-500000000e  Y YB@opp-600000000#F  Y YB@opp-700000000)'  B@opp-800000000/  ~~B@pinctrlrockchip,rk3528-pinctrl4 +A gpio@ff610000rockchip,gpio-banka r s HGSco {gpio@ffaf0000rockchip,gpio-bank  HISco { :gpio@ffb00000rockchip,gpio-bank $ % HKSco @ { gpio@ffb10000rockchip,gpio-bank  HLSco ` { 9gpio@ffb20000rockchip,gpio-bank  HNSco { pcfg-pull-uppcfg-pull-downpcfg-pull-nonepcfg-pull-none-drv-level-0pcfg-pull-none-drv-level-2pcfg-pull-up-drv-level-2pcfg-pull-none-smtarmclkclkm1-32k-outxemmcemmc-bus8Xemmc-clkYemmc-cmdZemmc-strb[ethfephyfephym0-led-linkKfephym0-led-spdLfspigpuhdmihsmi2c0i2c0m0-xfer ?i2c1i2c2i2c2m1-xfer Ai2c3i2c4i2c4-xfer Bi2c5i2c6i2c7i2c7-xfer Ci2s0i2s1jtagpciepcie20-perstnpdmpmupwm0pwm1pwm2pwm2m0-pinsDpwm3pwm3m0-pinsEpwm4pwm5pwm6pwm7pwrrefrgmiirgmii-miim Rrgmii-rx-bus20Trgmii-tx-bus20Srgmii-rgmii-clk Urgmii-rgmii-bus@ Vscrsdio0sdio0-bus4@\sdio0-clk]sdio0-cmd^sdio1sdio1-bus4@ asdio1-clkbsdio1-cmdcsdmmcsdmmc-bus4@dsdmmc-clkesdmmc-cmdfsdmmc-detgsdmmc-vol-ctrl-htsdmmc-pwren-lpspdifspi0spi1tsi0tsi1uart0uart0m0-xfer 5uart1uart2uart2m1-xfer  6uart2m1-ctsn 7uart2m1-rtsn 8uart3uart4uart5uart6uart7bluetoothbt-reg-on-h;bt-wake-host-h<host-wake-bt-h=ethernetgmac1-rstn-l Wledsg-led lr-led mrtcrtc-int-l@usbusb20-host1-drv-h qusb20-host2-drv-hrusb20-otg0-drv-h swifiwifi-reg-on-hwwifi-wake-host-h`psciarm,psci-1.0arm,psci-0.2smcreserved-memory+Ashmem@10f000arm,scmi-shmem  timerarm,armv8-timer0H   clock-xin24m fixed-clockn6!xin24mclock-gmac50m fixed-clock!gmac0soc simple-busAD+pcie@fe000000*rockchip,rk3528-pcierockchip,rk3568-pcie0@O4dbiapbconfig>( $Haclk_mstaclk_slvaclk_dbipclkauxpciHHTsyspmcmsglegacyerrmsid`w pcie-phy TA @ d b pwrpipe+okaydefault legacy-interrupt-controller{  Hinterrupt-controller@fed01000 arm,gic-400@ @ `  H {qos@ff200000rockchip,rk3528-qossyscon qos@ff200080rockchip,rk3528-qossyscon qos@ff200100rockchip,rk3528-qossyscon  qos@ff200200rockchip,rk3528-qossyscon  qos@ff200280rockchip,rk3528-qossyscon  qos@ff200300rockchip,rk3528-qossyscon  qos@ff200380rockchip,rk3528-qossyscon  qos@ff210000rockchip,rk3528-qossyscon! qos@ff210080rockchip,rk3528-qossyscon! qos@ff220000rockchip,rk3528-qossyscon" qos@ff220080rockchip,rk3528-qossyscon" qos@ff240000rockchip,rk3528-qossyscon$ qos@ff250000rockchip,rk3528-qossyscon% qos@ff260000rockchip,rk3528-qossyscon& qos@ff270000rockchip,rk3528-qossyscon'  qos@ff270080rockchip,rk3528-qossyscon' !qos@ff270100rockchip,rk3528-qossyscon' "qos@ff270200rockchip,rk3528-qossyscon' #qos@ff270280rockchip,rk3528-qossyscon' $qos@ff270300rockchip,rk3528-qossyscon' %qos@ff270380rockchip,rk3528-qossyscon' &qos@ff270480rockchip,rk3528-qossyscon' 'qos@ff270500rockchip,rk3528-qossyscon' (qos@ff280000rockchip,rk3528-qossyscon( )qos@ff280080rockchip,rk3528-qossyscon( *qos@ff280100rockchip,rk3528-qossyscon( +qos@ff280180rockchip,rk3528-qossyscon( ,qos@ff280200rockchip,rk3528-qossyscon( -qos@ff280280rockchip,rk3528-qossyscon( .qos@ff280300rockchip,rk3528-qossyscon( /qos@ff280380rockchip,rk3528-qossyscon( 0qos@ff280400rockchip,rk3528-qossyscon( 1syscon@ff340000rockchip,rk3528-vpu-grfsyscon4Msyscon@ff348000$rockchip,rk3528-pipe-phy-grfsyscon4jsyscon@ff360000rockchip,rk3528-vo-grfsyscon6Gclock-controller@ff4a0000rockchip,rk3528-cruJ t          z y  LLFq;;]Q沀eр Cׄ#FsY@e Hxin24mgmac01 syscon@ff540000rockchip,rk3528-ioc-grfsysconT power-management@ff600000&rockchip,rk3528-pmusysconsimple-mfd` power-controller!rockchip,rk3528-power-controller>+ power-domain@4 R>power-domain@5R> disabledpower-domain@6R>power-domain@7$R !"#$%&'(>power-domain@8$R)*+,-./01>gpu@ff700000"rockchip,rk3528-maliarm,mali-450p @  HbuscoreTHXYV\]Z["Tgpgpmmupppp0ppmmu0pp1ppmmu12  wokayY3spi@ff9c0000(rockchip,rk3528-spirockchip,rk3066-spi Hspiclkapb_pclk He44jtxrx + disabledspi@ff9d0000(rockchip,rk3528-spirockchip,rk3066-spi Hspiclkapb_pclk He44jtxrx + disabledserial@ff9f0000&rockchip,rk3528-uartsnps,dw-apb-uart  kHbaudclkapb_pclk H(e4 4tokaydefault5serial@ff9f8000&rockchip,rk3528-uartsnps,dw-apb-uart  Hbaudclkapb_pclk H)e4 4  t disabledserial@ffa00000&rockchip,rk3528-uartsnps,dw-apb-uart  Hbaudclkapb_pclk H*e4 4  tokayjtxrxdefault 678bluetoothbrcm,bcm43438-bt uHlpo 9 :H Thost-wakeupdefault ;<= :>serial@ffa08000&rockchip,rk3528-uartsnps,dw-apb-uart  Hbaudclkapb_pclk H+e44 t disabledserial@ffa10000&rockchip,rk3528-uartsnps,dw-apb-uart  1Hbaudclkapb_pclk H,e44 t disabledserial@ffa18000&rockchip,rk3528-uartsnps,dw-apb-uart " Hbaudclkapb_pclk H-e44 t disabledserial@ffa20000&rockchip,rk3528-uartsnps,dw-apb-uart % Hbaudclkapb_pclk H.e44 t disabledserial@ffa28000&rockchip,rk3528-uartsnps,dw-apb-uart ( Hbaudclkapb_pclk H/e44 t disabledi2c@ffa50000(rockchip,rk3528-i2crockchip,rk3399-i2c  Hi2cpclk H= +okaydefault?rtc@51haoyu,hym8563Q Hdefault@i2c@ffa58000(rockchip,rk3528-i2crockchip,rk3399-i2c  Hi2cpclk H> + disabledi2c@ffa60000(rockchip,rk3528-i2crockchip,rk3399-i2c j i Hi2cpclk H?defaultA+ disabledi2c@ffa68000(rockchip,rk3528-i2crockchip,rk3399-i2c  Hi2cpclk H@ + disabledi2c@ffa70000(rockchip,rk3528-i2crockchip,rk3399-i2c 3 2 Hi2cpclk HAdefaultB + disabledi2c@ffa78000(rockchip,rk3528-i2crockchip,rk3399-i2c  Hi2cpclk HB + disabledi2c@ffa80000(rockchip,rk3528-i2crockchip,rk3399-i2c  Hi2cpclk HC + disabledi2c@ffa88000(rockchip,rk3528-i2crockchip,rk3399-i2c 5 4 Hi2cpclk HDdefaultC + disabledpwm@ffa90000(rockchip,rk3528-pwmrockchip,rk3328-pwm o n Hpwmpclk disabledpwm@ffa90010(rockchip,rk3528-pwmrockchip,rk3328-pwm o n Hpwmpclk disabledpwm@ffa90020(rockchip,rk3528-pwmrockchip,rk3328-pwm  o n HpwmpclkokaydefaultDvpwm@ffa90030(rockchip,rk3528-pwmrockchip,rk3328-pwm0 o n HpwmpclkokaydefaultEupwm@ffa98000(rockchip,rk3528-pwmrockchip,rk3328-pwm r q Hpwmpclk disabledpwm@ffa98010(rockchip,rk3528-pwmrockchip,rk3328-pwm r q Hpwmpclk disabledpwm@ffa98020(rockchip,rk3528-pwmrockchip,rk3328-pwm  r q Hpwmpclk disabledpwm@ffa98030(rockchip,rk3528-pwmrockchip,rk3328-pwm0 r q Hpwmpclk disabledadc@ffae0000rockchip,rk3528-saradc Hsaradcapb_pclk H  o saradc-apbokay>kethernet@ffbd0000&rockchip,rk3528-gmacsnps,dwmac-4.20a0      >Hstmmacethclk_mac_refmac_clk_rxmac_clk_txpclk_macaclk_macHqtTmacirqeth_wake_irqFrmii   stmmaceth4G"H2CIVJi disabledmdiosnps,dwmac-mdio+ethernet-phy@2ethernet-phy-ieee802.3-c22 "rdefaultKL Fstmmac-axi-configHrx-queues-configIqueue0tx-queues-configJqueue0ethernet@ffbe0000&rockchip,rk3528-gmacsnps,dwmac-4.20a (Hstmmacethclk_mac_refpclk_macaclk_macHy|Tmacirqeth_wake_irq  a stmmaceth4M"N2COVPiokayoutputQ rgmii-iddefaultRSTUVmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22defaultWN   Qstmmac-axi-configNrx-queues-configOqueue0tx-queues-configPqueue0mmc@ffbf00000rockchip,rk3528-dwcmshcrockchip,rk3588-dwcmshc   n6 ( Hcorebusaxiblocktimer H defaultXYZ[ ( A B C D Ecorebusaxiblocktimerokay",>MS[iu>mmc@ffc100000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc@  Hbiuciuciu-driveciu-sample H default \]^  gresetokay"_M[iu>+wifi@1brcm,bcm4329-fmac uHlpo :H Thost-wakedefault`mmc@ffc200000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc@  Hbiuciuciu-driveciu-sample H default abc  hreset disabledmmc@ffc300000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshc@ ( '  Hbiuciuciu-driveciu-sample Hрdefaultdefg  resetZokay",ihuidma-controller@ffd60000arm,pl330arm,primecell@ ^ Hapb_pclklH 4phy@ffdc0000rockchip,rk3528-naneng-combphy { {  Hrefapbpipe  c ephyapb,7MIjokaychosen_serial0:1500000n8adc-keys adc-keyskkwbuttonsw@dbutton-maskromMASKROMleds gpio-ledsdefaultlmled-0on heartbeat 9  heartbeatled-1onstatus 9  default-onregulator-0v6-vcc-ddrregulator-fixed vcc0v6_ddr1C '[ 'snregulator-0v9-vddregulator-fixedvdd_0v91C [ snregulator-1v1-vcc-ddrregulator-fixedvcc_ddr1C[snregulator-1v8-vccregulator-fixedvcc_1v81Cw@[w@s>regulator-1v8-vcc-ddrregulator-fixed vcc1v8_ddr1Cw@[w@snregulator-3v3-vccregulator-fixedvcc_3v31C2Z[2Zsoregulator-3v3-vcc-sdregulator-fixed defaultp vcc3v3_sdC2Z[2Zshregulator-5v0-vcc-sysregulator-fixed vcc5v0_sys1CLK@[LK@sonregulator-5v0-vcc-usb1-hostregulator-fixed~  defaultqvcc5v0_usb1_hostCLK@[LK@snregulator-5v0-vcc-usb2-hostregulator-fixed~ defaultrvcc5v0_usb2_hostCLK@[LK@snregulator-5v0-vcc-usb-otgregulator-fixed~ : defaultsvcc5v0_usb_otgCLK@[LK@snregulator-vcc-dcinregulator-fixed vcc_dcin1oregulator-vccio-sdregulator-gpio defaultt vccio_sdCw@[2Zw@2Zsniregulator-vdd-armpwm-regulatorunvdd_arm1C b[Shregulator-vdd-logicpwm-regulatorvn vdd_logic1C [Y3sdio-pwrseqmmc-pwrseq-simpledefaultwx :_ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4ethernet0i2c0mmc0mmc1mmc2serial0serial2cpuregdevice_typeenable-methodclocksoperating-points-v2cpu-supplyphandlearm,smc-idshmem#clock-cellsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,grfrangesinterruptsgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellspower-domainsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsno-mapclock-frequencyclock-output-namesreg-namesbus-rangeclock-namesinterrupt-namesinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speednum-lanesphysphy-namesresetsreset-namesstatuspinctrl-namespinctrl-0reset-gpiosvpcie3v3-supplyassigned-clocksassigned-clock-rates#reset-cells#power-domain-cellspm_qosmali-supplydmasdma-namesreg-io-widthreg-shiftuart-has-rtsctsdevice-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplywakeup-source#pwm-cells#io-channel-cellsvref-supplyphy-handlephy-modesnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsophy-is-integratedsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useclock_in_outphy-supplyreset-assert-usreset-deassert-usmax-frequencybus-widthcap-mmc-highspeedmmc-hs200-1_8vno-sdno-sdionon-removablevmmc-supplyvqmmc-supplyfifo-depthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcsd-uhs-sdr104rockchip,default-sample-phasedisable-wp#dma-cellsarm,pl330-periph-burst#phy-cellsrockchip,pipe-grfrockchip,pipe-phy-grfstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltcolordefault-statefunctionlinux,default-triggerregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplyenable-active-highstatespwmspwm-supplyregulator-settling-time-up-uspost-power-on-delay-ms