8(  ,,asus,rk3566-tinker-board-3srockchip,rk35667Asus Tinker Board 3Saliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/mmc@fe2b0000/mmc@fe310000cpus cpu@0cpu,arm,cortex-a55 psci(@:GT@fs cpu@100cpu,arm,cortex-a55 psci(@:GT@fs cpu@200cpu,arm,cortex-a55 psci(@:GT@fs cpu@300cpu,arm,cortex-a55 psci(@:GT@fs l3-cache,cache*@<display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc˂ protocol@14hdmi-sound,simple-audio-cardHDMIi2s 3disabledsimple-audio-card,codec:simple-audio-card,cpu: pmu,arm,cortex-a55-pmu0DO psci ,arm,psci-1.0smcreserved-memory bshmem@10f000,arm,scmi-shmemitimer,arm,armv8-timer0D   pxin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32kdefaultsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob D_ sata-phy 3disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob D` sata-phy 3disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ Dref_clksuspend_clkbus_clkotg utmi_wide 3disabled usb2-phy. 5high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ Dref_clksuspend_clkbus_clkhost usb2-phyusb3-phy utmi_wide 3disabledinterrupt-controller@fd400000 ,arm,gic-v3 @F D CXiAs(~b msi-controller@fd440000,arm,gic-v3-itsD~Lusb@fd800000 ,generic-ehci Dusb3okayusb@fd840000 ,generic-ohci Dusb3okayusb@fd880000 ,generic-ehci Dusb3okayusb@fd8c0000 ,generic-ohci Dusb3okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdJio-domains&,rockchip,rk3568-pmu-io-voltage-domain 3disabledsyscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucruclock-controller@fdd20000,rockchip,rk3568-cruxin24m G i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c D.- i2cpclkdefault 3okaypmic@20,rockchip,rk809 HHmclkrk809-clkout1rk809-clkout2Ddefault'5AMYeq}regulatorsDCDC_REG5vcc_1v8w@w@Yregulator-state-memSWITCH_REG1vcc_3v3Xregulator-state-memSWITCH_REG2 vcc3v3_sdQregulator-state-memLDO_REG5 vccio_sdw@2ZRregulator-state-memregulator@40,silergy,syr827@vdd_cpu 0O<Qregulator-state-memserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart Dt ,baudclkapb_pclk\ !defaultan 3disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk"defaultx 3disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk#defaultx 3disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk$defaultx 3disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk%defaultx 3disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller power-domain@7&power-domain@8 '()power-domain@9  *+,power-domain@10 -./012power-domain@11 3power-domain@13 4power-domain@14 567power-domain@1589:;<gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$D()' jobmmugpugpubus 3disabled=video-codec@fdea0400,rockchip,rk3568-vpu Dvdpu aclkhclk> iommu@fdea0800,rockchip,rk3568-iommu@ D aclkiface >rga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga DZaclkhclksclk&$% coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu D@ aclkhclk? iommu@fdee0800,rockchip,rk3568-iommu@ D? aclkiface ?video-capture@fdfe0000,rockchip,rk3568-vicap D aclkhclkdclkiclk@(arsthrstdrstprstirst 3disabledports port@0port@1iommu@fdfe0800,rockchip,rk3568-iommu D aclkiface 3disabled@mmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ Dd biuciuciu-driveciu-sampleрreset 3disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aD macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref stmmacethA#B6CI 3disabledmdio,snps,dwmac-mdio stmmac-axi-configR\lArx-queues-config|Bqueue0tx-queues-configCqueue0vop@fe040000 0@vopgamma-lut D(%aclkhclkdclk_vp0dclk_vp1dclk_vp2D  3disabled,rockchip,rk3566-vopports port@0 port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >? D aclkiface  3disabledDdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi DDpclkdphyE apb 3disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi DEpclkdphyF apb 3disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  D-((iahbisfrcecrefdefault GHI a 3disabledports port@0port@1qos@fe128000,rockchip,rk3568-qossyscon &qos@fe138080,rockchip,rk3568-qossyscon 5qos@fe138100,rockchip,rk3568-qossyscon 6qos@fe138180,rockchip,rk3568-qossyscon 7qos@fe148000,rockchip,rk3568-qossyscon 'qos@fe148080,rockchip,rk3568-qossyscon (qos@fe148100,rockchip,rk3568-qossyscon )qos@fe150000,rockchip,rk3568-qossyscon 3qos@fe158000,rockchip,rk3568-qossyscon -qos@fe158100,rockchip,rk3568-qossyscon .qos@fe158180,rockchip,rk3568-qossyscon /qos@fe158200,rockchip,rk3568-qossyscon 0qos@fe158280,rockchip,rk3568-qossyscon 1qos@fe158300,rockchip,rk3568-qossyscon 2qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon 8qos@fe190280,rockchip,rk3568-qossyscon 9qos@fe190300,rockchip,rk3568-qossyscon :qos@fe190380,rockchip,rk3568-qossyscon ;qos@fe190400,rockchip,rk3568-qossyscon <qos@fe198000,rockchip,rk3568-qossyscon 4qos@fe1a8000,rockchip,rk3568-qossyscon *qos@fe1a8080,rockchip,rk3568-qossyscon +qos@fe1a8100,rockchip,rk3568-qossyscon ,dfi@fe230000,rockchip,rk3568-dfi# D Jpcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<DKJIHGsyspmcmsglegacyerr($aclk_mstaclk_slvaclk_dbipclkauxpciX`KKKK (L0 pcie-phyTb @pipe  3disabledlegacy-interrupt-controllerXC DHKmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ Db biuciuciu-driveciu-sampleрreset3okay:DUdefaultMNOP`QlRmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ Dc biuciuciu-driveciu-sampleрreset 3disabledspi@fe300000 ,rockchip,sfc0@ Dexvclk_sfchclk_sfcSdefault 3disabledmmc@fe310000,rockchip,rk3568-dwcmshc1 D{} n6(|zy{}corebusaxiblocktimer3okay:y defaultTUVW`XlYrng@fe388000,rockchip,rk3568-rng8@po coreahbm 3disabledi2s@fe400000,rockchip,rk3568-i2s-tdm@ D4=AFqFq?C9mclk_txmclk_rxhclk\ZtxPQ tx-mrx-m 3disabled i2s@fe410000,rockchip,rk3568-i2s-tdmA D5EIFqFqGK:mclk_txmclk_rxhclk\ZZrxtxRS tx-mrx-mdefault0[\]^_`abcdef 3disabledi2s@fe420000,rockchip,rk3568-i2s-tdmB D6MFqOO;mclk_txmclk_rxhclk\ZZtxrxTtx-mdefaultghij 3disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC D7SW<mclk_txmclk_rxhclk\ZZtxrxUV tx-mrx-m 3disabledpdm@fe440000,rockchip,rk3568-pdmD DLZYpdm_clkpdm_hclk\Z rxklmnopdefaultXpdm-m 3disabledspdif@fe460000,rockchip,rk3568-spdifF Df mclkhclk_\\Ztxdefaultq 3disableddma-controller@fe530000,arm,pl330arm,primecellS@D   apb_pclk dma-controller@fe550000,arm,pl330arm,primecellU@D  apb_pclkZi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ D/HG i2cpclkrdefault  3disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ D0JI i2cpclksdefault 3okayeeprom@50 ,atmel,24c08Pdefaulttrtc@6f ,isil,isl1208oirq defaultui2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ D1LK i2cpclkvdefault  3disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] D2NM i2cpclkwdefault  3disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ D3PO i2cpclkxdefault  3disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt` D tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia DgRQspiclkapb_pclk\  txrxdefault yz{  3disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib DhTSspiclkapb_pclk\  txrxdefault |}~  3disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic DiVUspiclkapb_pclk\  txrxdefault   3disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid DjXWspiclkapb_pclk\  txrxdefault   3disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte Dubaudclkapb_pclk\  defaultan 3disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf Dv# baudclkapb_pclk\  defaultan3okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg Dw'$baudclkapb_pclk\  defaultan 3disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth Dx+(baudclkapb_pclk\  defaultan 3disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti Dy/,baudclkapb_pclk\ defaultan 3disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj Dz30baudclkapb_pclk\ defaultan 3disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk D{74baudclkapb_pclk\  defaultan 3disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl D|;8baudclkapb_pclk\  defaultan 3disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm D}?<baudclkapb_pclk\  defaultan 3disabledthermal-zonescpu-thermald tripscpu_alert0p(passivecpu_alert1$(passivecpu_crits( criticalcooling-mapsmap0308 gpu-thermal tripsgpu-thresholdp(passivegpu-target$(passivegpu-crits( criticalcooling-mapsmap03 8tsadc@fe710000,rockchip,rk3568-tsadcq Dsf@ `tsadcapb_pclkGsdefaultsleep^h 3disabledsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr D]saradcapb_pclk saradc-apb~ 3disabledpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultx 3disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultx 3disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefaultx 3disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefaultx 3disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultx 3disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultx 3disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefaultx 3disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefaultx 3disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultx 3disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultx 3disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefaultx 3disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefaultx 3disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe"phy 3disabledphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe%phy 3disabledphy@fe870000,rockchip,rk3568-csi-dphyypclkapb 3disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz apb 3disabledEmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{ apb 3disabledFusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m D3okayhost-port3okayotg-port 3disabledusb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m D3okayhost-port3okayotg-port 3disabledpinctrl,rockchip,rk3568-pinctrlJ bgpio@fdd60000,rockchip,gpio-bank D!.  CXgpio@fe740000,rockchip,gpio-bankt D"cd CXgpio@fe750000,rockchip,gpio-banku D#ef@ CXgpio@fe760000,rockchip,gpio-bankv D$gh` CXgpio@fe770000,rockchip,gpio-bankw D%ij CXpcfg-pull-up pcfg-pull-none pcfg-pull-none-drv-level-1  pcfg-pull-none-drv-level-2  pcfg-pull-none-drv-level-3  pcfg-pull-up-drv-level-1  pcfg-pull-up-drv-level-2  pcfg-pull-none-smt  /acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 Dcpuebcedpdpemmcemmc-bus8 D  Temmc-clk DUemmc-cmd DVemmc-datastrobe DWeth0eth1flashfspifspi-pins` DSgmac0gmac1gpuhdmitxhdmitxm0-cec DIhdmitx-scl DGhdmitx-sda DHi2c0i2c0-xfer D  i2c1i2c1-xfer D  ri2c2i2c2m0-xfer D si2c3i2c3m0-xfer Dvi2c4i2c4m0-xfer D  wi2c5i2c5m0-xfer D  xi2s1i2s1m0-lrckrx D^i2s1m0-lrcktx D]i2s1m0-mclk Di2s1m0-sclkrx D\i2s1m0-sclktx D[i2s1m0-sdi0 D _i2s1m0-sdi1 D `i2s1m0-sdi2 D ai2s1m0-sdi3 Dbi2s1m0-sdo0 Dci2s1m0-sdo1 Ddi2s1m0-sdo2 D ei2s1m0-sdo3 D fi2s2i2s2m0-lrcktx Dhi2s2m0-sclktx Dgi2s2m0-sdi Dii2s2m0-sdo Dji2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk Dkpdmm0-clk1 Dlpdmm0-sdi0 D mpdmm0-sdi1 D npdmm0-sdi2 D opdmm0-sdi3 Dppmicpmic-int-l Dpmupwm0pwm0m0-pins D"pwm1pwm1m0-pins D#pwm2pwm2m0-pins D$pwm3pwm3-pins D%pwm4pwm4-pins Dpwm5pwm5-pins Dpwm6pwm6-pins Dpwm7pwm7-pins Dpwm8pwm8m0-pins D pwm9pwm9m0-pins D pwm10pwm10m0-pins D pwm11pwm11m0-pins Dpwm12pwm12m0-pins Dpwm13pwm13m0-pins Dpwm14pwm14m0-pins Dpwm15pwm15m0-pins Drefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ DMsdmmc0-clk DNsdmmc0-cmd DOsdmmc0-det DPsdmmc1sdmmc2spdifspdifm0-tx Dqspi0spi0m0-pins0 D {spi0m0-cs0 Dyspi0m0-cs1 Dzspi1spi1m0-pins0 D ~spi1m0-cs0 D|spi1m0-cs1 D}spi2spi2m0-pins0 Dspi2m0-cs0 Dspi2m0-cs1 Dspi3spi3m0-pins0 D  spi3m0-cs0 Dspi3m0-cs1 Dtsadctsadc-shutorg Dtsadc-pin Duart0uart0-xfer D!uart1uart1m0-xfer D  uart2uart2m0-xfer Duart3uart3m0-xfer Duart4uart4m0-xfer Duart5uart5m0-xfer Duart6uart6m0-xfer Duart7uart7m0-xfer Duart8uart8m0-xfer Duart9uart9m0-xfer Dvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2eepromeeprom-wc-n Dtrtcrtcic-int-l Duusbu2-a-vbus-en Du3-a-vbus-en Dopp-table-0,operating-points-v2 Ropp-408000000 ]Q d P P0 r@opp-600000000 ]#F d P P0 r@opp-816000000 ]0, d P P0 r@ opp-1104000000 ]Aʹ d 0 r@opp-1416000000 ]Tfr d0 r@opp-1608000000 ]_" d0 r@opp-1800000000 ]kI d000 r@opp-table-1,operating-points-v2=opp-200000000 ]  d P PB@opp-300000000 ] d P PB@opp-400000000 ]ׄ d P PB@opp-600000000 ]#F d B@opp-700000000 ])' d~~B@opp-800000000 ]/ dB@B@B@chosen serial2:1500000n8gpio-leds ,gpio-ledsact-led  mmc1rsv-led  noneregulator-3v3-vcc-sys,regulator-fixed vcc3v3_sys2Z2ZQregulator-5v0-vcc-sys,regulator-fixed vcc5v0_sysLK@LK@regulator-5v0-vcc-usb-host,regulator-fixed  defaultvcc5v0_usb_hostLK@LK@Q interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc1mmc0device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cells#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellssystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-off-in-suspendfcs,suspend-voltage-selectorregulator-ramp-delayvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-hs200-1_8vnon-removabledma-namesarm,pl330-periph-burst#dma-cellsinterrupts-extendedpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cells#io-channel-cellsrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplygpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathgpioslinux,default-triggerenable-active-high