8T( q %,lunzn,fastrhino-r68srockchip,rk35687Lunzn FastRhino R68Saliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe2a0000/ethernet@fe010000/mmc@fe310000cpus cpu@0cpu,arm,cortex-a55 psci*7@IVc@u cpu@100cpu,arm,cortex-a55 psci*7@IVc@u cpu@200cpu,arm,cortex-a55 psci*7@IVc@u cpu@300cpu,arm,cortex-a55 psci*7@IVc@u l3-cache,cache,9@Kdisplay-subsystem,rockchip,display-subsystem disabledfirmwarescmi ,arm,scmi-smc protocol@14hdmi-sound,simple-audio-cardHDMIi2s/ disabledsimple-audio-card,codecIsimple-audio-card,cpuI pmu,arm,cortex-a55-pmu0S^ psci ,arm,psci-1.0#smcreserved-memory qshmem@10f000,arm,scmi-shmemxtimer,arm,armv8-timer0S   xin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32kdefaultsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob S_ sata-phy disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob S` sata-phy disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ Sref_clksuspend_clkbus_clk host utmi_wide$okay usb2-phyusb3-phy=usb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ Sref_clksuspend_clkbus_clk host usb2-phyusb3-phy utmi_wide$okayinterrupt-controller@fd400000 ,arm,gic-v3 @F S DYjAt(q msi-controller@fd440000,arm,gic-v3-itsD\usb@fd800000 ,generic-ehci Susb disabledusb@fd840000 ,generic-ohci Susb disabledusb@fd880000 ,generic-ehci Susb disabledusb@fd8c0000 ,generic-ohci Susb disabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdZio-domains&,rockchip,rk3568-pmu-io-voltage-domainokay syscon@fdc50000 ,rockchip,rk3568-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru'clock-controller@fdd20000,rockchip,rk3568-cruxin24m'4 DG Ypi2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c S.- i2cpclkdefault okayregulator@1c ,tcs,tcs4525}vdd_cpu 50 regulator-state-mempmic@20,rockchip,rk809 !Sdefault"8P#\#h#t######regulatorsDCDC_REG1 vdd_logic pqregulator-state-memDCDC_REG2vdd_gpu pqEregulator-state-memDCDC_REG3vcc_ddrregulator-state-memDCDC_REG4vdd_npu pqregulator-state-memDCDC_REG5vcc_1v8w@w@regulator-state-memLDO_REG1vdda0v9_image~~regulator-state-memLDO_REG2 vdda_0v9  regulator-state-memLDO_REG3 vdda0v9_pmu  regulator-state-mem LDO_REG4 vccio_acodec2Z2Zregulator-state-memLDO_REG5 vccio_sdw@2Zregulator-state-memLDO_REG6 vcc3v3_pmu2Z2Zregulator-state-mem2ZLDO_REG7 vcca_1v8w@w@regulator-state-memLDO_REG8 vcca1v8_pmuw@w@regulator-state-memw@LDO_REG9vcca1v8_image~w@regulator-state-mem~SWITCH_REG1vcc_3v3regulator-state-memSWITCH_REG2 vcc3v3_sdregulator-state-memserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart St ,baudclkapb_pclk$$%default' disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk&default1 disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk'default1 disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk(default1 disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk)default1 disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller< power-domain@7P*<power-domain@8 P+,-<power-domain@9  P./0<power-domain@10 P123456<power-domain@11 P7<power-domain@13 P8<power-domain@14 P9:;<power-domain@15 P<=>?@ABC<gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$S()' Wjobmmugpugpubus okayDgEvideo-codec@fdea0400,rockchip,rk3568-vpu SWvdpu aclkhclksF iommu@fdea0800,rockchip,rk3568-iommu@ S aclkiface zFrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga SZaclkhclksclk&$% coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu S@ aclkhclksG iommu@fdee0800,rockchip,rk3568-iommu@ S? aclkiface zGvideo-capture@fdfe0000,rockchip,rk3568-vicap S4D aclkhclkdclkiclksH(arsthrstdrstprstirstp disabledports port@0port@1iommu@fdfe0800,rockchip,rk3568-iommu S aclkifacez disabledHmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ Sd biuciuciu-driveciu-sampleрreset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aS Wmacirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref stmmacethpIJKokay4YDsY@output$L /rgmii-iddefaultMNOPQmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22Rdefault8N H ZS Lstmmac-axi-configfpIrx-queues-configJqueue0tx-queues-configKqueue0vop@fe040000 0@vopgamma-lut S(%aclkhclkdclk_vp0dclk_vp1dclk_vp2sT pokay,rockchip,rk3568-vop4Yports port@0 port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >? S aclkifacez okayTdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi SDpclkdphyU apbp disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi SEpclkdphyV apbp disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  S-((iahbisfrcecrefdefault WXY p disabledports port@0port@1qos@fe128000,rockchip,rk3568-qossyscon *qos@fe138080,rockchip,rk3568-qossyscon 9qos@fe138100,rockchip,rk3568-qossyscon :qos@fe138180,rockchip,rk3568-qossyscon ;qos@fe148000,rockchip,rk3568-qossyscon +qos@fe148080,rockchip,rk3568-qossyscon ,qos@fe148100,rockchip,rk3568-qossyscon -qos@fe150000,rockchip,rk3568-qossyscon 7qos@fe158000,rockchip,rk3568-qossyscon 1qos@fe158100,rockchip,rk3568-qossyscon 2qos@fe158180,rockchip,rk3568-qossyscon 3qos@fe158200,rockchip,rk3568-qossyscon 4qos@fe158280,rockchip,rk3568-qossyscon 5qos@fe158300,rockchip,rk3568-qossyscon 6qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon <qos@fe190280,rockchip,rk3568-qossyscon @qos@fe190300,rockchip,rk3568-qossyscon Aqos@fe190380,rockchip,rk3568-qossyscon Bqos@fe190400,rockchip,rk3568-qossyscon Cqos@fe198000,rockchip,rk3568-qossyscon 8qos@fe1a8000,rockchip,rk3568-qossyscon .qos@fe1a8080,rockchip,rk3568-qossyscon /qos@fe1a8100,rockchip,rk3568-qossyscon 0dfi@fe230000,rockchip,rk3568-dfi# S Zpcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<SKJIHGWsyspmcmsglegacyerr($aclk_mstaclk_slvaclk_dbipclkauxpciY`[[[[ />M\U pcie-phyTq @pipe  disabledlegacy-interrupt-controllerYD SH[mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ Sb biuciuciu-driveciu-sampleрreset disabledmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ Sc biuciuciu-driveciu-sampleрreset disabledspi@fe300000 ,rockchip,sfc0@ Sexvclk_sfchclk_sfc]default disabledmmc@fe310000,rockchip,rk3568-dwcmshc1 S4{}D n6(|zy{}corebusaxiblocktimerokay_ idefault^_`arng@fe388000,rockchip,rk3568-rng8@po coreahbmokayi2s@fe400000,rockchip,rk3568-i2s-tdm@ S44=ADFqFq?C9mclk_txmclk_rxhclkbwtxPQ tx-mrx-mp disabled i2s@fe410000,rockchip,rk3568-i2s-tdmA S54EIDFqFqGK:mclk_txmclk_rxhclkbbwrxtxRS tx-mrx-mpdefault0cdefghijklmn disabledi2s@fe420000,rockchip,rk3568-i2s-tdmB S64MDFqOO;mclk_txmclk_rxhclkbbwtxrxTtx-mpdefaultopqr disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC S7SW<mclk_txmclk_rxhclkbbwtxrxUV tx-mrx-mp disabledpdm@fe440000,rockchip,rk3568-pdmD SLZYpdm_clkpdm_hclkb wrxstuvwxdefaultXpdm-m disabledspdif@fe460000,rockchip,rk3568-spdifF Sf mclkhclk_\bwtxdefaulty disableddma-controller@fe530000,arm,pl330arm,primecellS@S   apb_pclk$dma-controller@fe550000,arm,pl330arm,primecellU@S  apb_pclkbi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ S/HG i2cpclkzdefault  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ S0JI i2cpclk{default  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ S1LK i2cpclk|default  disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] S2NM i2cpclk}default  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ S3PO i2cpclk~default  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt` S tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia SgRQspiclkapb_pclk$$wtxrxdefault   disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib ShTSspiclkapb_pclk$$wtxrxdefault   disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic SiVUspiclkapb_pclk$$wtxrxdefault   disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid SjXWspiclkapb_pclk$$wtxrxdefault   disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte Subaudclkapb_pclk$$default' disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf Sv# baudclkapb_pclk$$default'okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg Sw'$baudclkapb_pclk$$default' disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth Sx+(baudclkapb_pclk$$ default' disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti Sy/,baudclkapb_pclk$ $ default' disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj Sz30baudclkapb_pclk$ $ default' disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk S{74baudclkapb_pclk$$default' disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl S|;8baudclkapb_pclk$$default' disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm S}?<baudclkapb_pclk$$default' disabledthermal-zonescpu-thermaldtripscpu_alert0ppassivecpu_alert1$passivecpu_crits criticalcooling-mapsmap00 gpu-thermaltripsgpu-thresholdppassivegpu-target$passivegpu-crits criticalcooling-mapsmap0 tsadc@fe710000,rockchip,rk3568-tsadcq Ss4Df@ `tsadcapb_pclkp sdefaultsleep  #okay 9 Psaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr S]saradcapb_pclk saradc-apb kokay }pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault1 disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault1 disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefault1 disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefault1 disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault1 disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault1 disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefault1 disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefault1 disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault1 disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault1 disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefault1 disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefault1 disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe4"Dphy   okayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe4%Dphy    disabledphy@fe870000,rockchip,rk3568-csi-dphyypclk apbp disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz  apb disabledUmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{  apb disabledVusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m S okayhost-port okay otg-port okay usb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m S  disabledhost-port  disabledotg-port  disabledpinctrl,rockchip,rk3568-pinctrlpZ qgpio@fdd60000,rockchip,gpio-bank S!.    DY!gpio@fe740000,rockchip,gpio-bankt S"cd   DYSgpio@fe750000,rockchip,gpio-banku S#ef  @  DYgpio@fe760000,rockchip,gpio-bankv S$gh  `  DYgpio@fe770000,rockchip,gpio-bankw S%ij   DYpcfg-pull-up pcfg-pull-none pcfg-pull-none-drv-level-1  pcfg-pull-none-drv-level-2  pcfg-pull-none-drv-level-3  pcfg-pull-up-drv-level-1  pcfg-pull-up-drv-level-2  pcfg-pull-none-smt  (acodecaudiopwmbt656bt1120camcan0can0m0-pins =  can1can1m0-pins =can2can2m0-pins =  cifclk32kclk32k-out0 =cpuebcedpdpemmcemmc-bus8 =  ^emmc-clk =_emmc-cmd =`emmc-datastrobe =aeth0eth1flashfspifspi-pins` =]gmac0gmac0-miim =gmac0-rx-bus20 =gmac0-tx-bus20 =   gmac0-rgmii-clk =gmac0-rgmii-bus@ =eth-phy0-reset-pin =gmac1gmac1m1-miim =Mgmac1m1-rx-bus20 = Ogmac1m1-tx-bus20 =Ngmac1m1-rgmii-clk =Pgmac1m1-rgmii-bus@ =Qeth-phy1-reset-pin = Rgpuhdmitxhdmitxm0-cec =Yhdmitx-scl =Whdmitx-sda =Xi2c0i2c0-xfer =  i2c1i2c1-xfer =  zi2c2i2c2m0-xfer = {i2c3i2c3m0-xfer =|i2c4i2c4m0-xfer =  }i2c5i2c5m0-xfer =  ~i2s1i2s1m0-lrckrx =fi2s1m0-lrcktx =ei2s1m0-sclkrx =di2s1m0-sclktx =ci2s1m0-sdi0 = gi2s1m0-sdi1 = hi2s1m0-sdi2 = ii2s1m0-sdi3 =ji2s1m0-sdo0 =ki2s1m0-sdo1 =li2s1m0-sdo2 = mi2s1m0-sdo3 = ni2s2i2s2m0-lrcktx =pi2s2m0-sclktx =oi2s2m0-sdi =qi2s2m0-sdo =ri2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk =spdmm0-clk1 =tpdmm0-sdi0 = updmm0-sdi1 = vpdmm0-sdi2 = wpdmm0-sdi3 =xpmicpmic-int ="pmupwm0pwm0m0-pins =&pwm1pwm1m0-pins ='pwm2pwm2m0-pins =(pwm3pwm3-pins =)pwm4pwm4-pins =pwm5pwm5-pins =pwm6pwm6-pins =pwm7pwm7-pins =pwm8pwm8m0-pins = pwm9pwm9m0-pins = pwm10pwm10m0-pins = pwm11pwm11m0-pins =pwm12pwm12m0-pins =pwm13pwm13m0-pins =pwm14pwm14m0-pins =pwm15pwm15m0-pins =refclksatasata0sata1sata2scrsdmmc0sdmmc1sdmmc2spdifspdifm0-tx =yspi0spi0m0-pins0 = spi0m0-cs0 =spi0m0-cs1 =spi1spi1m0-pins0 = spi1m0-cs0 =spi1m0-cs1 =spi2spi2m0-pins0 =spi2m0-cs0 =spi2m0-cs1 =spi3spi3m0-pins0 =  spi3m0-cs0 =spi3m0-cs1 =tsadctsadc-shutorg =tsadc-pin =uart0uart0-xfer =%uart1uart1m0-xfer =  uart2uart2m0-xfer =uart3uart3m0-xfer =uart4uart4m0-xfer =uart5uart5m0-xfer =uart6uart6m0-xfer =uart7uart7m0-xfer =uart8uart8m0-xfer =uart9uart9m0-xfer =vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2gpio-ledsstatus-led-pin =rockchip-keyreset-button-pin =usbvcc5v0-usb-otg-en =opp-table-0,operating-points-v2 Kopp-408000000 VQ ] P P0 k@opp-600000000 V#F ] P P0 k@opp-816000000 V0, ] P P0 k@ |opp-1104000000 VAʹ ] 0 k@opp-1416000000 VTfr ]0 k@opp-1608000000 V_" ]0 k@opp-1800000000 VkI ]000 k@opp-1992000000 Vv ]000 k@opp-table-1,operating-points-v2Dopp-200000000 V  ] P PB@opp-300000000 V ] P PB@opp-400000000 Vׄ ] P PB@opp-600000000 V#F ] B@opp-700000000 V)' ]~~B@opp-800000000 V/ ]B@B@B@sata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob S^ sata-phy disabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconqos@fe190080,rockchip,rk3568-qossyscon =qos@fe190100,rockchip,rk3568-qossyscon >qos@fe190200,rockchip,rk3568-qossyscon ?syscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconˀphy@fe8c0000,rockchip,rk3568-pcie3-phy &'wrefclk_mrefclk_npclkphy okay pcie@fe270000,rockchip,rk3568-pcie ($aclk_mstaclk_slvaclk_dbipclkauxpci<SWsyspmcmsglegacyerrY` />M\U pcie-phy0@@'Tq @@@dbiapbconfigpipeokay Z! legacy-interrupt-controllerDY Spcie@fe280000,rockchip,rk3568-pcie  /($aclk_mstaclk_slvaclk_dbipclkauxpci<SWsyspmcmsglegacyerrY` />M \ U pcie-phy0@(Tq @dbiapbconfigpipeokay Z! legacy-interrupt-controllerDY Sethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20a*SWmacirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref stmmacethpokay4YDsY@output$ /rgmii-iddefaultmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22default8N H ZSstmmac-axi-configfprx-queues-configqueue0tx-queues-configqueue0can@fe570000,rockchip,rk3568v2-canfdW SA@ baudpclkUT coreapbdefault disabledcan@fe580000,rockchip,rk3568v2-canfdX SCB baudpclkWV coreapbdefault disabledcan@fe590000,rockchip,rk3568v2-canfdY SED baudpclkYX coreapbdefault disabledphy@fe820000,rockchip,rk3568-naneng-combphy| refapbpipe4Dphy   okaychosen serial2:1500000n8gpio-keys ,gpio-keysdefaultbutton-reset 2 `! reset gpio-leds ,gpio-ledsdefaultled-status  status `! heartbeatregulator-vcc12v-dcin,regulator-fixed vcc12v_dcinregulator-vcc3v3-pcie,regulator-fixed vcc3v3_pcie2Z2Z regulator-vcc3v3-sys,regulator-fixed vcc3v3_sys2Z2Z#regulator-vcc5v0-sys,regulator-fixed vcc5v0_sysLK@LK@ regulator-vcc5v0-usb-otg,regulator-fixed  !defaultvcc5v0_usb_otgLK@LK@ adc-keys ,adc-keys  ,buttons =w@button-recovery Recovery h W interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0ethernet1mmc0device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsstatusarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fssound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyvccio3-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendsystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modereset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-names#sound-dai-cellsrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthnon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplygpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,phy-grfdata-lanesvpcie3v3-supplystdout-pathdebounce-intervallabellinux,codecolorfunctionlinux,default-triggerenable-active-highgpioio-channelsio-channel-nameskeyup-threshold-microvoltpress-threshold-microvolt