Q8B(B-google,ciri-sku6google,cirimediatek,mt8188 +7Google Ciri sku6 board (rev4)aliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/dsc@1c009000Y/soc/ethdr@1c114000`/soc/mailbox@10320000e/soc/mailbox@10330000j/soc/merge0@1c014000q/soc/merge@1c10c000x/soc/merge@1c10d000/soc/merge@1c10e000/soc/merge@1c10f000/soc/merge@1c110000/soc/mutex@1c016000/soc/mutex@1c101000/soc/padding@1c11d000/soc/padding@1c11e000/soc/padding@1c11f000/soc/padding@1c120000/soc/padding@1c121000/soc/padding@1c122000/soc/padding@1c123000/soc/padding@1c124000/soc/rdma@1c104000/soc/rdma@1c105000/soc/rdma@1c106000 /soc/rdma@1c107000/soc/rdma@1c108000!/soc/rdma@1c109000,/soc/rdma@1c10a0007/soc/rdma@1c10b000B/soc/dsi@1c008000G/soc/i2c@11280000L/soc/i2c@11e00000Q/soc/i2c@11281000V/soc/i2c@11282000[/soc/i2c@11e01000`/soc/i2c@11ec0000e/soc/i2c@11ec1000j/soc/mmc@11230000o/soc/serial@11001100cpus+cpu@0wcpuarm,cortex-a55psciw5@@ 1ET cpu@100wcpuarm,cortex-a55psciw5@@ 1ET cpu@200wcpuarm,cortex-a55psciw5@@ 1ET cpu@300wcpuarm,cortex-a55psciw5@@ 1ET cpu@400wcpuarm,cortex-a55psciw5@@ 1ET cpu@500wcpuarm,cortex-a55psciw5@@ 1ETcpu@600wcpuarm,cortex-a78psci@@ 1ETcpu@700wcpuarm,cortex-a78psci@@ 1ETcpu-mapcluster0core0\ core1\ core2\ core3\ core4\ core5\core6\core7\idle-states`pscicpu-off-larm,idle-statem2_DTcpu-off-barm,idle-statem-Tcluster-off-larm,idle-statem7HTcluster-off-barm,idle-statem2Tl2-cache0cache@ Tl2-cache1cache@ Tl3-cachecache @Toscillator-13m fixed-clock]@clk13mT@oscillator-26m fixed-clockclk26mTCoscillator-32k fixed-clockclk32kopp-table-gpuoperating-points-v2Twopp-390000000 >!opp-431000000 !opp-473000000 1h@ '!opp-515000000 F X!opp-556000000 !# h!opp-598000000 # <!opp-640000000 &% !opp-670000000 'c !opp-700000000 )' L!opp-730000000 + }!opp-760000000 -L `!opp-790000000 /q 4!opp-835000000 1 (r!opp-880000000 4s q!opp-915000000 6 X!opp-915000000-5 6 !0opp-915000000-6 6 q!popp-950000000 8ـ 5!opp-950000000-5 8ـ X!0opp-950000000-6 8ـ q!ppmu-a55arm,cortex-a55-pmu 2pmu-a78arm,cortex-a78-pmu 2psci arm,psci-1.0smcsound=Ookay]Vaud_etdm_hp_onaud_etdm_hp_offaud_etdm_spk_onaud_etdm_spk_offaud_mtkaif_onaud_mtkaif_offdnxmediatek,mt8188-es83267mt8188_tas2563_8326ETDM1_OUTETDM_SPK_PINETDM2_OUTETDM_HP_PINETDM1_INETDM_SPK_PINETDM2_INETDM_HP_PINADDA CaptureMTKAIF_PINHeadphone JackHPOLHeadphone JackHPORMIC1Headset Micdai-link-0 ETDM1_IN_BEi2scpudai-link-1 ETDM1_OUT_BEi2scpucodecdai-link-2 ETDM2_IN_BEcpucodecdai-link-3 ETDM2_OUT_BEcpucodecdai-link-4DPTX_BEcodecthermal-zonescpu-little0-thermaltripstrip-alert0%_1~passiveT trip-alert1%s1~hottrip-crit%1 ~criticalcooling-mapsmap0< HA cpu-little1-thermaltripstrip-alert0%_1~passiveT!trip-alert1%s1~hottrip-crit%1 ~criticalcooling-mapsmap0<!HA cpu-little2-thermaltripstrip-alert0%_1~passiveT"trip-alert1%s1~hottrip-crit%1 ~criticalcooling-mapsmap0<"HA cpu-little3-thermaltripstrip-alert0%_1~passiveT#trip-alert1%s1~hottrip-crit%1 ~criticalcooling-mapsmap0<#HA cpu-big0-thermaldtripstrip-alert0%_1~passiveT$trip-alert1%s1~hottrip-crit%1 ~criticalcooling-mapsmap0<$Acpu-big1-thermaldtripstrip-alert0%_1~passiveT%trip-alert1%s1~hottrip-crit%1 ~criticalcooling-mapsmap0<%Aapu-thermal&tripstrip-alert0%L1~passivetrip-alert1%s1~hottrip-crit%1 ~criticalgpu-thermal&tripstrip-alert0%L1~passiveT'trip-alert1%s1~hottrip-crit%1 ~criticalcooling-mapsmap0<' A(gpu1-thermal&tripstrip-alert0%L1~passiveT)trip-alert1%s1~hottrip-crit%1 ~criticalcooling-mapsmap0<) A(adsp-thermal&tripstrip-alert0%L1~passivetrip-alert1%s1~hottrip-crit%1 ~criticalvdo-thermal&tripstrip-alert0%L1~passivetrip-alert1%s1~hottrip-crit%1 ~criticalinfra-thermal&tripstrip-alert0%L1~passivetrip-alert1%s1~hottrip-crit%1 ~criticalcam1-thermal&tripstrip-alert0%L1~passivetrip-alert1%s1~hottrip-crit%1 ~criticalcam2-thermal&tripstrip-alert0%L1~passivetrip-alert1%s1~hottrip-crit%1 ~criticaltimerarm,armv8-timer @2   ]@soc+ simple-busPTperformance-controller@11bc10mediatek,cpufreq-hw  0 [Tinterrupt-controller@c000000 arm,gic-v3u     2 Tppi-partitionsinterrupt-partition-0 Tinterrupt-partition-1Tsyscon@10000000 mediatek,mt8188-topckgensysconT-syscon@10001000#mediatek,mt8188-infracfg-aosysconT.syscon@10003000mediatek,mt8188-pericfgsyscon0TWpinctrl@10005000mediatek,mt8188-pinctrl`P0iocfg0iocfg_rmiocfg_ltiocfg_lmiocfg_rteint*2uBGSC_AP_INT_ODLAP_DISP_BKLTENEN_PPVAR_MIPI_DISPEN_PPVAR_MIPI_DISP_150MATCHSCR_RST_1V8_LI2S_SPKR_DATAOUTEN_PP3300_WLAN_XWIFI_KILL_1V8_LBT_KILL_1V8_LAP_FLASH_WP_LWCAM_PWDN_LWCAM_RST_LUCAM_PWDM_LUCAM_RST_LWCAM_24M_CLKUCAM_24M_CLKMT6319_INTDISP_RST_1V8_LDSIO_DSI_TETPMIPI_BL_PWM_1V8UART_AP_TX_GSC_RXUART_GSC_TX_AP_RXUART_SSPM_TX_DBGCON_RXUART_DBGCON_TX_SSPM_RXUART_ADSP_TX_DBGCON_RXUART_DBGCON_TX_ADSP_RXJTAG_AP_TMSJTAG_AP_TCKJTAG_AP_TDIJTAG_AP_TDOJTAG_AP_TRSTAP_KPCOL0TPTPEC_AP_HPD_ODPCIE_WAKE_1V8_ODLPCIE_RST_1V8_LPCIE_CLKREQ_1V8_ODLAP_I2C_AUD_SCL_1V8AP_I2C_AUD_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_TPM_SDA_1V8AP_I2C_TCHSCR_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_PMIC_SAR_SCL_1V8AP_I2C_PMIC_SAR_SDA_1V8AP_I2C_EC_HID_KB_SCL_1V8AP_I2C_EC_HID_KB_SDA_1V8AP_I2C_UCAM_SCL_1V8AP_I2C_UCAM_SDA_1V8AP_I2C_WCAM_SCL_1V8AP_I2C_WCAM_SDA_1V8SPI_AP_CS_EC_LSPI_AP_CLK_ECSPI_AP_DO_EC_DISPI_AP_DI_EC_DOTPTPSPI_AP_CS_TCHSCR_LSPI_AP_CLK_TCHSCRSPI_AP_DO_TCHSCR_DISPI_AP_DI_TCHSCR_DOTPTPTPTPTPPWRAP_SPI_CS_LPWRAP_SPI_CKPWRAP_SPI_MOSIPWRAP_SPI_MISOSRCLKENA0SRCLKENA1SCP_VREQ_VAOAP_RTC_CLK32KAP_PMIC_WDTRST_LAUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_DAT_MISO0AUD_DAT_MISO1HP_INT_ODLSPKR_INT_ODLI2S_HP_DATAINEN_SPKRI2S_SPKR_MCLKI2S_SPKR_BCLKI2S_HP_MCLKI2S_HP_BCLKI2S_HP_LRCKI2S_HP_DATAOUTRST_SPKR_LI2S_SPKR_LRCKI2S_SPKR_DATAINSPI_AP_CLK_ROMSPI_AP_CS_ROM_LSPI_AP_DO_ROM_DISPI_AP_DI_ROM_DOTPTPEN_PP2800A_UCAM_XEN_PP1200_UCAM_XEN_PP2800A_WCAM_XEN_PP1100_WCAM_XTCHSCR_INT_1V8_LMT7921_PMU_EN_1V8AP_EC_WARM_RST_REQEC_AP_HID_INT_ODLEC_AP_INT_ODLAP_XHCI_INIT_DONEEMMC_DAT7EMMC_DAT6EMMC_DAT5EMMC_DAT4EMMC_RST_LEMMC_CMDEMMC_CLKEMMC_DAT3EMMC_DAT2EMMC_DAT1EMMC_DAT0EMMC_DSLUSB3_HUB_RST_LEC_AP_RSVD0_ODLSPMI_SCLSPMI_SDAT*adsp-uart-pinsTKpins-bus #$aud-etdm-hp-on-pinsTpins-bus nstupins-mclk raud-etdm-hp-off-pinsTpins-bus nstu pins-mclk r aud-etdm-spk-on-pinsTpins-bus qwx-aud-etdm-spk-off-pinsTpins-bus qwx aud-mtkaif-on-pinsTpins-bus efghijaud-mtkaif-off-pinsTpins-bus efghij cros-ec-int-pinsTNpins-ec-ap-int-odl  disp-pwm0-pinsTPpins-disp-pwm0 <disp-pwm1-pinsTQpins-disp-pwm1 <dp-tx-hpd-pinsTpins-dp-tx-hpd .gsc-int-pinsTppins-gsc-ap-int-odl  i2c0-pinsTbpins-bus 87i2c1-pinsTopins-bus :9i2c2-pinsTdpins-bus <;H- i2c3-pinsTepins-bus >=i2c4-pinsTqpins-bus @?i2c5-pinsTspins-bus BAi2c6-pinsTtpins-bus DCmipi-disp-avdd-en-pinsTpins-en-ppvar-mipi-disp Umipi-disp-avee-en-pinsTpins-en-ppvar-mipi-disp-150ma Umipi-dsi-pinsTpins-bus Ummc0-default-pinsT]pins-bus$  -`epins-clk -fpins-rst -`emmc0-uhs-pinsT^pins-bus$  -`epins-clk -fpins-ds -fpins-rst -`enor-default-pinsTmpins-clk  }pins-cs ~`pcie-default-pinsTlpins-bus  /01scp-pinsTApins-scp-vreq bHspi0-pinsTMpins-bus EFGHHspi1-default-pinsTRpins-bus KLMNHspi1-sleep-pinsTSpins-bus KLMN spi2-pinsTTpins-bus OPQRHuart0-pinsTLpins-bus  `wlan-en-pinsTpins-en-pp3300-wlan Uaudio-codec-pinsTcpins-hp-int-odl l speaker-en-pinspins-en-spkr osyscon@10006000)mediatek,mt8188-scpsyssysconsimple-mfd`power-controller!mediatek,mt8188-power-controller+mTDpower-domain@0+m+power-domain@1,-mfgalt.+m/power-domain@2mpower-domain@3mpower-domain@4mpower-domain@15---- -3-4-=--0 0 00000000000000000 topcamccuimgvencvdecwpecfgckcfgxoss-sram-cmnss-sram-v0l0ss-sram-v0l1ss-sram-ve0ss-sram-ve1ss-sram-ifass-sram-camss-sram-v1l5ss-sram-v1l6ss-sram-rdrss-iommuss-imgcamss-emiss-subcmn-rdrss-rsiss-cmn-l4ss-vdec1ss-wpess-cvdo-ve1.+mpower-domain@16H--1111111Acfgckcfgxoss-galsss-cmnss-emiss-iommuss-larbss-rsiss-bus.+mpower-domain@200--22228cfgckcfgxoss-vpp1-g5ss-vpp1-g6ss-vpp1-l5ss-vpp1-l6.mpower-domain@223ss-vdec1-soc-l1.+mpower-domain@234 ss-vdec2-l1.mpower-domain@29 --- -camccubuscfgck.+m5power-domain@30(666666ss-cam-l13ss-cam-l14ss-cam-mm0ss-cam-mm1ss-camsys.+mpower-domain@32 678$ss-camb-subss-camb-rawss-camb-yuvmpower-domain@3169:$ss-cama-subss-cama-rawss-cama-yuvmpower-domain@17(--;;;&cfgckcfgxoss-larb2ss-larb3ss-gals.+mpower-domain@9 -@-? bushdcp.mpower-domain@18.mpower-domain@19.mpower-domain@24 <<<<0ss-ve1-larbss-ve1-coress-ve1-galsss-ve1-sram.mpower-domain@21==ss-wpe-l7ss-wpe-l7pce.mpower-domain@5.> ss-pextp-fmemmpower-domain@7-0-1seninf0seninf1mpower-domain@6mpower-domain@10 -E-D busmain.+mpower-domain@11 .+mpower-domain@14-Fasm.mpower-domain@13 -S-?a1sysintbusadspck.mpower-domain@12 .mpower-domain@8>  ethermac.mwatchdog@10007000mediatek,mt8188-wdtpTEsyscon@1000c000"mediatek,mt8188-apmixedsyssysconT,timer@10017000,mediatek,mt8188-timermediatek,mt6765-timerp2 @pwrap@100240003mediatek,mt8188-pwrapmediatek,mt8195-pwrapsyscon@pwrap2.. spiwrappmicmediatek,mt6359u *adcmediatek,mt6359-auxadcaudio-codecmediatek,mt6359-codec*regulatorsmediatek,mt6359-regulatorbuck_vs1>vs1M 5e!}buck_vgpu11>vgpu11Me7} buck_vmodem>vmodemM Xe X*}buck_vpu>vpuMe7} buck_vcore>vcoreMe } buck_vs2>vs2M 5ej}buck_vpa>vpaM e/M`},buck_vproc2>ppvar_dvdd_vgpuMdpe 5L} /jT+buck_vproc1>vproc1Me7L} T5buck_vcore_sshub >vcore_sshubMe7buck_vgpu11_sshub >vgpu11_sshubMdpedpldo_vaud18>vaud18Mw@ew@}ldo_vsim1>vsim1Me/M`ldo_vibr>vibrMOe2Zldo_vrf12>vrf12Me ldo_vusb>vusbM-e-}ldo_vsram_proc2 >vsram_proc2M eL}ldo_vio18>vio18Me}ldo_vcamio>vcamioMeldo_vcn18>vcn18Mw@ew@}ldo_vfe28>vfe28M*e*}xldo_vcn13>vcn13M e ldo_vcn33_1_bt >vcn33_1_btM*e5gldo_vcn33_1_wifi >vcn33_1_wifiM*e5gldo_vaux18>vaux18Mw@ew@}ldo_vsram_others>pp0850_dvdd_sram_gpuM qe 5}+jT/ldo_vefuse>vefuseMeldo_vxo22>vxo22Mw@e!ldo_vrfck>vrfckM`eldo_vrfck_1>vrfckMejldo_vbif28>vbif28M*e*}ldo_vio28>vio28M*e2Zldo_vemc>vemcM,@ e2Zldo_vemc_1>vemcM&%e2ZT_ldo_vcn33_2_bt >vcn33_2_btM*e5gldo_vcn33_2_wifi >vcn33_2_wifiM*e5gldo_va12>va12MOe ldo_va09>va09M 5eOldo_vrf18>vrf18MePldo_vsram_md >vsram_mdM 5e 5*}ldo_vufs>vufsMeT`ldo_vm18>vm18Mw@eTldo_vbbck>vbbckMeOldo_vsram_proc1 >vsram_proc1M eL}ldo_vsim2>vsim2Me/M`ldo_vsram_others_sshub>vsram_others_sshubM ertcmediatek,mt6358-rtcspmi@10027000*mediatek,mt8188-spmimediatek,mt8195-spmi p pmifspmimst)-89-..-8(pmif_sys_ckpmif_tmr_ckspmimst_clk_muxiommu@10315000mediatek,mt8188-iommu-infra1P2PTjmailbox@10320000mediatek,mt8188-gce2@2].Txmailbox@10330000mediatek,mt8188-gce3@2].Tzscp@10720000mediatek,mt8188-scp-dualrcfg+TPOokayscp@0mediatek,scp-core sram2OokayVdefaultdAiBT{scp@d0000mediatek,scp-core sram2 Odisabledaudio-controller@10b10000mediatek,mt8188-afe)-S9-C, , ------S-- -E-Q-M-N-O-P?----T-Rclk26mapll1apll2apll12_div0apll12_div1apll12_div2apll12_div3apll12_div9top_a1sys_hptop_aud_intbustop_audio_htop_audio_local_bustop_dptxtop_i2so1top_i2so2top_i2si1top_i2si2adsp_audio_26mapll1_d4apll2_d4apll12_div4top_a2systop_aud_iec26wD E audiosys.-OokayiFTadsp@10b80000mediatek,mt8188-dsp@ cfgsramsecbus)-D-D-Eaudiodspadsp_busGHrxtxwD OokayiIJVdefaultdKTmailbox@10b861004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxa2]TGmailbox@10b871004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxq2]THclock-controller@10b91100mediatek,mt8188-adsp-audio26mT?serial@11001100*mediatek,mt8188-uartmediatek,mt6577-uart2 C. baudbusOokayVdefaultdLserial@11001200*mediatek,mt8188-uartmediatek,mt6577-uart2 C. baudbus Odisabledserial@11001300*mediatek,mt8188-uartmediatek,mt6577-uart2 C. baudbus Odisabledserial@11001400*mediatek,mt8188-uartmediatek,mt6577-uart2 C. baudbus Odisabledadc@11002000.mediatek,mt8188-auxadcmediatek,mt8173-auxadc .mainOokaysyscon@11003000"mediatek,mt8188-pericfg-aosyscon0T>spi@1100a000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+2-y-.parent-clksel-clkspi-clkOokayVdefaultdMec@0google,cros-ec-spi *VdefaultdN-i2c-tunnelgoogle,cros-ec-i2c-tunnel+sbs-battery@fsbs,sbs-battery!5cbasgoogle,cros-cbaskeyboard-controllergoogle,cros-ec-keybJZ mDtx q rs}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g i(  thermal-sensor@1100b000mediatek,mt8188-lvts-ap 2..Olvts-calib-data-1T&pwm@1100e0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwm-'./mainmm2OokayVdefaultdPTpwm@1100f0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwm-(.Fmainmm2 OdisabledVdefaultdQspi@11010000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+2-y-.2parent-clksel-clkspi-clkOokayVdefaultsleepdRnSspi@11012000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+ 2-y-.3parent-clksel-clkspi-clkOokayVdefaultdTspi@11013000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+02-y-.4parent-clksel-clkspi-clk Odisabledspi@11018000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+2-y-.8parent-clksel-clkspi-clk Odisabledspi@11019000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+2-y-.9parent-clksel-clkspi-clk Odisabledusb@11201000#mediatek,mt8188-mtu3mediatek,mtu3  - > macippcT ?+2)-)9-v> -> sys_ckref_ckmcu_ckUV WhOokay host Xusb@0'mediatek,mt8188-xhcimediatek,mtk-xhcimac2)-*9-v> sys_ckOokay X 'Yethernet@11021000;mediatek,mt8188-gmacmediatek,mt8195-gmacsnps,dwmac-5.10a@2 3macirq0>>-A-B-C> .axiapbmac_mainptp_refrmii_internalmac_cg)-A-B-C9---wD C. TZ d[ w\    Odisabledmdiosnps,dwmac-mdio+stmmac-axi-config   TZrx-queues-config  T[queue0  queue1  queue2  queue3  tx-queues-config ) ?T\queue0  Q _queue1  Q _queue2  Q _queue3  Q _mmc@11230000(mediatek,mt8188-mmcmediatek,mt8183-mmc # -...M!sourcehclksource_cgcrypto_clkOokay k u  H       Vdefaultstate_uhsd]n^  _ `mmc@11240000(mediatek,mt8188-mmcmediatek,mt8183-mmc $-..$sourcehclksource_cg)-9- Odisabledmmc@11250000(mediatek,mt8188-mmcmediatek,mt8183-mmc %-..Asourcehclksource_cg)-9- Odisabledthermal-sensor@11278000mediatek,mt8188-lvts-mcu'2..Olvts-calib-data-1Ti2c@11280000mediatek,mt8188-i2c ("2 !a.7 maindma+OokayVdefaultdbaudio-codec@19everest,es8326 *lVdefaultdc + <Tamplifier@4fti,tas2563ti,tas2781OL R*vTi2c@11281000mediatek,mt8188-i2c ("2 !a.7 maindma+OokayVdefaultddi2c@11282000mediatek,mt8188-i2c ( "2 !a.7 maindma+OokayVdefaultdeclock-controller@11283000mediatek,mt8188-imp-iic-wrap-c(0Tausb@112a1000#mediatek,mt8188-mtu3mediatek,mtu3 *-*> macippcT*?+2)--9-v>->sys_ckref_ckmcu_ckf WpOokay host Xusb@0'mediatek,mt8188-xhcimediatek,mtk-xhcimac2)-.9-v>sys_ckOokay ^usb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 +-+> macippcT+?+2)-,9-v>->sys_ckref_ckmcu_ckg W`Ookay host Xusb@0'mediatek,mt8188-xhcimediatek,mtk-xhcimac2)-+9-v>sys_ckOokay 'hpcie@112f0000*mediatek,mt8188-pciemediatek,mt8192-pcie/  pcie-macT  owpci y+0.L.#.&.+.C> /pl_250mtl_26mtl_96mtl_32kperi_26mperi_memu2` iiii  j k pcie-phywDEmacOokayVdefaultdlinterrupt-controlleruTispi@1132c000(mediatek,mt8188-normediatek,mt8186-nor2-X>> spisfaxi)-X29+OokayVdefaultdmflash@0jedec,spi-norut-phy@11c20700.mediatek,mt8188-tphymediatek,generic-tphy-v3T+wDOokaypcie-phy@0-ref Tkhdmi-phy@11d5f0002mediatek,mt8188-hdmi-phymediatek,mt8195-hdmi-phy.pll_ref hdmi_txpll    OdisabledTdsi-phy@11c800000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-txC mipi_tx0_pll Ookay PTdsi-phy@11c900000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-txC mipi_tx0_pll  OdisabledTi2c@11e00000mediatek,mt8188-i2c "2 !n.7 maindma+OokayVdefaultdotpm@50 google,cr50P *Vdefaultdpi2c@11e01000mediatek,mt8188-i2c "2 !n.7 maindma+OokayVdefaultdqclock-controller@11e02000mediatek,mt8188-imp-iic-wrap-w Tnt-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+TOokayusb-phy@0-, refda_ref Tgt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+TOokayusb-phy@0-, refda_ref TUusb-phy@700 ,C refda_ref TVt-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+TOokayusb-phy@0-, refda_ref Tfi2c@11ec0000mediatek,mt8188-i2c "2 !r.7 maindma+OokayVdefaultdsi2c@11ec1000mediatek,mt8188-i2c "2 !r.7 maindma+OokayVdefaultdtclock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-en Trefuse@11f20000,mediatek,mt8188-efusemediatek,mt8186-efuse+dp-calib@1a0 Tlvts1-calib@1ac@TOgpu-speedbin@581 Tvsocinfo-data1@7a0socinfo-data2@7e0gpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jm@u02~} 3jobmmugpuv speed-bin wwDDD +core0core1core2EOokay >+T(clock-controller@13fbf000mediatek,mt8188-mfgcfgTusyscon@14000000mediatek,mt8188-vppsys0sysconT0dma-controller@14001000mediatek,mt8188-mdp3-rdma J0<x xxxx UywD \z t  {display@140020000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg 0 \z display@140040002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr@0" \z@display@140050002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aalP2F0 wD \zPdisplay@140060002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz`0  \z` t%display@140070006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshpp0# \zpdisplay@140080006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color2I0$wD \zdisplay@140090002mediatek,mt8188-mdp3-ovlmediatek,mt8195-mdp3-ovl2J0%wD \z Uydisplay@1400a000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding0wD \zdisplay@1400b0002mediatek,mt8188-mdp3-tccmediatek,mt8195-mdp3-tcc0 \zdisplay@1400c0004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot J0 UywD \z t +mutex@1400f000mediatek,mt8188-vpp-mutex2P0wD \zsmi@14012000mediatek,mt8188-smi-common-vpp 00apbsmiwDT|smi@14013000mediatek,mt8188-smi-larb000apbsmiwD  |Tiommu@14018000mediatek,mt8188-iommu-vppP0bclk2RwDP }~Tydma-controller@14f09000mediatek,mt8188-mdp3-rdma J2  UwD \z  tdma-controller@14f0a000mediatek,mt8188-mdp3-rdma J2  UywD \z  tdisplay@14f0c0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg2  \z display@14f0d0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg2  \z display@14f0f0002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr2" \z display@14f100002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr2$ \z display@14f120002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal 2j2#wD \z display@14f130002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal02k2%wD \z 0display@14f150002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rszP2 \z P tdisplay@14f160002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz`2 \z ` tdisplay@14f180006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp2 \z display@14f190006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp2 \z display@14f1a0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge2wD \z display@14f1b0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge2wD \z display@14f1d0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color2u2wD \z display@14f1e0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color2v2wD \z display@14f21000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding2wD \z display@14f22000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding 2wD \z display@14f240004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot@ J2 UwD \z @ tdisplay@14f250004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrotP J2 UywD \z P tclock-controller@14e00000mediatek,mt8188-wpesysT=clock-controller@14e02000mediatek,mt8188-wpesys-vpp0 smi@14e04000mediatek,mt8188-smi-larb@==apbsmiwD  |Tsyscon@14f00000mediatek,mt8188-vppsys1sysconT2mutex@14f01000mediatek,mt8188-vpp-mutex2{2&wD \z smi@14f02000mediatek,mt8188-smi-larb 22apbsmiwD  Tsmi@14f03000mediatek,mt8188-smi-larb022apbsmiwD  |Tclock-controller@15000000mediatek,mt8188-imgsysclock-controller@15110000 mediatek,mt8188-imgsys1-dip-topclock-controller@15130000mediatek,mt8188-imgsys1-dip-nrclock-controller@15220000mediatek,mt8188-imgsys-wpe1"clock-controller@15330000mediatek,mt8188-ipesys3clock-controller@15520000mediatek,mt8188-imgsys-wpe2Rclock-controller@15620000mediatek,mt8188-imgsys-wpe3bclock-controller@16000000mediatek,mt8188-camsysT6clock-controller@1604f000mediatek,mt8188-camsys-rawaT9clock-controller@1606f000mediatek,mt8188-camsys-yuvaT:clock-controller@1608f000mediatek,mt8188-camsys-rawbT7clock-controller@160af000mediatek,mt8188-camsys-yuvb T8clock-controller@17200000mediatek,mt8188-ccusys video-decoder@18000000mediatek,mt8188-vcodec-dec @T` Uy+ {video-codec@10000mediatek,mtk-vcodec-lat)-49-x -433-xselvdeclattop2H UyyyyyyyyywDvideo-codec@25000mediatek,mtk-vcodec-coreP)-49-x -444-xselvdeclattop2X UwDsmi@1800d000mediatek,mt8188-smi-larb33apbsmiwD  |Tclock-controller@1800f000mediatek,mt8188-vdecsys-socT3smi@1802e000mediatek,mt8188-smi-larb44apbsmiwD  Tclock-controller@1802f000mediatek,mt8188-vdecsysT4clock-controller@1a000000mediatek,mt8188-vencsysT<smi@1a010000mediatek,mt8188-smi-larb<<apbsmiwD  Tvideo-encoder@1a020000mediatek,mt8188-vcodec-enc+)-39-p< venc_sel2aX UwD {jpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgenc<jpgenc2b UwDjpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdec<<jpgdec-smijpgdec2c0 UwDovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovl12| UwD \xports+port@0endpoint Tport@1endpoint Trdma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdma 12~ Uy wD \x ports+port@0endpoint Tport@1endpoint Tcolor@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-color012wD \x0ports+port@0endpoint Tport@1endpoint Tccorr@1c0040006mediatek,mt8188-disp-ccorrmediatek,mt8192-disp-ccorr@12wD \x@ports+port@0endpoint Tport@1endpoint Taal@1c0050002mediatek,mt8188-disp-aalmediatek,mt8183-disp-aalP1 2wD \xPports+port@0endpoint Tport@1endpoint Tgamma@1c0060006mediatek,mt8188-disp-gammamediatek,mt8195-disp-gamma`12wD \x`ports+port@0endpoint Tport@1endpoint Tdither@1c0070008mediatek,mt8188-disp-dithermediatek,mt8183-disp-ditherp12wD \xpports+port@0endpoint Tport@1endpoint Tdsi@1c008000mediatek,mt8188-dsi11enginedigitalhs2 dphywD1Ookay+panel@0 *Vdefaultd     Ookayboe,nv110wum-l60himax,hx83102portendpoint Tports+port@0endpoint Tport@1endpoint Tdsc@1c0090002mediatek,mt8188-disp-dscmediatek,mt8195-disp-dsc1 2wD \xdsi@1c012000mediatek,mt8188-dsi 1 1enginedigitalhs2 dphywD1  Odisabledmerge0@1c0140006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge@1 ;mergemerge_async2wD \x@dp-intf@1c015000mediatek,mt8188-dp-intfP1 1 ,pixelenginepll2wD Odisabledmutex@1c016000mediatek,mt8188-disp-mutex`12wD \x` t>postmask@1c01a000<mediatek,mt8188-disp-postmaskmediatek,mt8192-disp-postmask12wD \xports+port@0endpoint Tport@1endpoint Tsyscon@1c01d000mediatek,mt8188-vdosys0syscon x \xT1port+endpoint@0 Tsmi@1c022000mediatek,mt8188-smi-larb 11apbsmiwD  Tsmi@1c023000mediatek,mt8188-smi-larb011apbsmiwD  |T}smi@1c024000mediatek,mt8188-smi-common-vdo@11apbsmiwDTiommu@1c028000mediatek,mt8188-iommu-vdoP1bclk2wDP Tsyscon@1c100000mediatek,mt8188-vdosys1syscon x \xT;port+endpoint@1 Tmutex@1c101000mediatek,mt8188-disp-mutex;2wD \x tsmi@1c102000mediatek,mt8188-smi-larb ;;apbsmiwD  Tsmi@1c103000mediatek,mt8188-smi-larb0;;apbsmiwD  |T~rdma@1c1040004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma@;2 U@wD J \x@rdma@1c1050004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaP;2 Uy`wD J \xPrdma@1c1060004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma`;2 UAwD J \x`rdma@1c1070004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmap;2 UyawD J \xprdma@1c1080004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma;2 UBwD J \xrdma@1c1090004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma;2 UybwD J \xrdma@1c10a0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma;2 UCwD J \xrdma@1c10b0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma;2 UycwD J \xmerge@1c10c0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge; ;mergemerge_async2wD; \x merge@1c10d0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge; ;mergemerge_async2wD; \x merge@1c10e0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge; ;mergemerge_async2wD; \x merge@1c10f0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge; ;mergemerge_async2wD; \x merge@1c1100006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge; ;mergemerge_async2wD; \x ,ports+port@0+endpoint@1 Tport@1+endpoint@1 Tdpi@1c112000(mediatek,mt8188-dpimediatek,mt8195-dpi ;8;;=pixelenginepll2 wD; Odisabledports+port@0endpointport@1endpointdp-intf@1c113000mediatek,mt8188-dp-intf0;:;,pixelenginepll2wDOokayports+port@0+endpoint@1 Tport@1+endpoint@1 Tethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrp@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsh;0;+;.;,;/;-;<;1;2;3;4;5-mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top26 UydyewD(;1;2;3;4;5p \x@xPxpxxxxports+port@0+endpoint@1 Tport@1+endpoint@1 Tpadding@1c11d000mediatek,mt8188-disp-padding;wD \xpadding@1c11e000mediatek,mt8188-disp-padding; wD \xpadding@1c11f000mediatek,mt8188-disp-padding;!wD \xpadding@1c120000mediatek,mt8188-disp-padding;"wD \xpadding@1c121000mediatek,mt8188-disp-padding;#wD \xpadding@1c122000mediatek,mt8188-disp-padding ;$wD \x padding@1c123000mediatek,mt8188-disp-padding0;%wD \x0padding@1c124000mediatek,mt8188-disp-padding@;&wD \x@hdmi@1c300000mediatek,mt8188-hdmi-tx0 -@->-?2.bushdcphdcp24mhdmi-split)->9-s2wD  hdmi Odisabledi2c2mediatek,mt8188-hdmi-ddcmediatek,mt8195-hdmi-ddcCports+port@0endpointport@1endpointedp-tx@1c500000mediatek,mt8188-edp-txP2dp_calibration_datawD C Odisableddp-tx@1c600000mediatek,mt8188-dp-tx`2dp_calibration_datawD COokayVdefaultdTports+port@0endpoint Tport@1endpoint Tbacklight-lcd0pwm-backlight _ q@ *    Tchosen serial0:115200n8dmic-codec dmic-codec  dmemory@40000000wmemory@regulator-pp1800-ldo-z1regulator-fixed>pp1800_ldo_z1 Mw@ew@ hregulator-pp3300-s3regulator-fixed >pp3300_s3 M2Ze2Z hTXregulator-pp3300-z1regulator-fixed >pp3300_z1 M2Ze2Z Thregulator-pp3300-wlanregulator-fixed >pp3300_wlanM2Ze2Z   * dVdefault hregulator-pp4200-s5regulator-fixed >pp4200_s5 M@@e@@ regulator-pp5000-z1regulator-fixed >pp5000_z1 MLK@eLK@ Tregulator-pp5000-usb-vbusregulator-fixed>pp5000_usb_vbusMLK@eLK@   * TYregulator-ppvar-sysregulator-fixed >ppvar_sys Tregulator-ppvar-mipi-disp-avddregulator-fixed>ppvar_mipi_disp_avdd   *Vdefaultd Tregulator-ppvar-mipi-disp-aveeregulator-fixed>ppvar_mipi_disp_avee}'   *Vdefaultd Treserved-memory+Tmemory@50000000shared-dma-poolPTBmemory@55000000shared-dma-poolU@memory@60000000shared-dma-pool`TJmemory@60f00000shared-dma-pool`TFmemory@61000000shared-dma-poolaTI compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7dsi0i2c0i2c1i2c2i2c3i2c4i2c5i2c6mmc0serial0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspinctrl-namespinctrl-0pinctrl-1pinctrl-2pinctrl-3pinctrl-4pinctrl-5mediatek,adspaudio-routinglink-namedai-formatmediatek,clk-providersound-daipolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxbias-pull-downinput-enabledrive-strengthoutput-highbias-disableoutput-lowbias-pull-up#power-domain-cellsdomain-supplyclocksclock-namesmediatek,infracfgmediatek,disable-extrst#sound-dai-cellsinterrupts-extended#io-channel-cellsmediatek,dmic-modemediatek,mic-type-0mediatek,mic-type-2regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadregulator-microvolt-offsetassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellsmemory-regionpower-domainsresetsreset-namesmediatek,topckgenmediatek,etdm-out1-cowork-sourcemediatek,etdm-in2-cowork-sourcemboxesmbox-namesspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsphyswakeup-sourcemediatek,syscon-wakeupdr_modevusb33-supplyvbus-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vmmc-hs400-enhanced-strobeno-sdno-sdionon-removablesupports-cqevmmc-supplyvqmmc-supplyclock-diveverest,jack-poleverest,interrupt-clkreset-gpiosusb2-lpm-disablebus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-names#phy-cellsmediatek,ibiasmediatek,ibias_updrive-strength-microampbitsoperating-points-v2power-domain-namesmali-supply#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsremote-endpointenable-gpiosbacklightavdd-supplyavee-supplypp1800-supplyrotationmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzdata-lanesbrightness-levelsdefault-brightness-levelnum-interpolated-stepspower-supplypwmsstdout-pathnum-channelswakeup-delay-msregulator-boot-onvin-supplyenable-active-highgpiono-map