S8ET(GE=ezurio,mt8390-tungsten-smarcmediatek,mt8390mediatek,mt8188 +"7Ezurio Tungsten700 SMARC (MT8390)aliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dpi@1c112000T/soc/dsc@1c009000Y/soc/ethdr@1c114000`/soc/mailbox@10320000e/soc/mailbox@10330000j/soc/merge0@1c014000q/soc/merge@1c10c000x/soc/merge@1c10d000/soc/merge@1c10e000/soc/merge@1c10f000/soc/merge@1c110000/soc/mutex@1c016000/soc/mutex@1c101000/soc/padding@1c11d000/soc/padding@1c11e000/soc/padding@1c11f000/soc/padding@1c120000/soc/padding@1c121000/soc/padding@1c122000/soc/padding@1c123000/soc/padding@1c124000/soc/rdma@1c104000/soc/rdma@1c105000/soc/rdma@1c106000 /soc/rdma@1c107000/soc/rdma@1c108000!/soc/rdma@1c109000,/soc/rdma@1c10a0007/soc/rdma@1c10b000B/soc/dsi@1c008000G/soc/ethernet@11021000Q/soc/i2c@11280000V/soc/i2c@11e00000[/soc/i2c@11281000`/soc/i2c@11282000e/soc/i2c@11e01000j/soc/i2c@11ec0000o/soc/i2c@11ec1000t/soc/mmc@11230000y/soc/mmc@11240000~/soc/mmc@11250000*/soc/i2c@11280000/i2c-mux@73/i2c@0/rtc@52/soc/pwrap@10024000/pmic/rtc/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55psciw5@@1>Ocr} cpu@100cpuarm,cortex-a55psciw5@@1>Ocr} cpu@200cpuarm,cortex-a55psciw5@@1>Ocr} cpu@300cpuarm,cortex-a55psciw5@@1>Ocr}cpu@400cpuarm,cortex-a55psciw5@@1>Ocr}cpu@500cpuarm,cortex-a55psciw5@@1>Ocr}cpu@600cpuarm,cortex-a78psci@@1> Ocr }cpu@700cpuarm,cortex-a78psci@@1> Ocr }cpu-mapcluster0core0 core1 core2 core3core4core5core6core7idle-statespscicpu-off-larm,idle-state2_D}cpu-off-barm,idle-state-}cluster-off-larm,idle-state7H}cluster-off-barm,idle-state2}l2-cache0cache@>}l2-cache1cache@>} l3-cachecache @}oscillator-13m fixed-clock ]@clk13m}8oscillator-26m fixed-clock clk26m}:oscillator-32k fixed-clock clk32kopp-table-gpuoperating-points-v2*}opp-3900000005><Jopp-4310000005<Jopp-47300000051h@< 'Jopp-5150000005F< XJopp-5560000005!#< hJopp-5980000005#< <Jopp-6400000005&%< Jopp-6700000005'c< Jopp-7000000005)'< LJopp-7300000005+< }Jopp-7600000005-L< `Jopp-7900000005/q< 4Jopp-83500000051< (rJopp-88000000054s< qJopp-91500000056< XJopp-915000000-556< J0opp-915000000-656< qJpopp-95000000058ـ< 5Jopp-950000000-558ـ< XJ0opp-950000000-658ـ< qJppmu-a55arm,cortex-a55-pmu [pmu-a78arm,cortex-a78-pmu [psci arm,psci-1.0smcsoundf xdisabledthermal-zonescpu-little0-thermaltripstrip-alert0Lpassive}trip-alert1shottrip-crit criticalcooling-mapsmap0H cpu-little1-thermaltripstrip-alert0Lpassive}trip-alert1shottrip-crit criticalcooling-mapsmap0H cpu-little2-thermaltripstrip-alert0Lpassive}trip-alert1shottrip-crit criticalcooling-mapsmap0H cpu-little3-thermaltripstrip-alert0Lpassive}trip-alert1shottrip-crit criticalcooling-mapsmap0H cpu-big0-thermaldtripstrip-alert0Lpassive}trip-alert1shottrip-crit criticalcooling-mapsmap0cpu-big1-thermaldtripstrip-alert0Lpassive}trip-alert1shottrip-crit criticalcooling-mapsmap0apu-thermaltripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalgpu-thermaltripstrip-alert0Lpassive}trip-alert1shottrip-crit criticalcooling-mapsmap0  gpu1-thermaltripstrip-alert0Lpassive}!trip-alert1shottrip-crit criticalcooling-mapsmap0!  adsp-thermaltripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalvdo-thermaltripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalinfra-thermaltripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalcam1-thermaltripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalcam2-thermaltripstrip-alert0Lpassivetrip-alert1shottrip-crit criticaltimerarm,armv8-timer @[   ]@soc+ simple-busperformance-controller@11bc10mediatek,cpufreq-hw  0 }interrupt-controller@c000000 arm,gic-v3 +    [ }ppi-partitionsinterrupt-partition-0@ }interrupt-partition-1@}syscon@10000000 mediatek,mt8188-topckgensyscon }%syscon@10001000#mediatek,mt8188-infracfg-aosyscon I}&syscon@10003000mediatek,mt8188-pericfgsyscon0 }Kpinctrl@10005000mediatek,mt8188-pinctrl`P0Viocfg0iocfg_rmiocfg_ltiocfg_lmiocfg_rteint`p|"+[}"audio-pinspins-aud-pmicefghijpins-pcm-wifiyz{|pins-i2swpxqndisp-pwm0-pins}Gpinsdsi0-sn65dsi84-pins}opins-irqpins-enableeth-default-pins}Spins-txdpins-cc pins-rxdfpins-mdiopins-powerpins-intrfeth-sleep-pins}Tpins-txdpins-ccpins-rxdpins-mdiogpio-keys-pinspins-keys ABhd3ss3320-pins}gpins-irq-ehdmi-vreg-pinspins-pwr2hdmi-pinspins-hotplug3pins-cec4pins-ddc56 i2c0-pins}dpins-bus87i2c0-mux-pins}epins-reseti2c1-pins}pins-bus:9i2c2-pins}mpins-bus<;i2c3-pins}spins-bus>=i2c4-pins}pins-bus@?i2c-mux-smarc-lcd-pins}npins-resetmmc0-default-pins}Upins-cmd-dat$epins-clkfpins-rstemmc0-uhs-pins}Vpins-cmd-dat$epins-clkfpins-dsfpins-rstemmc1-default-pins}Ypins-cmd-datepins-pwropins-pullup pins-clkfpins-insertmmc1-uhs-pins}Zpins-cmd-datepins-clkfmmc2-default-pins}]pins-clkfpins-cmd-datemmc2-uhs-pins}^pins-clkfpins-cmd-datemmc2-eint-pins}_pins-dat1erv3028-pins}fpins-irq*espi0-pins}Epins-spiEFGHspi1-pins}Hpins-spiKLMNpcie-default-pins}pins /01ts-dsi0-goodix-pins}rpins-irqepins-resetuart0-pins}Bpins uart1-pins}Cpins!"uart2-pins}Dpins#$usbotg-pins}wpins-iddigSpins-validUpins-vbusTusb1-hub-pins}pinsusb1-pins}MpinsXusb2-eth-pins}pinsPwifi-pwrseq-pins}pinsYwatchdog-pins}7pinsdsyscon@10006000)mediatek,mt8188-scpsyssysconsimple-mfd`power-controller!mediatek,mt8188-power-controller+};power-domain@0+%#power-domain@13$%:mfgaltF&+%'power-domain@2power-domain@3power-domain@4power-domain@153%%%% %3%4%=%%( ( ((((((((((((((((( :topcamccuimgvencvdecwpecfgckcfgxoss-sram-cmnss-sram-v0l0ss-sram-v0l1ss-sram-ve0ss-sram-ve1ss-sram-ifass-sram-camss-sram-v1l5ss-sram-v1l6ss-sram-rdrss-iommuss-imgcamss-emiss-subcmn-rdrss-rsiss-cmn-l4ss-vdec1ss-wpess-cvdo-ve1F&+power-domain@16H3%%)))))))A:cfgckcfgxoss-galsss-cmnss-emiss-iommuss-larbss-rsiss-busF&+power-domain@2003%%****8:cfgckcfgxoss-vpp1-g5ss-vpp1-g6ss-vpp1-l5ss-vpp1-l6F&power-domain@223+:ss-vdec1-soc-l1F&+power-domain@233, :ss-vdec2-l1F&power-domain@29 3%%% %:camccubuscfgckF&+power-domain@30(3-----6:ss-cam-l13ss-cam-l14ss-cam-mm0ss-cam-mm1ss-camsysF&+power-domain@32 3-./$:ss-camb-subss-camb-rawss-camb-yuvpower-domain@313-01$:ss-cama-subss-cama-rawss-cama-yuvpower-domain@17(3%%222&:cfgckcfgxoss-larb2ss-larb3ss-galsF&+power-domain@9 3%@%? :bushdcpF&power-domain@18F&power-domain@19F&power-domain@24 333330:ss-ve1-larbss-ve1-coress-ve1-galsss-ve1-sramF&power-domain@21344:ss-wpe-l7ss-wpe-l7pceF&power-domain@5F&35 :ss-pextp-fmempower-domain@73%0%1:seninf0seninf1power-domain@6power-domain@10 3%E%D :busmainF&+power-domain@11 F&+power-domain@143%F:asmF&power-domain@13 3%S%6:a1sysintbusadspckF&power-domain@12 F&power-domain@835  :ethermacF&watchdog@10007000mediatek,mt8188-wdtpXIpdefault~7}<syscon@1000c000"mediatek,mt8188-apmixedsyssyscon }$timer@10017000,mediatek,mt8188-timermediatek,mt6765-timerp[ 38pwrap@100240003mediatek,mt8188-pwrapmediatek,mt8195-pwrapsyscon@Vpwrap[3&& :spiwrappmicmediatek,mt6359+ "adcmediatek,mt6359-auxadcaudio-codecmediatek,mt6359-codecregulatorsmediatek,mt6359-regulatorbuck_vs1vs1 5!&Bbuck_vgpu11 dvdd_core7V& kBbuck_vmodemvmodemV*&Bbuck_vpu dvdd_adsp7V& kBbuck_vcore dvdd_proc_l V& kB}buck_vs2vs2jj&Bbuck_vpavpa_pmu 7&,Bbuck_vproc2vgpudp 5VL& k'n}#buck_vproc1vproc17VL& kbuck_vcore_sshub vcore_sshub7buck_vgpu11_sshub vgpu11_sshub7ldo_vaud18vaud18w@w@&ldo_vsim1 vsim1_pmuw@&}[ldo_vibrvibrO2Zldo_vrf12va12_abb2_pmu Bldo_vusbvusb--&B}Lldo_vsram_proc2 vsram_proc2 VL&Bldo_vio18vio18&Bldo_vcamiovcamioldo_vcn18 vcn18_pmuw@w@&B}aldo_vfe28vfe28**&xldo_vcn13vcn13  ldo_vcn33_1_bt vcn33_1_pmu*5gBldo_vcn33_1_wifi vcn33_1_wifi*5gldo_vaux18vaux18w@w@&Bldo_vsram_others vsram_gpu q 5V&#n}'ldo_vefusevefuse}ldo_vxo22vxo22w@!Bldo_vrfckvrfck`ldo_vrfck_1vrfckjldo_vbif28vbif28**&ldo_vio28vio28*2ZBldo_vemcvemc,@ 2Zldo_vemc_1vemc&%2ZB}Wldo_vcn33_2_bt vcn33_2_pmu2Z2ZB}`ldo_vcn33_2_wifi vcn33_2_wifi*5gldo_va12va12O Bldo_va09va09 5Oldo_vrf18vrf18Pldo_vsram_md vsram_md V*&Bldo_vufs vufs18_pmuB}Xldo_vm18vm18Bldo_vbbckvbbckOBldo_vsram_proc1 vsram_proc1 VL&Bldo_vsim2vsim2/M`ldo_vsram_others_sshubvsram_others_sshub rtcmediatek,mt6358-rtckeysmediatek,mt6359-keyspower-keytspmi@10027000*mediatek,mt8188-spmimediatek,mt8195-spmi p Vpmifspmimst%8"%3&&%8(:pmif_sys_ckpmif_tmr_ckspmimst_clk_mux+pmic@6mediatek,mt6315-regulatorregulatorsvbuck1vbuck17& kB} vbuck3vbuck37& kBvbuck4vbuck477& kBregulator-state-mem9Q7iommu@10315000mediatek,mt8188-iommu-infra1P[m}~mailbox@10320000mediatek,mt8188-gce2@[z3&}mailbox@10330000mediatek,mt8188-gce3@[z3&}scp@10720000mediatek,mt8188-scp-dualrVcfg+Pxokayscp@0mediatek,scp-core Vsram[xokay9}scp@d0000mediatek,scp-core Vsram[ xdisabledaudio-controller@10b10000mediatek,mt8188-afe%S"%3:$ $ %%%%%%S%% %E%Q%M%N%O%P6%%%%T%R:clk26mapll1apll2apll12_div0apll12_div1apll12_div2apll12_div3apll12_div9top_a1sys_hptop_aud_intbustop_audio_htop_audio_local_bustop_dptxtop_i2so1top_i2so2top_i2si1top_i2si2adsp_audio_26mapll1_d4apll2_d4apll12_div4top_a2systop_aud_iec[6; < audiosysF&%xokay=}adsp@10b80000mediatek,mt8188-dsp@ Vcfgsramsecbus%D3%D%E:audiodspadsp_bus>?rxtx; xokay@Amailbox@10b861004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxa[z}>mailbox@10b871004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxq[z}?clock-controller@10b91100mediatek,mt8188-adsp-audio26m }6serial@11001100*mediatek,mt8188-uartmediatek,mt6577-uart[ 3:& :baudbusxokay~Bpdefaultserial@11001200*mediatek,mt8188-uartmediatek,mt6577-uart[ 3:& :baudbusxokay~Cpdefaultserial@11001300*mediatek,mt8188-uartmediatek,mt6577-uart[ 3:& :baudbusxokay~Dpdefaultserial@11001400*mediatek,mt8188-uartmediatek,mt6577-uart[ 3:& :baudbus xdisabledadc@11002000.mediatek,mt8188-auxadcmediatek,mt8173-auxadc 3&:main xdisabledsyscon@11003000"mediatek,mt8188-pericfg-aosyscon0 }5spi@1100a000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+[3%y%&:parent-clksel-clkspi-clkxokay~Epdefaultthermal-sensor@1100b000mediatek,mt8188-lvts-ap [3&&Flvts-calib-data-1 }pwm@1100e0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwm3%'&/:mainmm[ xokaypdefault~G}pwm@1100f0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwm3%(&F:mainmm[  xdisabledspi@11010000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+[3%y%&2:parent-clksel-clkspi-clkxokay~Hpdefaultspi@11012000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+ [3%y%&3:parent-clksel-clkspi-clk xdisabledspi@11013000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+0[3%y%&4:parent-clksel-clkspi-clk xdisabledspi@11018000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+[3%y%&8:parent-clksel-clkspi-clk xdisabledspi@11019000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+[3%y%&9:parent-clksel-clkspi-clk xdisabledusb@11201000#mediatek,mt8188-mtu3mediatek,mtu3  - > Vmacippc ?+[%)"%v35 %5 :sys_ckref_ckmcu_ck+IJ 0KhxokayGhostOL~Mpdefaultusb@0'mediatek,mt8188-xhcimediatek,mtk-xhciVmac[%*"%v35 :sys_ckxokay]NOLethernet@11021000;mediatek,mt8188-gmacmediatek,mt8195-gmacsnps,dwmac-5.10a@[imacirq0355%A%B%C5 .:axiapbmac_mainptp_refrmii_internalmac_cg%A%B%C"%%%;y&OPQxokay rgmii-idRpdefaultsleep~ST  " " 8*mdiosnps,dwmac-mdio+ethernet-phy@7ethernet-phy-ieee802.3-c22 "}Rstmmac-axi-config M W g}Orx-queues-config w }Pqueue0  queue1  queue2  queue3  tx-queues-config  }Qqueue0   queue1   queue2   queue3   mmc@11230000(mediatek,mt8188-mmcmediatek,mt8183-mmc # 3%&&&M!:sourcehclksource_cgcrypto_clkxokay   ' 8H G  U d s   pdefaultstate_uhs~UV W Xmmc@11240000(mediatek,mt8188-mmcmediatek,mt8183-mmc $3%&&$:sourcehclksource_cg%"%xokay   G   pdefaultstate_uhs~YZ " [ \mmc@11250000(mediatek,mt8188-mmcmediatek,mt8183-mmc % "3%&&A:sourcehclksource_cg%"%xokay     G   s  pdefaultstate_uhsstate_eint~]^ _imsdcsdio_wakeup ` a bthermal-sensor@11278000mediatek,mt8188-lvts-mcu'[3&&Flvts-calib-data-1 }i2c@11280000mediatek,mt8188-i2c ("[ )3c&7 :maindma+xokaypdefault~di2c-mux@73 nxp,pca9546spdefault~e 3"+i2c@0+rtc@52microcrystal,rv3028R "*pdefault~f i2c@1+usb-typec@60 ti,hd3ss3220` "-pdefault~gports+port@0endpoint ?h}zport@1endpoint ?i}|i2c@2+codec@1a wlf,wm89623%M Oj [j hk uj k j l l i2c@3+i2c@11281000mediatek,mt8188-i2c ("[ )3c&7 :maindma+xokaypdefault~mi2c-mux@73 nxp,pca9546spdefault~n 3"+i2c@0+i2c@1+i2c@2+bridge@2c ti,sn65dsi84,pdefault~o "ports+port@0endpoint ?p }port@2endpoint ?q}touchscren@5d goodix,gt911]pdefault~r " " 3"i2c@3+i2c@11282000mediatek,mt8188-i2c ( "[ )3c&7 :maindma+xokaypdefault~sclock-controller@11283000mediatek,mt8188-imp-iic-wrap-c(0 }cusb@112a1000#mediatek,mt8188-mtu3mediatek,mtu3 *-*> Vmacippc*?+[%-"%v35%5:sys_ckref_ckmcu_ck+t 0KpxokayGhost high-speedOLusb@0'mediatek,mt8188-xhcimediatek,mtk-xhciVmac[%."%v35:sys_ckxokay]uOL+ethernet@1 usb424,7850+mdio+ethernet-phy@1 usb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 +-+> Vmacippc+?+[%,"%v35%5:sys_ckref_ckmcu_ck+v 0K`xokayGotg high-speed OL~wpdefaultusb@0'mediatek,mt8188-xhcimediatek,mtk-xhciVmac[%+"%v35:sys_ckxokay]xOLconnectorusb-c-connector USB-C dualports+port@0endpoint ?y}{port@1endpoint ?z}hports+port@0endpoint ?{}yport@1endpoint ?|}ipcie@112f0000*mediatek,mt8188-pciemediatek,mt8192-pcie/  Vpcie-mac  )pci 3+03&L&#&&&+&C5 /:pl_250mtl_26mtl_96mtl_32kperi_26mperi_mem[` D}}}} R e~ o+ ~pcie-phy;<macxokaypdefault~interrupt-controller+}}spi@1132c000(mediatek,mt8188-normediatek,mt8186-nor23%X55 :spisfaxi%X[9+ xdisabledt-phy@11c20700.mediatek,mt8188-tphymediatek,generic-tphy-v3+;xokaypcie-phy@03%:ref }hdmi-phy@11d5f0002mediatek,mt8188-hdmi-phymediatek,mt8195-hdmi-phy3&:pll_ref hdmi_txpll     xdisabled}dsi-phy@11c800000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx3: mipi_tx0_pll  xokay}dsi-phy@11c900000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx3: mipi_tx0_pll   xdisabled}i2c@11e00000mediatek,mt8188-i2c "[ )3&7 :maindma+xokaypdefault~i2c@11e01000mediatek,mt8188-i2c "[ )3&7 :maindma+xokaypdefault~clock-controller@11e02000mediatek,mt8188-imp-iic-wrap-w  }t-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+xokayusb-phy@03%$ :refda_ref xokay}vt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+xokayusb-phy@03%$ :refda_ref xokay}Iusb-phy@700 3$: :refda_ref xokay}Jt-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+xokayusb-phy@03%$ :refda_ref xokay}ti2c@11ec0000mediatek,mt8188-i2c "[ )3&7 :maindma+ xdisabledi2c@11ec1000mediatek,mt8188-i2c "[ )3&7 :maindma+ xdisabledclock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-en  }efuse@11f20000,mediatek,mt8188-efusemediatek,mt8186-efuse+dp-calib@1a0 }lvts1-calib@1ac@}Fgpu-speedbin@581 }socinfo-data1@7a0socinfo-data2@7e0gpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jm@30[~} ijobmmugpu speed-bin ;;; core0core1core2cxokay #} clock-controller@13fbf000mediatek,mt8188-mfgcfg }syscon@14000000mediatek,mt8188-vppsys0syscon }(dma-controller@14001000mediatek,mt8188-mdp3-rdma 3(<  ;    *display@140020000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg 3( display@140040002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr@3(" @display@140050002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aalP[F3( ; Pdisplay@140060002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz`3(  ` %display@140070006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshpp3(# pdisplay@140080006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color[I3($; display@140090002mediatek,mt8188-mdp3-ovlmediatek,mt8195-mdp3-ovl[J3(%;  display@1400a000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding3(; display@1400b0002mediatek,mt8188-mdp3-tccmediatek,mt8195-mdp3-tcc3( display@1400c0004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot 3( ;   +mutex@1400f000mediatek,mt8188-vpp-mutex[P3(; smi@14012000mediatek,mt8188-smi-common-vpp 3((:apbsmi;}smi@14013000mediatek,mt8188-smi-larb03((:apbsmi; 7 H}iommu@14018000mediatek,mt8188-iommu-vppP3(:bclk[R;m U}dma-controller@14f09000mediatek,mt8188-mdp3-rdma 3*  ;  dma-controller@14f0a000mediatek,mt8188-mdp3-rdma 3*  ;  display@14f0c0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg3*  display@14f0d0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg3*  display@14f0f0002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr3*" display@14f100002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr3*$ display@14f120002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal [j3*#; display@14f130002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal0[k3*%; 0display@14f150002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rszP3* P display@14f160002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz`3* ` display@14f180006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp3* display@14f190006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp3* display@14f1a0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge3*; display@14f1b0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge3*; display@14f1d0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color[u3*; display@14f1e0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color[v3*; display@14f21000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding3*; display@14f22000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding 3*; display@14f240004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot@ 3* ; @ display@14f250004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrotP 3* ; P clock-controller@14e00000mediatek,mt8188-wpesys }4clock-controller@14e02000mediatek,mt8188-wpesys-vpp0  smi@14e04000mediatek,mt8188-smi-larb@344:apbsmi; 7 H}syscon@14f00000mediatek,mt8188-vppsys1syscon }*mutex@14f01000mediatek,mt8188-vpp-mutex[{3*&; smi@14f02000mediatek,mt8188-smi-larb 3**:apbsmi; 7 H}smi@14f03000mediatek,mt8188-smi-larb03**:apbsmi; 7 H}clock-controller@15000000mediatek,mt8188-imgsys clock-controller@15110000 mediatek,mt8188-imgsys1-dip-top Iclock-controller@15130000mediatek,mt8188-imgsys1-dip-nr Iclock-controller@15220000mediatek,mt8188-imgsys-wpe1" Iclock-controller@15330000mediatek,mt8188-ipesys3 Iclock-controller@15520000mediatek,mt8188-imgsys-wpe2R Iclock-controller@15620000mediatek,mt8188-imgsys-wpe3b Iclock-controller@16000000mediatek,mt8188-camsys }-clock-controller@1604f000mediatek,mt8188-camsys-rawa I}0clock-controller@1606f000mediatek,mt8188-camsys-yuva I}1clock-controller@1608f000mediatek,mt8188-camsys-rawb I}.clock-controller@160af000mediatek,mt8188-camsys-yuvb  I}/clock-controller@17200000mediatek,mt8188-ccusys  video-decoder@18000000mediatek,mt8188-vcodec-dec @` + *video-codec@10000mediatek,mtk-vcodec-lat%4"%x 3%4++%x:selvdeclattop[H ;video-codec@25000mediatek,mtk-vcodec-coreP%4"%x 3%4,,%x:selvdeclattop[X ;smi@1800d000mediatek,mt8188-smi-larb3++:apbsmi; 7 H}clock-controller@1800f000mediatek,mt8188-vdecsys-soc }+smi@1802e000mediatek,mt8188-smi-larb3,,:apbsmi; 7 H}clock-controller@1802f000mediatek,mt8188-vdecsys },clock-controller@1a000000mediatek,mt8188-vencsys }3smi@1a010000mediatek,mt8188-smi-larb333:apbsmi; 7 H}video-encoder@1a020000mediatek,mt8188-vcodec-enc+%3"%p33 :venc_sel[aX ; *jpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgenc33:jpgenc[b ;jpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdec333:jpgdec-smijpgdec[c0 ;ovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovl3)[| ; ports+port@0endpoint ?}port@1endpoint ?}rdma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdma 3)[~ ;  ports+port@0endpoint ?}port@1endpoint ?}color@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-color03)[; 0ports+port@0endpoint ?}port@1endpoint ?}ccorr@1c0040006mediatek,mt8188-disp-ccorrmediatek,mt8192-disp-ccorr@3)[; @ports+port@0endpoint ?}port@1endpoint ?}aal@1c0050002mediatek,mt8188-disp-aalmediatek,mt8183-disp-aalP3) [; Pports+port@0endpoint ?}port@1endpoint ?}gamma@1c0060006mediatek,mt8188-disp-gammamediatek,mt8195-disp-gamma`3)[; `ports+port@0endpoint ?}port@1endpoint ?}dither@1c0070008mediatek,mt8188-disp-dithermediatek,mt8183-disp-ditherp3)[; pports+port@0endpoint ?}port@1endpoint ?}dsi@1c008000mediatek,mt8188-dsi3)):enginedigitalhs[+ ~dphy;)xokay+ports+port@0endpoint ?}port@1endpoint ?}pdsc@1c0090002mediatek,mt8188-disp-dscmediatek,mt8195-disp-dsc3) [; dsi@1c012000mediatek,mt8188-dsi 3) ):enginedigitalhs[+ ~dphy;)  xdisabledmerge0@1c0140006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge@3) 2:mergemerge_async[; @dp-intf@1c015000mediatek,mt8188-dp-intfP3) ) $:pixelenginepll[; xdisabledmutex@1c016000mediatek,mt8188-disp-mutex`3)[; ` >postmask@1c01a000<mediatek,mt8188-disp-postmaskmediatek,mt8192-disp-postmask3)[; ports+port@0endpoint ?}port@1endpoint ?}syscon@1c01d000mediatek,mt8188-vdosys0syscon I  })port+endpoint@0 ?}smi@1c022000mediatek,mt8188-smi-larb 3)):apbsmi; 7 H}smi@1c023000mediatek,mt8188-smi-larb03)):apbsmi; 7 H}smi@1c024000mediatek,mt8188-smi-common-vdo@3)):apbsmi;}iommu@1c028000mediatek,mt8188-iommu-vdoP3):bclk[;m U}syscon@1c100000mediatek,mt8188-vdosys1syscon I  }2mutex@1c101000mediatek,mt8188-disp-mutex32[;  smi@1c102000mediatek,mt8188-smi-larb 322:apbsmi; 7 H}smi@1c103000mediatek,mt8188-smi-larb0322:apbsmi; 7 H}rdma@1c1040004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma@32[ @;  @rdma@1c1050004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaP32[ `;  Prdma@1c1060004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma`32[ A;  `rdma@1c1070004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmap32[ a;  prdma@1c1080004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma32[ B;  rdma@1c1090004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma32[ b;  rdma@1c10a0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma32[ C;  rdma@1c10b0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma32[ c;  merge@1c10c0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge32 2:mergemerge_async[;2  dmerge@1c10d0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge32 2:mergemerge_async[;2  dmerge@1c10e0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge32 2:mergemerge_async[;2  dmerge@1c10f0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge32 2:mergemerge_async[;2  dmerge@1c1100006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge32 2:mergemerge_async[;2  xdpi@1c112000(mediatek,mt8188-dpimediatek,mt8195-dpi 32822=:pixelenginepll[ ;2 xdisabledports+port@0endpointport@1endpointdp-intf@1c113000mediatek,mt8188-dp-intf032:2$:pixelenginepll[; xdisabledethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrp@Pp4Vmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsh3202+2.2,2/2-2<2122232425%:mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top[6 de;(2122232425p @Pppadding@1c11d000mediatek,mt8188-disp-padding32; padding@1c11e000mediatek,mt8188-disp-padding32 ; padding@1c11f000mediatek,mt8188-disp-padding32!; padding@1c120000mediatek,mt8188-disp-padding32"; padding@1c121000mediatek,mt8188-disp-padding32#; padding@1c122000mediatek,mt8188-disp-padding 32$;  padding@1c123000mediatek,mt8188-disp-padding032%; 0padding@1c124000mediatek,mt8188-disp-padding@32&; @hdmi@1c300000mediatek,mt8188-hdmi-tx0 3%@%>%?*.:bushdcphdcp24mhdmi-split%>"%s[; + ~hdmi xdisabledi2c2mediatek,mt8188-hdmi-ddcmediatek,mt8195-hdmi-ddc3:ports+port@0endpointport@1endpointedp-tx@1c500000mediatek,mt8188-edp-txP[dp_calibration_data;  xdisableddp-tx@1c600000mediatek,mt8188-dp-tx`[dp_calibration_data;  xdisabledbacklight-lcd0pwm-backlight    " u0}chosen serial0:115200n8firmwareopteelinaro,optee-tzsmcmemory@40000000memory@panel-dsi0tianma,tm070jdhg30  lportendpoint ?}qreserved-memory+optee@43200000 C memory@50000000shared-dma-poolP }9memory@54600000 T` memory@55000000shared-dma-poolU@memory@57000000shared-dma-poolW@memory@60000000shared-dma-pool` }Amemory@60f00000shared-dma-pool` }=memory@61000000shared-dma-poola }@regulator-efuseregulator-outputregulator-1v8regulator-fixedreg_1v8w@w@B}jregulator-3v3regulator-fixedreg_3v32Z2ZB}kregulator-5vregulator-fixedreg_5vLK@LK@B}lregulator-sdcard-enregulator-fixedBsdcard_en_3v32Z2Z "o}\regulator-usb-p0-vbusregulator-fixedvbus_p0LK@LK@ "T}xregulator-usb-p1-vbusregulator-fixedpdefault~vbus_p1w@w@ "}Nregulator-usb-p2-vbusregulator-fixedpdefault~vbus_p2w@w@ "P}uwifi-pwrseqmmc-pwrseq-simplepdefault~0 3"Y}b compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dpi1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7dsi0ethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6mmc0mmc1mmc2rtc0rtc1serial0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellscpu-supplyphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-downinput-enabledrive-strengthbias-pull-upoutput-highinput-disablebias-disabledrive-strength-microampoutput-low#power-domain-cellsdomain-supplyclocksclock-namesmediatek,infracfgmediatek,disable-extrstpinctrl-namespinctrl-0#sound-dai-cellsinterrupts-extended#io-channel-cellsmediatek,mic-type-0mediatek,mic-type-1regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-boot-onregulator-coupled-withregulator-coupled-max-spreadmediatek,long-press-modepower-off-time-seclinux,keycodeswakeup-sourceassigned-clocksassigned-clock-parentsregulator-on-in-suspendregulator-suspend-microvolt#iommu-cells#mbox-cellsmemory-regionpower-domainsresetsreset-namesmediatek,topckgenmboxesmbox-namesmediatek,pad-selectnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsphysmediatek,syscon-wakeupdr_modevusb33-supplyvbus-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlepinctrl-1mediatek,mac-wolsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ussnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymax-frequencymmc-hs200-1_8vmmc-hs400-1_8vnon-removableno-sdno-sdiosupports-cqevmmc-supplyvqmmc-supplycap-sd-highspeedsd-uhs-sdr104sd-uhs-sdr50cd-gpioscap-sdio-irqkeep-power-in-suspendno-mmcpinctrl-2mmc-pwrseqclock-divreset-gpiosremote-endpointAVDD-supplyCPVDD-supplyDBVDD-supplyDCVDD-supplyMICVDD-supplyPLLVDD-supplySPKVDD1-supplySPKVDD2-supplygpio-cfgenable-gpiosdata-lanesirq-gpiosmaximum-speedmicrochip,led-modesusb-role-switchlabeldata-rolebus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-names#phy-cellsmediatek,ibiasmediatek,ibias_upbitsoperating-points-v2power-domain-namesmali-supply#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzbrightness-levelsdefault-brightness-levelnum-interpolated-stepspwmsstdout-pathbacklightpower-supplyno-mapvout-supplyenable-active-highpost-power-on-delay-ms