Ð þí4ß83¸('3€"renesas,ironhiderenesas,r8a78000 &)7Renesas Ironhide board based on r8a78000cpus cpu-mapcluster0core0=core1=core2=core3=cluster1core0=core1=core2=core3= cluster2core0= core1= core2= core3= cluster3core0=core1=core2=core3=cluster4core0=core1=core2=core3=cluster5core0=core1=core2=core3=cluster6core0=core1=core2=core3=cluster7core0=core1=core2= core3=!cpu@0arm,cortex-a720aeAEcpuQ"bcpu@100arm,cortex-a720aeAEcpuQ#bcpu@200arm,cortex-a720aeAEcpuQ$bcpu@300arm,cortex-a720aeAEcpuQ%bcpu@10000arm,cortex-a720aeAEcpuQ&bcpu@10100arm,cortex-a720aeAEcpuQ'bcpu@10200arm,cortex-a720aeAEcpuQ(bcpu@10300arm,cortex-a720aeAEcpuQ)b cpu@20000arm,cortex-a720aeAEcpuQ*b cpu@20100arm,cortex-a720aeAEcpuQ+b cpu@20200arm,cortex-a720aeAEcpuQ,b cpu@20300arm,cortex-a720aeAEcpuQ-b cpu@30000arm,cortex-a720aeAEcpuQ.bcpu@30100arm,cortex-a720aeAEcpuQ/bcpu@30200arm,cortex-a720aeAEcpuQ0bcpu@30300arm,cortex-a720aeAEcpuQ1bcpu@40000arm,cortex-a720aeAEcpuQ2bcpu@40100arm,cortex-a720aeAEcpuQ3bcpu@40200arm,cortex-a720aeAEcpuQ4bcpu@40300arm,cortex-a720aeAEcpuQ5bcpu@50000arm,cortex-a720aeAEcpuQ6bcpu@50100arm,cortex-a720aeAEcpuQ7bcpu@50200arm,cortex-a720aeAEcpuQ8bcpu@50300arm,cortex-a720aeAEcpuQ9bcpu@60000arm,cortex-a720aeAEcpuQ:bcpu@60100arm,cortex-a720aeAEcpuQ;bcpu@60200arm,cortex-a720aeAEcpuQ<bcpu@60300arm,cortex-a720aeAEcpuQ=bcpu@70000arm,cortex-a720aeAEcpuQ>bcpu@70100arm,cortex-a720aeAEcpuQ?bcpu@70200arm,cortex-a720aeAEcpuQ@b cpu@70300arm,cortex-a720aeAEcpuQAb!cache-controller-200cachejxQBb"cache-controller-201cachejxQBb#cache-controller-202cachejxQBb$cache-controller-203cachejxQBb%cache-controller-204cachejxQCb&cache-controller-205cachejxQCb'cache-controller-206cachejxQCb(cache-controller-207cachejxQCb)cache-controller-208cachejxQDb*cache-controller-209cachejxQDb+cache-controller-210cachejxQDb,cache-controller-211cachejxQDb-cache-controller-212cachejxQEb.cache-controller-213cachejxQEb/cache-controller-214cachejxQEb0cache-controller-215cachejxQEb1cache-controller-216cachejxQFb2cache-controller-217cachejxQFb3cache-controller-218cachejxQFb4cache-controller-219cachejxQFb5cache-controller-220cachejxQGb6cache-controller-221cachejxQGb7cache-controller-222cachejxQGb8cache-controller-223cachejxQGb9cache-controller-224cachejxQHb:cache-controller-225cachejxQHb;cache-controller-226cachejxQHb<cache-controller-227cachejxQHb=cache-controller-228cachejxQIb>cache-controller-229cachejxQIb?cache-controller-230cachejxQIb@cache-controller-231cachejxQIbAcache-controller-30cachejxbBcache-controller-31cachejxbCcache-controller-32cachejxbDcache-controller-33cachejxbEcache-controller-34cachejxbFcache-controller-35cachejxbGcache-controller-36cachejxbHcache-controller-37cachejxbIdummy-clk-sgasyncd16 fixed-clock„‘ù>bJdummy-clk-sgasyncd4 fixed-clock„‘äè bKextal-clk fixed-clock„‘þOèextalr-clk fixed-clock„‘€scif-clk fixed-clock„‘Œº€bLsoc simple-bus ¡chipid@189e0044 renesas,prrAžDinterrupt-controller@39000000 arm,gic-v3¨ ¹ A99€ Î bserial@c0700000:renesas,scif-r8a78000renesas,rcar-gen5-scifrenesas,scifAÀp@ Î  ÙJKLàfckbrg_intscif_clk ìdisabledserial@c0704000:renesas,scif-r8a78000renesas,rcar-gen5-scifrenesas,scifAÀp@@ Î  ÙJKLàfckbrg_intscif_clk ìdisabledserial@c0708000:renesas,scif-r8a78000renesas,rcar-gen5-scifrenesas,scifAÀp€@ Î  ÙJKLàfckbrg_intscif_clk ìdisabledserial@c070c000:renesas,scif-r8a78000renesas,rcar-gen5-scifrenesas,scifAÀpÀ@ Î  ÙJKLàfckbrg_intscif_clk ìdisabledserial@c0710000=renesas,hscif-r8a78000renesas,rcar-gen5-hscifrenesas,hscifAÀq` Î ÙKKLàfckbrg_intscif_clkìokayóserial@c0714000=renesas,hscif-r8a78000renesas,rcar-gen5-hscifrenesas,hscifAÀq@` Î ÙKKLàfckbrg_intscif_clk ìdisabledserial@c0718000=renesas,hscif-r8a78000renesas,rcar-gen5-hscifrenesas,hscifAÀq€` Î ÙKKLàfckbrg_intscif_clk ìdisabledserial@c071c000=renesas,hscif-r8a78000renesas,rcar-gen5-hscifrenesas,hscifAÀqÀ` Î ÙKKLàfckbrg_intscif_clk ìdisabledtimerarm,armv8-timer<Î    %sec-physphysvirthyp-physhyp-virtaliases/soc/serial@c0710000chosenserial0:1843200n8memory@60600000EmemoryA``_ memory@1080000000EmemoryA€€memory@1200000000EmemoryAmemory@1400000000EmemoryAmemory@1600000000EmemoryAmemory@1800000000EmemoryAmemory@1a00000000EmemoryAmemory@1c00000000EmemoryAmemory@1e00000000EmemoryA compatible#address-cells#size-cellsinterrupt-parentmodelcpuregdevice_typenext-level-cachephandlecache-unifiedcache-level#clock-cellsclock-frequencyranges#interrupt-cellsinterrupt-controllerinterruptsclocksclock-namesstatusuart-has-rtsctsinterrupt-namesserial0stdout-path