8(t'tsd,px30-ringneck-haikourockchip,px30 +07Theobroma Systems PX30-uQ7 SoM on Haikou devkitpanelX%ON~Avesa-247Badmatec,9904379panel-lvdsBportendpoint1F{Cpanel-timing   XZuZiZaO`backlight-lvds1B2a%Opwm-backlight=aliases=/i2c@ff180000B/i2c@ff190000G/i2c@ff1a0000L/i2c@ff1b0000Q/serial@ff030000Y/serial@ff158000a/serial@ff160000i/serial@ff168000q/serial@ff170000y/serial@ff178000/spi@ff1d0000/spi@ff1d8000#/i2c@ff190000/fan@18/i2c-mux/i2c@0/mmc@ff390000/mmc@ff380000*/i2c@ff190000/fan@18/i2c-mux/i2c@0/rtc@6f/i2c@ff180000/pmic@20/ethernet@ff360000/mmc@ff370000cpus+cpu@0cpuarm,cortex-a35psciZ&1cpu@1cpuarm,cortex-a35psciZ&1cpu@2cpuarm,cortex-a35psciZ&1 cpu@3cpuarm,cortex-a35psciZ&1 idle-states9pscicpu-sleeparm,idle-stateFWnx1cluster-sleeparm,idle-stateFWn1opp-table-0operating-points-v21opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem okayled1external-gmac-clock fixed-clock gmac_clkin+1psci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zones1soc-thermal8N\n 1tripstrip-point-0~ppassive1trip-point-1~Lpassive1soc-crit~8 critical1cooling-mapsmap0 gpu-thermal8dNn 1tripsgpu-threshold~ppassive1gpu-target~Lpassive1gpu-crit~8 critical1cooling-mapsmap0 xin24m fixed-clock+n6xin24m1gpower-management@ff000000$rockchip,px30-pmusysconsimple-mfd1power-controllerrockchip,px30-power-controller+1ipower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"#power-domain@14I$syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd1io-domains$rockchip,px30-pmu-io-voltage-domainokay%%1reboot-modesyscon-reboot-modeRBRB RBRB*RBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart &&8baudclkapb_pclkD''ItxrxS]jdefaultx(okay1i2s@ff060000rockchip,px30-i2s-tdm  8mclk_txmclk_rxhclkD''Itxrx) tx-mrx-mjdefaultx*+,-okay1i2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  8i2s_clki2s_hclkD''Itxrxjdefaultx./01 disabled1i2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s 8i2s_clki2s_hclkD''Itxrxjdefaultx2345 disabled1interrupt-controller@ff131000 arm,gic-400@ @ `   1syscon@ff140000$rockchip,px30-grfsysconsimple-mfd1)io-domains rockchip,px30-io-voltage-domainokay%6%%,%:7H%1lvdsrockchip,px30-lvds\8adphy)klvdsokayled1ports+port@0+1endpoint@0{91endpoint@1{:1port@11endpoint1C{Fserial@ff158000$rockchip,px30-uartsnps,dw-apb-uart I8baudclkapb_pclkD''ItxrxS]jdefault x;<= disabled1serial@ff160000$rockchip,px30-uartsnps,dw-apb-uart J8baudclkapb_pclkD''ItxrxS]jdefaultx> disabled1serial@ff168000$rockchip,px30-uartsnps,dw-apb-uart K8baudclkapb_pclkD''ItxrxS]jdefault x?@A disabled1serial@ff170000$rockchip,px30-uartsnps,dw-apb-uart L8baudclkapb_pclkD'' ItxrxS]jdefault xBCD disabled1serial@ff178000$rockchip,px30-uartsnps,dw-apb-uart M8baudclkapb_pclkS]jdefaultxEFokay G 1i2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN 8i2cpclk jdefaultxH+okay1pmic@20rockchip,rk809  GxIjdefault+xin32kJJJJ%%%J1regulatorsDCDC_REG1vdd_log*~BpZqo1regulator-state-mem~DCDC_REG2vdd_arm*~BpZqo1regulator-state-mem~DCDC_REG3vcc_ddro1regulator-state-memDCDC_REG4 vcc_3v0_1v8*w@B-o17regulator-state-mem-DCDC_REG5vcc_3v3*2ZB2Zo1%regulator-state-mem2ZLDO_REG2vcc_1v8*w@Bw@o1fregulator-state-memw@LDO_REG3vcc_1v0*B@BB@o1regulator-state-memB@LDO_REG5 vccio_sd*w@B2Zo16regulator-state-mem2ZLDO_REG7o*B@BB@vcc_lcd1regulator-state-memB@LDO_REG8 vcc_1v8_lcd*w@Bw@o1regulator-state-memw@LDO_REG9 vcca_1v8*w@Bw@o1regulator-state-memw@SWITCH_REG1vg_attiny_updi1i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO 8i2cpclk jdefaultxK+okay1eeprom@54O st,24c04atmel,24c04en@Ttouchscreen@14OOjdefaultxDE G G G goodix,gt928fan@18tsd,muleti,amc68211i2c-muxtsd,mule-i2c-mux+i2c@0+1rtc@6f isil,isl1208o1i2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP 8i2cpclk  jdefaultxL+okay1codec@a fsl,sgtl5000 MNOP1i2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q 8i2cpclk  jdefaultxQ+okay1eeprom@50P atmel,24c01 Ospi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $U8spiclkapb_pclkD' ' ItxrxjdefaultxRSTU+ disabled1spi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %V8spiclkapb_pclkD''ItxrxjdefaultxVWXYZ+okay"[ [ 1watchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ %okay1pwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S 8pwmpclkjdefaultx\+okay1pwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S 8pwmpclkjdefaultx]+ disabled1pwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S 8pwmpclkjdefaultx^+ disabled1pwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S 8pwmpclkjdefaultx_+ disabled1pwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T 8pwmpclkjdefaultx`+ disabled1pwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T 8pwmpclkjdefaultxa+ disabled1pwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T 8pwmpclkjdefaultxb+ disabled1pwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T 8pwmpclkjdefaultxc+ disabled1timer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& 8pclktimer1dma-controller@ff240000arm,pl330arm,primecell$@6 8apb_pclkM1'tsadc@ff280000rockchip,px30-tsadc( $X,hP,X8tsadcapb_pclk tsadc-apb)}jinitdefaultsleepxdedokay1 saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( T-W8saradcapb_pclk saradc-apbokayf1nvmem@ff290000rockchip,px30-otp)@/Za8otpapb_pclkphyphy+1id@71cpu-leakage@171performance@1e1clock-controller@ff2b0000rockchip,px30-cru+ g& 8xin24mgpll)+8X@IhFq рр 1clock-controller@ff2bc000rockchip,px30-pmucru+g8xin24m)+X&&& hG1&syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+1usb2phy@100rockchip,px30-usb2phy & 8phyclk+Xh usb480m_phyokay1hhost-port D linestateokay1kotg-port$BA@otg-bvalidotg-idlinestateokay1jphy@ff2e0000rockchip,px30-dsi-dphy.& E 8refpclk>apb i okayled18phy@ff2f0000rockchip,px30-csi-dphy/@F8pclk i /apb) disabled1usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >8otg.otg6HW@ \j ausb2-phy iokay1usb@ff340000 generic-ehci4 <\kausb iokay1usb@ff350000 generic-ohci5 =\kausb iokay1ethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[8stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed)frmiijdefaultxlm i ^ stmmacethokayonz%output1mdiosnps,dwmac-mdio+1ethernet-phy@0ethernet-phy-ieee802.3-c22jdefaultxoPP [1nmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CD8biuciuciu-driveciu-sampleрjdefaultxpqrs iokay6 ) :GCNO1mmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EF8biuciuciu-driveciu-sampleрjdefault xtuv i  disabled1mmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GH8biuciuciu-driveciu-sampleрjdefault xwxy i okayZiztN%71spi@ff3a0000 rockchip,sfc:@ 8:8clk_sfchclk_sfc x{|}jdefault i  disabled1nand-controller@ff3b0000rockchip,px30-nfc;@ 978ahbnfcX7hрjdefault x~ i  disabled1opp-table-1operating-points-v21opp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuI iokay1video-codec@ff442000rockchip,px30-vpuD PO vepuvdpu 8aclkhclk i 1iommu@ff442800rockchip,iommuD( Q 8aclkiface i 1dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsiE KD8pclk\8adphy i =apb) disabled1ports+port@0+1endpoint@0{1endpoint@1{1port@11vop@ff460000rockchip,px30-vop-bigF M8aclk_vopdclk_vophclk_vop345 axiahbdclk i okayled1port+1 endpoint@0{1endpoint@1{19iommu@ff460f00rockchip,iommuF M 8aclkiface i okayled1vop@ff470000rockchip,px30-vop-litG N8aclk_vopdclk_vophclk_vop789 axiahbdclk i okayled1port+1 endpoint@0{1endpoint@1{1:iommu@ff470f00rockchip,iommuG N 8aclkiface i okayled1video-capture@ff490000rockchip,px30-vipI E`8aclkhclkpclk i ,-.axiahbpclkin disabled1isp@ff4a0000rockchip,px30-cif-ispJ$FIJ ispmimipi 3_8ispaclkhclkpclk\adphy i  disabled1ports+port@01iommu@ff4a8000rockchip,iommuJ F 8aclkiface i 1qos@ff518000rockchip,px30-qossysconQ 1qos@ff520000rockchip,px30-qossysconR 1$qos@ff52c000rockchip,px30-qossysconR 1qos@ff538000rockchip,px30-qossysconS 1qos@ff538080rockchip,px30-qossysconS 1qos@ff538100rockchip,px30-qossysconS 1qos@ff538180rockchip,px30-qossysconS 1qos@ff540000rockchip,px30-qossysconT 1qos@ff540080rockchip,px30-qossysconT 1qos@ff548000rockchip,px30-qossysconT 1qos@ff548080rockchip,px30-qossysconT 1 qos@ff548100rockchip,px30-qossysconT 1!qos@ff548180rockchip,px30-qossysconT 1"qos@ff548200rockchip,px30-qossysconT 1#qos@ff550000rockchip,px30-qossysconU 1qos@ff550080rockchip,px30-qossysconU 1qos@ff550100rockchip,px30-qossysconU 1qos@ff550180rockchip,px30-qossysconU 1qos@ff558000rockchip,px30-qossysconU 1qos@ff558080rockchip,px30-qossysconU 1pinctrlrockchip,px30-pinctrl)+1touchtouch-rst1E ktouch-int1D kgpio@ff040000rockchip,gpio-bank &1Ggpio@ff250000rockchip,gpio-bank% \1gpio@ff260000rockchip,gpio-bank& ]1bios-disable-override-hog bios_disable_overridebios-disable-n-hog bios_disable gpio@ff270000rockchip,gpio-bank' ^1[pcfg-pull-up 1pcfg-pull-down 1pcfg-pull-none "1pcfg-pull-none-2ma " /1pcfg-pull-up-2ma  /1pcfg-pull-up-4ma  /1pcfg-pull-none-4ma " /1pcfg-pull-down-4ma  /1pcfg-pull-none-8ma " /1pcfg-pull-up-8ma  /1pcfg-pull-none-12ma " / 1pcfg-pull-up-12ma  / 1pcfg-pull-none-smt " >1pcfg-output-high1pcfg-output-low S1pcfg-input-high  ^1pcfg-input ^1i2c0i2c0-xfer k 1Hi2c1i2c1-xfer k1Ki2c2i2c2-xfer k1Li2c3i2c3-xfer k  1Qtsadctsadc-otp-pin k1dtsadc-otp-out k1euart0uart0-xfer k  1(uart0-cts k 1uart0-rts k 1uart1uart1-xfer k1;uart1-cts k1<uart1-rts k1=uart2-m0uart2m0-xfer k1>uart2-m1uart2m1-xfer k 1uart3-m0uart3m0-xfer k1uart3m0-cts k1uart3m0-rts k1uart3-m1uart3m1-xfer k1?uart3m1-cts k 1@uart3m1-rts k 1Auart4uart4-xfer k1Buart4-cts k1Cuart4-rts k1Duart5uart5-xfer k1Euart5-cts k1uart5-rts k1spi0spi0-clk k1Rspi0-csn k1Sspi0-miso k 1Tspi0-mosi k 1Uspi0-clk-hs k1spi0-miso-hs k 1spi0-mosi-hs k 1spi1spi1-clk k1Vspi1-csn0 k 1spi1-csn1 k 1spi1-miso k1Yspi1-mosi k 1Zspi1-clk-hs k1spi1-miso-hs k1 spi1-mosi-hs k 1 spi1-csn0-gpio-pin k 1Wspi1-csn1-gpio-pin k 1Xpdmpdm-clk0m0 k1 pdm-clk0m1 k1 pdm-clk1 k1 pdm-sdi0m0 k1pdm-sdi0m1 k1pdm-sdi1 k1pdm-sdi2 k1pdm-sdi3 k1pdm-clk0m0-sleep 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