8(d ,anbernic,rg-dsrockchip,rk35687Anbernic RG DS=handsetaliasesJ/pinctrl/gpio@fdd60000P/pinctrl/gpio@fe740000V/pinctrl/gpio@fe750000\/pinctrl/gpio@fe760000b/pinctrl/gpio@fe770000h/i2c@fdd40000m/i2c@fe5a0000r/i2c@fe5b0000w/i2c@fe5c0000|/i2c@fe5d0000/i2c@fe5e0000/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/mmc@fe310000/mmc@fe2b0000/mmc@fe000000cpus cpu@0cpu,arm,cortex-a55 psci-:@LYf@x cpu@100cpu,arm,cortex-a55 psci-:@LYf@x cpu@200cpu,arm,cortex-a55 psci-:@LYf@x cpu@300cpu,arm,cortex-a55 psci-:@LYf@x l3-cache,cache/<@Ndisplay-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc݂ protocol@14hdmi-sound,simple-audio-cardHDMIi2s+ Edisabledsimple-audio-card,codecLsimple-audio-card,cpuL pmu,arm,cortex-a55-pmu0Va psci ,arm,psci-1.0&smcreserved-memory tshmem@10f000,arm,scmi-shmem{timer,arm,armv8-timer0V   xin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32kdefaultsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@ satapmaliverxoob V_ sata-phy Edisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci satapmaliverxoob V` sata-phy Edisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ V ref_clksuspend_clkbus_clk peripheral utmi_wide 'Eokay usb2-phy @high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ V ref_clksuspend_clkbus_clkhost usb2-phyusb3-phy utmi_wide ' Edisabledinterrupt-controller@fd400000 ,arm,gic-v3 @F V NctA~(t msi-controller@fd440000,arm,gic-v3-itsDnusb@fd800000 ,generic-ehci V usbEokayusb@fd840000 ,generic-ohci V usbEokayusb@fd880000 ,generic-ehci V usb Edisabledusb@fd8c0000 ,generic-ohci V usb Edisabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdlio-domains&,rockchip,rk3568-pmu-io-voltage-domainEokaysyscon@fdc50000 ,rockchip,rk3568-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru#clock-controller@fdd20000,rockchip,rk3568-cru xin24m# 0@G o2 Uli2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c V. - i2cpclkdefault Eokaypmic@20,rockchip,rk817 U0Hmclkrk808-clkout1rk808-clkout2 H V!"defaulty########$regulatorsDCDC_REG10BYpq  vdd_logicqregulator-state-mem DCDC_REG20BYpq vdd_gpuqHregulator-state-memDCDC_REG30Bvcc_ddrregulator-state-memDCDC_REG40BY2Zq2Zvcc_3v3regulator-state-mem2ZLDO_REG10Yw@qw@ vcca1v8_pmuregulator-state-memw@LDO_REG20Y q  vdda_0v9regulator-state-memLDO_REG30Y q  vdda0v9_pmuregulator-state-mem LDO_REG40Y2Zq2Z vccio_acodecregulator-state-memLDO_REG50Y2Zqw@ vccio_sdregulator-state-memLDO_REG60Y2Zq2Z vcc3v3_pmuregulator-state-mem2ZLDO_REG70Yw@qw@vcc_1v8regulator-state-memLDO_REG80Y2Zqw@ vcc1v8_dvpregulator-state-memLDO_REG90Y*q* vcc2v8_dvpregulator-state-memBOOST0YReqG`boost$regulator-state-memOTG_SWITCH otg_switchregulator-state-memcharger% '/IU&regulator@40,silergy,syr827@|0Y5q 4vdd_cpu#regulator-state-membattery@62,cellwise,cw2015b@goiecTuPWVNOD5,$$2AMW 4TYm<ll AM8~/dF%& Edisabledserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart Vt  ,baudclkapb_pclk''(default Edisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk)default Edisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk*default Edisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm   0 pwmpclk+default Edisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0  0 pwmpclk,default Edisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller power-domain@7 $-power-domain@8  $./0power-domain@9   $123power-domain@10  $456789power-domain@11  $:power-domain@13  $;power-domain@14  $<=>power-domain@15  $?@ABCDEFgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$V()' +jobmmugpu gpubusEokayG;Hvideo-codec@fdea0400,rockchip,rk3568-vpu V+vdpu  aclkhclkGI iommu@fdea0800,rockchip,rk3568-iommu@ V aclkiface  NIrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga VZ aclkhclksclk &$% [coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu V@  aclkhclkGJ iommu@fdee0800,rockchip,rk3568-iommu@ V?  aclkiface NJvideo-capture@fdfe0000,rockchip,rk3568-vicap V0@  aclkhclkdclkiclkGK( [arsthrstdrstprstirstl Edisabledports port@0port@1iommu@fdfe0800,rockchip,rk3568-iommu V  aclkifaceNg EdisabledKmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ Vd  biuciuciu-driveciu-sample [resetEokayL MNOdefault Pwifi@1QV +host-wakeRdefaultethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aV +macirqeth_wake_irq@ Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref  [stmmacethl S-T@US Edisabledmdio,snps,dwmac-mdio stmmac-axi-config\fvSrx-queues-configTqueue0tx-queues-configUqueue0vop@fe040000 0@vopgamma-lut V( %aclkhclkdclk_vp0dclk_vp1dclk_vp2GV lEokay,rockchip,rk3568-vop0Uports port@0 endpoint@4WZport@1 endpoint@6Xbport@2 iommu@fe043e00,rockchip,rk3568-iommu >? V  aclkifaceN EokayVdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi VDpclk dphyY [apb lEokay ports port@0endpointZWport@1endpoint[`panel@01,anbernic,rg-ds-display-bottomjadard,jd9365da-h3\]default  ^_portendpoint`[dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi VEpclk dphya [apb lEokay ports port@0endpointbXport@1endpointchpanel@0.,anbernic,rg-ds-display-topjadard,jd9365da-h3dedefault  fgportendpointhchdmi@fe0a0000,rockchip,rk3568-dw-hdmi  V-( (iahbisfrcecrefdefault ijk ly Edisabledports port@0port@1qos@fe128000,rockchip,rk3568-qossyscon -qos@fe138080,rockchip,rk3568-qossyscon <qos@fe138100,rockchip,rk3568-qossyscon =qos@fe138180,rockchip,rk3568-qossyscon >qos@fe148000,rockchip,rk3568-qossyscon .qos@fe148080,rockchip,rk3568-qossyscon /qos@fe148100,rockchip,rk3568-qossyscon 0qos@fe150000,rockchip,rk3568-qossyscon :qos@fe158000,rockchip,rk3568-qossyscon 4qos@fe158100,rockchip,rk3568-qossyscon 5qos@fe158180,rockchip,rk3568-qossyscon 6qos@fe158200,rockchip,rk3568-qossyscon 7qos@fe158280,rockchip,rk3568-qossyscon 8qos@fe158300,rockchip,rk3568-qossyscon 9qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon ?qos@fe190280,rockchip,rk3568-qossyscon Cqos@fe190300,rockchip,rk3568-qossyscon Dqos@fe190380,rockchip,rk3568-qossyscon Eqos@fe190400,rockchip,rk3568-qossyscon Fqos@fe198000,rockchip,rk3568-qossyscon ;qos@fe1a8000,rockchip,rk3568-qossyscon 1qos@fe1a8080,rockchip,rk3568-qossyscon 2qos@fe1a8100,rockchip,rk3568-qossyscon 3dfi@fe230000,rockchip,rk3568-dfi# V lpcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<VKJIHG+syspmcmsglegacyerr ( $aclk_mstaclk_slvaclk_dbipclkauxpcic ` $mmmm 2 C R a pn x pcie-phyTt @ [pipe  Edisabledlegacy-interrupt-controllercN VHmmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ Vb  biuciuciu-driveciu-sampleр [resetEokay  opqrdefaults mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ Vc  biuciuciu-driveciu-sampleр [reset Edisabledspi@fe300000 ,rockchip,sfc0@ Ve xvclk_sfchclk_sfctdefault Edisabledmmc@fe310000,rockchip,rk3568-dwcmshc1 V0{}@ n6( |zy{}corebusaxiblocktimerEokay   uvwxydefaultrng@fe388000,rockchip,rk3568-rng8@ po coreahb mEokayi2s@fe400000,rockchip,rk3568-i2s-tdm@ V40=A@FqFq ?C9mclk_txmclk_rxhclkz tx PQ [tx-mrx-mly Edisabled i2s@fe410000,rockchip,rk3568-i2s-tdmA V50EI@FqFq GK:mclk_txmclk_rxhclkzz rxtx RS [tx-mrx-mldefault{|}~yEokay i2s@fe420000,rockchip,rk3568-i2s-tdmB V60M@Fq OO;mclk_txmclk_rxhclkzz txrx T[tx-mldefaulty Edisabledi2s@fe430000,rockchip,rk3568-i2s-tdmC V7 SW<mclk_txmclk_rxhclkzz txrx UV [tx-mrx-mly Edisabledpdm@fe440000,rockchip,rk3568-pdmD VL ZYpdm_clkpdm_hclkz  rxdefault X[pdm-my Edisabledspdif@fe460000,rockchip,rk3568-spdifF Vf mclkhclk _\z txdefaulty Edisableddma-controller@fe530000,arm,pl330arm,primecellS@V     apb_pclk 'dma-controller@fe550000,arm,pl330arm,primecellU@V    apb_pclk zi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ V/ HG i2cpclkdefault  Edisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ V0 JI i2cpclkdefault Eokay @i2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ V1 LK i2cpclkdefault Eokaytouchscreen@14 ,goodix,gt911  V       ) < Sdefault ji2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] V2 NM i2cpclkdefault  Edisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ V3 PO i2cpclkdefault Eokaytouchscreen@14 ,goodix,gt911  V       )default jwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt` V  tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia Vg RQspiclkapb_pclk'' txrxdefault   Edisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib Vh TSspiclkapb_pclk'' txrxdefault   Edisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic Vi VUspiclkapb_pclk'' txrxdefault   Edisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid Vj XWspiclkapb_pclk'' txrxdefault   Edisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte Vu baudclkapb_pclk'' defaultEokay wbluetooth*,realtek,rtl8821cs-btrealtek,rtl8723bs-bt   serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf Vv # baudclkapb_pclkdefaultEokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg Vw '$baudclkapb_pclk''default Edisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth Vx +(baudclkapb_pclk'' default Edisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti Vy /,baudclkapb_pclk' ' default Edisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj Vz 30baudclkapb_pclk' ' default Edisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk V{ 74baudclkapb_pclk''default Edisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl V| ;8baudclkapb_pclk''default Edisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm V} ?<baudclkapb_pclk''default Edisabledthermal-zonescpu-thermal d  tripscpu_alert0 p Epassivecpu_alert1 $ Epassivecpu_crit s  Ecriticalcooling-mapsmap0 0  gpu-thermal   tripsgpu-threshold p Epassivegpu-target $ Epassivegpu-crit s  Ecriticalcooling-mapsmap0  tsadc@fe710000,rockchip,rk3568-tsadcq Vs0@f@ ` tsadcapb_pclk l sdefaultsleep , 6Eokay L csaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr V] saradcapb_pclk  [saradc-apb ~Eokay pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefault Edisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefaultEokaypwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn  ZY pwmpclkdefaultEokaypwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0 ZY pwmpclkdefaultEokaypwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefault Edisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefault Edisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo  ]\ pwmpclkdefault Edisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0 ]\ pwmpclkdefault Edisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefaultEokaypwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefaultEokaypwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp  `_ pwmpclkdefaultEokaypwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0 `_ pwmpclkdefault Edisabledphy@fe830000,rockchip,rk3568-naneng-combphy "} refapbpipe0"@ [phy    Edisabledphy@fe840000,rockchip,rk3568-naneng-combphy %~ refapbpipe0%@ [phy    Edisabledphy@fe870000,rockchip,rk3568-csi-dphy ypclk  [apbl Edisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclk z  [apb EokayYmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk {  [apb Eokayausb2phy@fe8a0000,rockchip,rk3568-usb2phy phyclkclk_usbphy0_480m V Eokayhost-port  Edisabledotg-port Eokayusb2phy@fe8b0000,rockchip,rk3568-usb2phy phyclkclk_usbphy1_480m V Eokayhost-port  Edisabledotg-port Eokaypinctrl,rockchip,rk3568-pinctrlll tgpio@fdd60000,rockchip,gpio-bank V! .    Nc gpio@fe740000,rockchip,gpio-bankt V" cd   Ncgpio@fe750000,rockchip,gpio-banku V# ef  @  Ncgpio@fe760000,rockchip,gpio-bankv V$ gh  `  Ncgpio@fe770000,rockchip,gpio-bankw V% ij   NcQpcfg-pull-up pcfg-pull-down pcfg-pull-none #pcfg-pull-none-drv-level-1 # 0pcfg-pull-none-drv-level-2 # 0pcfg-pull-none-drv-level-3 # 0pcfg-pull-up-drv-level-1  0pcfg-pull-up-drv-level-2  0pcfg-pull-none-smt # ?pcfg-output-low Tacodecaudiopwmbt656bt1120camcan0can0m0-pins _  can1can1m0-pins _can2can2m0-pins _  cifclk32kclk32k-out0 _cpuebcedpdpemmcemmc-rstnout _yemmc-bus8 _  uemmc-clk _vemmc-cmd _wemmc-datastrobe _xeth0eth1flashfspifspi-pins` _tgmac0gmac1gpuhdmitxhdmitxm0-cec _khdmitx-scl _ihdmitx-sda _ji2c0i2c0-xfer _  i2c1i2c1-xfer _  i2c2i2c2m1-xfer _  i2c3i2c3m1-xfer _ i2c4i2c4m0-xfer _  i2c5i2c5m0-xfer _  i2s1i2s1m0-lrcktx _|i2s1m0-mclk _!i2s1m0-sclktx _{i2s1m0-sdi0 _ }i2s1m0-sdo0 _~i2s2i2s2m0-lrcktx _i2s2m0-sclktx _i2s2m0-sdi _i2s2m0-sdo _i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk _pdmm0-clk1 _pdmm0-sdi0 _ pdmm0-sdi1 _ pdmm0-sdi2 _ pdmm0-sdi3 _pmicpmic-int-l _"pmupwm0pwm0m0-pins _)pwm1pwm1m0-pins _*pwm2pwm2m0-pins _+pwm3pwm3-pins _,pwm4pwm4-pins _pwm5pwm5-pins _pwm6pwm6-pins _pwm7pwm7-pins _pwm8pwm8m0-pins _ pwm9pwm9m0-pins _ pwm10pwm10m0-pins _ pwm11pwm11m0-pins _pwm12pwm12m1-pins _pwm13pwm13m1-pins _pwm14pwm14m0-pins _pwm15pwm15m0-pins _refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ _osdmmc0-clk _psdmmc0-cmd _qsdmmc0-det _rsdmmc1sdmmc2sdmmc2m0-bus4@ _Msdmmc2m0-clk _Nsdmmc2m0-cmd _Ospdifspdifm0-tx _spi0spi0m0-pins0 _ spi0m0-cs0 _spi0m0-cs1 _spi1spi1m0-pins0 _ spi1m0-cs0 _spi1m0-cs1 _spi2spi2m0-pins0 _spi2m0-cs0 _spi2m0-cs1 _spi3spi3m0-pins0 _  spi3m0-cs0 _spi3m0-cs1 _tsadctsadc-shutorg _tsadc-pin _uart0uart0-xfer _(uart1uart1m1-xfer _uart1m1-ctsn _uart1m1-rtsn _uart2uart2m0-xfer _uart3uart3m0-xfer _uart4uart4m0-xfer _uart5uart5m0-xfer _uart6uart6m0-xfer _uart7uart7m0-xfer _uart8uart8m0-xfer _uart9uart9m0-xfer _vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2gpio-keysvol-keys_l _gamepad-keys-l _  gpio-lcdlcd0-rst _ ]lcd1-rst _ ehall-sensorhal-int-l _hp-detecthp-det _joy-muxjoy-mux-en _joy-mux-config _sdio-pwrseqwifi-enable-h _sdmmcsdmmc-pwren-l _touchtouch0-rst _ touch0-irq _touch1-rst _touch1-irq _vcc-lcdvdd-lcd0-h _vccio-lcd0-h _vdd-lcd1-h _vccio-lcd1-h _vcc-wifivcc-wifi-h _wifi-irqwifi-host-wake-irq _Ropp-table-0,operating-points-v2 mopp-408000000 xQ  P P0 @opp-600000000 x#F  P P0 @opp-816000000 x0,  P P0 @ opp-1104000000 xAʹ  0 @opp-1416000000 xTfr 0 @opp-1608000000 x_" 0 @opp-1800000000 xkI 000 @opp-1992000000 xv 000 @opp-table-1,operating-points-v2Gopp-200000000 x   P PB@opp-300000000 x  P PB@opp-400000000 xׄ  P PB@opp-600000000 x#F  B@opp-700000000 x)' ~~B@opp-800000000 x/ B@B@B@sata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci satapmaliverxoob V^ sata-phy Edisabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconqos@fe190080,rockchip,rk3568-qossyscon @qos@fe190100,rockchip,rk3568-qossyscon Aqos@fe190200,rockchip,rk3568-qossyscon Bsyscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconˀphy@fe8c0000,rockchip,rk3568-pcie3-phy  &'wrefclk_mrefclk_npclk [phy  Edisabledpcie@fe270000,rockchip,rk3568-pcie  ( $aclk_mstaclk_slvaclk_dbipclkauxpci<V+syspmcmsglegacyerrc ` $ 2 C R a pn x pcie-phy0@@'Tt @@@dbiapbconfig [pipe Edisabledlegacy-interrupt-controllerNc Vpcie@fe280000,rockchip,rk3568-pcie   /( $aclk_mstaclk_slvaclk_dbipclkauxpci<V+syspmcmsglegacyerrc ` $ 2 C R a p n  x pcie-phy0@(Tt @dbiapbconfig [pipe Edisabledlegacy-interrupt-controllerNc Vethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20a*V+macirqeth_wake_irq@ Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref  [stmmacethl -@S Edisabledmdio,snps,dwmac-mdio stmmac-axi-config\fvrx-queues-configqueue0tx-queues-configqueue0can@fe570000,rockchip,rk3568v2-canfdW V A@ baudpclk UT [coreapbdefault Edisabledcan@fe580000,rockchip,rk3568v2-canfdX V CB baudpclk WV [coreapbdefault Edisabledcan@fe590000,rockchip,rk3568v2-canfdY V ED baudpclk YX [coreapbdefault Edisabledphy@fe820000,rockchip,rk3568-naneng-combphy | refapbpipe0@ [phy    Edisabledchosen serial2:1500000n8adc-keys-home ,adc-keys buttons  w@ <button-home HOME < adc-keys-play ,adc-keys buttons    <button-play PLAY  adc-mux,io-channel-mux left_xright_xleft_yright_y ~  parent 7 Ddadc-joystick ,adc-joystick default < axis@0 S  \  e axis@1 S  \  e axis@2 S  \  e axis@3 S  \  e backlight0,pwm-backlight Q oa\backlight1,pwm-backlight Q oadbattery,simple-battery t=    B`0 8% @6`B`0}-B1Pd@x_?Z?@U>M8P=XK<F<9A;<:7:aP29-9`(9ch#94888x8H7 43@%gpio-keys-control ,gpio-keysdefaultbutton-a  EAST 1button-b  SOUTH 0button-down  DPAD-DOWN !button-l1  TL 6button-l2  TL2 8button-left  DPAD-LEFT "button-menu  HOME fbutton-right  DPAD-RIGHT #button-r1  T2 7button-r2  TR2 9button-select   SELECT :button-start   START ;button-thumbl  THUMBL =button-thumbr  THUMBR >button-up  DPAD-UP  button-x  NORTH 3button-y  WEST 4gpio-keys-hall ,gpio-keysdefaultlid-switch   LID gpio-keys-volume ,gpio-keysdefaultvol-down-key  VOLUMEDOWN rvol-up-key  VOLUMEUP smux-controller ,gpio-muxdefaultpwm-leds ,pwm-ledsled-0on%power. oaled-1 %charging. oaled-2off%status. oasdio-pwrseq,mmc-pwrseq-simple ext_clock default= QLsound,simple-audio-carddefaulti2s TQ+ rk817_extsInternal Speakers\MICLMic JackHeadphonesHPOLHeadphonesHPORInternal SpeakersHPOLInternal SpeakersHPORCMicrophoneMic JackHeadphoneHeadphonesSpeakerInternal Speakerssimple-audio-card,codecLsimple-audio-card,cpuLregulator-vdd-lcd0,regulator-fixed  default vdd_lcd0^regulator-state-memregulator-vccio-lcd0,regulator-fixed  default vccio_lcd0_regulator-state-memregulator-vdd-lcd1,regulator-fixed  default vdd_lcd1fregulator-state-memregulator-vccio-lcd1,regulator-fixed  default vccio_lcd1gregulator-state-memregulator-vcc3v3-sd,regulator-fixed  default0 vcc3v3_sdq2ZY2Zsregulator-vcc-sys,regulator-fixed0q9Y9vcc_sys#pwm-vibrator ,pwm-vibratorenable o#regulator-vcc-wifi,regulator-fixed  default0q2ZY2Z vcc_wifiP interrupt-parent#address-cells#size-cellscompatiblemodelchassis-typegpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellssystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-initial-moderegulator-max-microvoltregulator-min-microvoltregulator-nameregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendmonitored-batteryrockchip,resistor-sense-micro-ohmsrockchip,sleep-enter-current-microamprockchip,sleep-filter-current-microampfcs,suspend-voltage-selectorvin-supplycellwise,battery-profilecellwise,monitor-interval-mspower-suppliesdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencybus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104vmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointbacklightreset-gpiosvdd-supplyvccio-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanescd-gpiosdisable-wpvqmmc-supplyno-sdno-sdiodma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsAVDD28-supplyirq-gpiospaneltouchscreen-size-xtouchscreen-size-ytouchscreen-inverted-xtouchscreen-inverted-yVDDIO-supplyuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiospolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-lowrockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,phy-grfstdout-pathio-channel-namesio-channelskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltmux-controlssettle-time-usabs-flatabs-fuzzabs-rangepwmscharge-full-design-microamp-hourscharge-term-current-microampconstant-charge-current-max-microampconstant-charge-voltage-max-microvoltfactory-internal-resistance-micro-ohmsprecharge-current-microampprecharge-upper-limit-microvoltvoltage-max-design-microvoltvoltage-min-design-microvoltocv-capacity-celsiusocv-capacity-table-0linux,input-typewakeup-event-actionautorepeat#mux-control-cellsmux-gpioscolordefault-statefunctionmax-brightnesspost-power-on-delay-mssimple-audio-card,hp-det-gpiossimple-audio-card,pin-switchessimple-audio-card,routingsimple-audio-card,widgetsenable-active-highgpiopwm-namesvcc-supply