\8( h)rockchip,rk3588-evb2-v10rockchip,rk3588 +7Rockchip RK3588 EVB2 V10 Boardaliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/mmc@fe2e0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0cpuarm,cortex-a55 psci+ 2 BO@an{@  cpu@100cpuarm,cortex-a55 psci+ 2 BO@an{@ cpu@200cpuarm,cortex-a55 psci+ 2 BO@an{@ cpu@300cpuarm,cortex-a55 psci+ 2 BO@an{@ cpu@400cpuarm,cortex-a76 psci+ 2 BO@an{@cpu@500cpuarm,cortex-a76 psci+ 2 BO@an{@cpu@600cpuarm,cortex-a76 psci+ 2 BO@an{@cpu@700cpuarm,cortex-a76 psci+ 2 BO@an{@ idle-statespscicpu-sleeparm,idle-state%d6xF l2-cache-l0cacheDQ@cWc l2-cache-l1cacheDQ@cWcl2-cache-l2cacheDQ@cWcl2-cache-l3cacheDQ@cWcl2-cache-b0cacheDQ@cWcl2-cache-b1cacheDQ@cWcl2-cache-b2cacheDQ@cWcl2-cache-b3cacheDQ@cWcl3-cachecacheD0Q@cWcdisplay-subsystemrockchip,display-subsystemqfirmwarescmi arm,scmi-smcw+protocol@14 protocol@16hdmi0-soundsimple-audio-cardi2shdmi0 disabledsimple-audio-card,codecsimple-audio-card,cpupmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫splltimerarm,armv8-timerP    %+sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32kreserved-memory+;shmem@10f000arm,scmi-shmemBhdmi-receiver-cmashared-dma-poolIJ VB disabledgpu@fb000000*rockchip,rk3588-maliarm,mali-valhall-csf ` p +corecoregroupstacks 0\]^ +jobmmugpu okay !"usb@fc000000rockchip,rk3588-dwc3snps,dwc3@+ref_clksuspend_clkbus_clkotg #$usb2-phyusb3-phy utmi_wideR&Gh disabledusb@fc800000"rockchip,rk3588-ehcigeneric-ehci+%&usbokayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci+%&usbokayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci+'(usbokayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci+'(usbokayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(+jihkr&ref_clksuspend_clkbus_clkutmipipehost) usb3-phy utmi_wide4&Gh disablediommu@fc900000 arm,smmu-v3 @qsvo+eventqgerrorpriqcmdq-synciommu@fcb00000 arm,smmu-v3 @}{+eventqgerrorpriqcmdq-sync disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdXsyscon@fd58c000rockchip,rk3588-sys-grfsysconXqsyscon@fd5e8000!rockchip,rk3588-dcphy-grfsyscon^@syscon@fd5ec000!rockchip,rk3588-dcphy-grfsyscon^@syscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ rsyscon@fd5a6000rockchip,rk3588-vo0-grfsysconZ` +syscon@fd5a8000rockchip,rk3588-vo1-grfsysconZ@+ssyscon@fd5ac000rockchip,rk3588-usb-grfsysconZ@syscon@fd5b0000rockchip,rk3588-php-grfsyscon[+syscon@fd5b4000#rockchip,rk3588-csidphy-grfsyscon[@syscon@fd5b5000#rockchip,rk3588-csidphy-grfsyscon[Psyscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon[ syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@ syscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsyscon\@syscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@0rockchip,rk3588-usb2phy+phyclk usb480m_phy0mphyapbokayotg-portokay*#syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@8000rockchip,rk3588-usb2phy+phyclk usb480m_phy2ophyapbokay%host-portokay*&syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@c000rockchip,rk3588-usb2phy+phyclk usb480m_phy3p phyapbokay'host-portokay*(syscon@fd5e0000$rockchip,rk3588-hdptxphy-grfsyscon^syscon@fd5f0000rockchip,rk3588-iocsyscon_ sram@fd600000 mmio-sram`;`+clock-controller@fd7c0000rockchip,rk3588-cru|`]q@pA.2Fq)׫ׄe/ׄ eZ р +i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=+ts i2cpclk,default+ disabledserial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK+baudclkapb_pclk--txrx.default disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+ pwmpclk/default disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+ pwmpclk0default disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm + pwmpclk1default disabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+ pwmpclk2default disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfdtpower-controller!rockchip,rk3588-power-controller)+okaypower-domain@8)+power-domain@9  +!#" =345)+power-domain@10 +!#"=6)power-domain@11 +!#"=7)power-domain@12 +=89:;)D!power-domain@13 +)power-domain@14(+=<)power-domain@15 +==)power-domain@16+ =>?@+)power-domain@17 + =ABC)power-domain@21+ =DEFGHIJK+)power-domain@23+CA=L)power-domain@14 +=<)power-domain@15+==)power-domain@22+=M)power-domain@24+[Z]=NO+)power-domain@258+Z=P)power-domain@268+Q=QR)power-domain@270+=STUV+)power-domain@28 +=WX)power-domain@29(+=YZ)power-domain@30+z{=[)power-domain@31@+W=\]^_)power-domain@33!+WZ[)power-domain@34"+WZ[)power-domain@37%+2=`)power-domain@38&+45)power-domain@40(=a)npu@fdab0000rockchip,rk3588-rknn-core00 Rpccnacoren + #aclkhclknpupclk` p srst_asrst_h \b disablediommu@fdab9000,rockchip,rk3588-iommurockchip,rk3568-iommu n+  aclkiface  disabledbnpu@fdac0000rockchip,rk3588-rknn-core00 Rpccnacoreo + #aclkhclknpupclk` p srst_asrst_h \c disablediommu@fdaca000,rockchip,rk3588-iommurockchip,rk3568-iommuo+ aclkiface  disabledcnpu@fdad0000rockchip,rk3588-rknn-core00 Rpccnacorep + #aclkhclknpupclk` p srst_asrst_h \d disablediommu@fdada000,rockchip,rk3588-iommurockchip,rk3568-iommup+ aclkiface  disableddvideo-codec@fdb50000+rockchip,rk3588-vpu121rockchip,rk3568-vpuw+vdpu+ aclkhclk\eiommu@fdb50800,rockchip,rk3588-iommurockchip,rk3568-iommu@v aclkiface+erga@fdb80000(rockchip,rk3588-rgarockchip,rk3288-rgat+aclkhclksclkrqp coreaxiahbvideo-codec@fdba0000rockchip,rk3588-vepu121z+ aclkhclk\fiommu@fdba0800,rockchip,rk3588-iommurockchip,rk3568-iommu@y+ aclkifacefvideo-codec@fdba4000rockchip,rk3588-vepu121@|+ aclkhclk\giommu@fdba4800,rockchip,rk3588-iommurockchip,rk3568-iommuH@{+ aclkifacegvideo-codec@fdba8000rockchip,rk3588-vepu121~+ aclkhclk\hiommu@fdba8800,rockchip,rk3588-iommurockchip,rk3568-iommu@}+ aclkifacehvideo-codec@fdbac000rockchip,rk3588-vepu121+ aclkhclk\iiommu@fdbac800,rockchip,rk3588-iommurockchip,rk3568-iommu@+ aclkifaceivideo-codec@fdc38000rockchip,rk3588-vdec0ÁÀÆRfunctionlinkcache_(+axiahbcabaccorehevc_cabac `p/#F#F;\j(CBFHGaxiahbcabaccorehevc_cabacckiommu@fdc38700,rockchip,rk3588-iommurockchip,rk3568-iommu Ç@Ç@@`+ aclkifacejvideo-codec@fdc40000rockchip,rk3588-vdec0Rfunctionlinkcachea(+axiahbcabaccorehevc_cabac `p/#F#F;\l(JIMONaxiahbcabaccorehevc_cabaccmiommu@fdc40700,rockchip,rk3588-iommurockchip,rk3568-iommu @@@b+ aclkifacelvideo-codec@fdc70000rockchip,rk3588-av1-vpul+vdpu`ACpׄׄ+AC aclkhclk vop@fdd90000rockchip,rk3588-vop BPRvopgamma-lut@+]\abcd[noQaclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_voppll_hdmiphy0pll_hdmiphy1\pqhrystokay``ports+port@0+endpoint@2uport@1+port@2+endpoint@a v|port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~+]\ aclkifaceokaypspdif-tx@fddb0000,rockchip,rk3588-spdifrockchip,rk3568-spdif` mclkhclk+txw disabledi2s@fddc0000rockchip,rk3588-i2s-tdm+mclk_txmclk_rxhclk`xtxtx-m disabledspdif-tx@fdde0000,rockchip,rk3588-spdifrockchip,rk3568-spdif`A mclkhclk+D@txw disabledi2s@fddf0000rockchip,rk3588-i2s-tdm+445mclk_txmclk_rxhclk`1xtxtx-m disabledi2s@fddfc000rockchip,rk3588-i2s-tdm+00,mclk_txmclk_rxhclk`-xrxrx-m disableddsi@fde20000rockchip,rk3588-mipi-dsi2+eg pclksysapby dcphyr disabledports+port@0port@1dsi@fde30000rockchip,rk3588-mipi-dsi2+fh pclksysapbz dcphyr disabledports+port@0port@1dp@fde50000rockchip,rk3588-dp@`p$(+apbauxhdcpi2sspdif$okay{defaultports+port@0endpoint|vport@1endpoint}/hdmi@fde80000rockchip,rk3588-dw-hdmi-qp0+4Rpclkearcrefaudhdphclk_vo1Ph+avpcecearcmainhpdndefault~0refhdpqsokayports+port@0endpointuport@1endpoint0edp@fdec0000rockchip,rk3588-edp+dppclkndpdpapbs disabledports+port@0port@1qos@fdf35000rockchip,rk3588-qossysconP 8qos@fdf35200rockchip,rk3588-qossysconR 9qos@fdf35400rockchip,rk3588-qossysconT :qos@fdf35600rockchip,rk3588-qossysconV ;qos@fdf36000rockchip,rk3588-qossyscon` [qos@fdf39000rockchip,rk3588-qossyscon `qos@fdf3d800rockchip,rk3588-qossyscon aqos@fdf3e000rockchip,rk3588-qossyscon ]qos@fdf3e200rockchip,rk3588-qossyscon \qos@fdf3e400rockchip,rk3588-qossyscon ^qos@fdf3e600rockchip,rk3588-qossyscon _qos@fdf40000rockchip,rk3588-qossyscon Yqos@fdf40200rockchip,rk3588-qossyscon Zqos@fdf40400rockchip,rk3588-qossyscon Sqos@fdf40500rockchip,rk3588-qossyscon Tqos@fdf40600rockchip,rk3588-qossyscon Uqos@fdf40800rockchip,rk3588-qossyscon Vqos@fdf41000rockchip,rk3588-qossyscon Wqos@fdf41100rockchip,rk3588-qossyscon Xqos@fdf60000rockchip,rk3588-qossyscon >qos@fdf60200rockchip,rk3588-qossyscon ?qos@fdf60400rockchip,rk3588-qossyscon @qos@fdf61000rockchip,rk3588-qossyscon Aqos@fdf61200rockchip,rk3588-qossyscon Bqos@fdf61400rockchip,rk3588-qossyscon Cqos@fdf62000rockchip,rk3588-qossyscon <qos@fdf63000rockchip,rk3588-qossyscon0 =qos@fdf64000rockchip,rk3588-qossyscon@ Lqos@fdf66000rockchip,rk3588-qossyscon` Dqos@fdf66200rockchip,rk3588-qossysconb Eqos@fdf66400rockchip,rk3588-qossyscond Fqos@fdf66600rockchip,rk3588-qossysconf Gqos@fdf66800rockchip,rk3588-qossysconh Hqos@fdf66a00rockchip,rk3588-qossysconj Iqos@fdf66c00rockchip,rk3588-qossysconl Jqos@fdf66e00rockchip,rk3588-qossysconn Kqos@fdf67000rockchip,rk3588-qossysconp Mqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon 6qos@fdf71000rockchip,rk3588-qossyscon 7qos@fdf72000rockchip,rk3588-qossyscon 3qos@fdf72200rockchip,rk3588-qossyscon" 4qos@fdf72400rockchip,rk3588-qossyscon$ 5qos@fdf80000rockchip,rk3588-qossyscon Pqos@fdf81000rockchip,rk3588-qossyscon Qqos@fdf81200rockchip,rk3588-qossyscon Rqos@fdf82000rockchip,rk3588-qossyscon Nqos@fdf82200rockchip,rk3588-qossyscon" Odfi@fe060000rockchip,rk3588-dfi@&0:pcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0+CH>MR)aclk_mstaclk_slvaclk_dbipclkauxpipepciP+syspmcmsglegacyerr` ,;00C00M) pcie-phy"T;  @0 @@Rdbiapbconfig). pwrpipe+ disabledlegacy-interrupt-controllerW pcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O0+DI?NSs)aclk_mstaclk_slvaclk_dbipclkauxpipepciP+syspmcmsglegacyerr` ,;@@C@@M pcie-phy"T;  @0 A@Rdbiapbconfig*/ pwrpipe+ disabledlegacy-interrupt-controllerW ethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a +macirqeth_wake_irq(+67Y^50stmmacethclk_mac_refpclk_macaclk_macptp_ref!$ stmmacethql+} disabledmdiosnps,dwmac-mdio+stmmac-axi-configrx-queues-configqueue0queue1tx-queues-config queue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci!(+b_eTosatapmaliverxoobrefasic#+ disabledsata-port@05@ sata-phyB Q sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(+dagVqsatapmaliverxoobrefasic#+ disabledsata-port@05@) sata-phyB Q spi@fe2b0000 rockchip,sfc+@+/0clk_sfchclk_sfc+ disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ +  biuciuciu-driveciu-sample`k default( disabledmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ +biuciuciu-driveciu-sample`kрdefault%okay+ywifi@1brcm,bcm4329-fmac   +host-wakedefaultmmc@fe2e0000rockchip,rk3588-dwcmshc.`-., p n6 (+,*+-.corebusaxiblocktimerk default(corebusaxiblocktimerokayy,rng@fe378000rockchip,rk3588-rng7+ 0i2s@fe470000rockchip,rk3588-i2s-tdmG++/(mclk_txmclk_rxhclk`)---txrx&*+ tx-mrx-m4default( disabledi2s@fe480000rockchip,rk3588-i2s-tdmH+y}umclk_txmclk_rxhclk--txrx^_ tx-mrx-m4default( disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI+i2s_clki2s_hclk`wwtxrx&default disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ+%i2s_clki2s_hclk`"wwtxrx&default disabledspdif-tx@fe4e0000,rockchip,rk3588-spdifrockchip,rk3568-spdifN`7 mclkhclk+96tx-default& disabledspdif-tx@fe4f0000,rockchip,rk3588-spdifrockchip,rk3568-spdifO`= mclkhclk+?<txwdefault& disabledinterrupt-controller@fe600000 arm,gic-v3 `h WO_ai8t;+msi-controller@fe640000arm,gic-v3-itsdOtmsi-controller@fe660000arm,gic-v3-itsfOt!ppi-partitionsinterrupt-partition-0interrupt-partition-1 dma-controller@fea10000arm,pl330arm,primecell@ VW+n apb_pclk-dma-controller@fea30000arm,pl330arm,primecell@ XY+o apb_pclkwi2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c+{ i2cpclk>default+ disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c+| i2cpclk?default+okayrtc@51haoyu,hym8563Qhym8563 default1i2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c+} i2cpclk@default+ disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c+~ i2cpclkAdefault+ disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkBdefault+ disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !+TW pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt+dc tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF+spiclkapb_pclk--txrx default+ disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG+spiclkapb_pclk--txrx default+ disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH+spiclkapb_pclkwwtxrx default+okay`p pmic@0rockchip,rk806 defaultB@   , 8 D P \ h t      dvs1-null-pins gpio_pwrctrl1 pin_fun0dvs2-null-pins gpio_pwrctrl2 pin_fun0dvs3-null-pins gpio_pwrctrl3 pin_fun0regulatorsdcdc-reg1   dp ~ 10 Fvdd_gpu_s0 U q" '!regulator-state-mem dcdc-reg2   dp ~ 10 Fvdd_npu_s0regulator-state-mem dcdc-reg3    L  q 10 Fvdd_log_s0regulator-state-mem  qdcdc-reg4   dp ~ 10 Fvdd_vdenc_s0regulator-state-mem dcdc-reg5    L ~ 10 U Fvdd_gpu_mem_s0 q! '"regulator-state-mem dcdc-reg6    L ~ 10 Fvdd_npu_mem_s0regulator-state-mem dcdc-reg7     10 Fvdd_2v0_pldo_s3regulator-state-mem  dcdc-reg8    L ~ 10 Fvdd_vdenc_mem_s0regulator-state-mem dcdc-reg9   Fvdd2_ddr_s3regulator-state-mem dcdc-reg10     10 Fvcc_1v1_nldo_s3regulator-state-mem  pldo-reg1   w@ w@ 10 Favcc_1v8_s0regulator-state-mem pldo-reg2   w@ w@ 10 Fvdd1_1v8_ddr_s3regulator-state-mem  w@pldo-reg3   w@ w@ 10 Favcc_1v8_codec_s0regulator-state-mem pldo-reg4   2Z 2Z 10 Fvcc_3v3_s3regulator-state-mem  2Zpldo-reg5   w@ 2Z 10 Fvccio_sd_s0regulator-state-mem pldo-reg6   w@ w@ 10 Fvccio_1v8_s3regulator-state-mem  w@nldo-reg1    q  q 10 Fvdd_0v75_s3regulator-state-mem  qnldo-reg2       Fvdd2l_0v9_ddr_s3regulator-state-mem  nldo-reg3    q  q Fvdd_0v75_hdmi_edp_s0regulator-state-mem nldo-reg4    q  q Favdd_0v75_s0regulator-state-mem nldo-reg5    P  P Fvdd_0v85_s0regulator-state-mem pmic@1rockchip,rk806  defaultB@   , 8 D P \ h t      dvs1-null-pins gpio_pwrctrl1 pin_fun0dvs2-null-pins gpio_pwrctrl2 pin_fun0dvs3-null-pins gpio_pwrctrl3 pin_fun0regulatorsdcdc-reg1   q ' dp  10 Fvdd_cpu_big1_s0regulator-state-mem dcdc-reg2   q ' dp  10 Fvdd_cpu_big0_s0regulator-state-mem dcdc-reg3   q ' dp ~ 10 Fvdd_cpu_lit_s0regulator-state-mem dcdc-reg4   2Z 2Z 10 Fvcc_3v3_s0regulator-state-mem dcdc-reg5   q '  L  10 Fvdd_cpu_big1_mem_s0regulator-state-mem dcdc-reg6   q '  L  10 Fvdd_cpu_big0_mem_s0regulator-state-mem dcdc-reg7   w@ w@ 10 Fvcc_1v8_s0regulator-state-mem dcdc-reg8   q '  L ~ 10 Fvdd_cpu_lit_mem_s0regulator-state-mem dcdc-reg9   Fvddq_ddr_s0regulator-state-mem dcdc-reg10    L   10 Fvdd_ddr_s0regulator-state-mem pldo-reg1   w@ w@ 10 Fvcc_1v8_cam_s0regulator-state-mem pldo-reg2   w@ w@ 10 Favdd1v8_ddr_pll_s0regulator-state-mem pldo-reg3   w@ w@ 10 Fvdd_1v8_pll_s0regulator-state-mem pldo-reg4   2Z 2Z 10 Fvcc_3v3_sd_s0regulator-state-mem pldo-reg5   * * 10 Fvcc_2v8_cam_s0regulator-state-mem pldo-reg6   w@ w@ Fpldo6_s3regulator-state-mem  w@nldo-reg1    q  q 10 Fvdd_0v75_pll_s0regulator-state-mem nldo-reg2    P  P Fvdd_ddr_pll_s0regulator-state-mem nldo-reg3    P  P 10 Favdd_0v85_s0regulator-state-mem nldo-reg4   O O 10 Favdd_1v2_cam_s0regulator-state-mem nldo-reg5   O O 10 Favdd_1v2_s0regulator-state-mem spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI+spiclkapb_pclkwwtxrx default+ disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL+baudclkapb_pclk-- txrxdefault disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM+baudclkapb_pclk- - txrxdefaultokayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN+baudclkapb_pclk- - txrxdefault disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO+baudclkapb_pclkw w txrxdefault disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP+baudclkapb_pclkw w txrxdefault disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ+baudclkapb_pclkw wtxrxdefault disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR+baudclkapb_pclkxxtxrxdefault disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS+baudclkapb_pclkx x txrxdefault disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT+baudclkapb_pclkx x txrxdefault disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+LK pwmpclkdefault disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+LK pwmpclkdefault disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +LK pwmpclkdefault disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+LK pwmpclkdefault disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+ON pwmpclkdefault disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+ON pwmpclkdefault disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +ON pwmpclkdefault disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+ON pwmpclkdefault disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+RQ pwmpclkdefault disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+RQ pwmpclkdefault disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +RQ pwmpclkdefault disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+RQ pwmpclkdefault disabledthermal-zonespackage-thermal   tripspackage-crit &8 2 criticalbigcore0-thermal d  tripsbigcore0-alert &L 2passivebigcore0-crit &8 2 criticalcooling-mapsmap0 = Bbigcore2-thermal d  tripsbigcore2-alert &L 2passivebigcore2-crit &8 2 criticalcooling-mapsmap0 = B littlecore-thermal d  tripslittlecore-alert &L 2passivelittlecore-crit &8 2 criticalcooling-mapsmap0 =0 Bcenter-thermal   tripscenter-crit &8 2 criticalgpu-thermal d  tripsgpu-alert &L 2passivegpu-crit &8 2 criticalcooling-mapsmap0 = Bnpu-thermal   tripsnpu-crit &8 2 criticaltsadc@fec00000rockchip,rk3588-tsadc+tsadcapb_pclk`pVWtsadc-apbtsadc Q h  defaultsleep  disabledadc@fec10000rockchip,rk3588-saradc +saradcapb_pclkU saradc-apb disabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkCdefault+ disabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkDdefault+ disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkEdefault+ disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ+spiclkapb_pclkx xtxrx default+ disabledefuse@fecc0000rockchip,rk3588-otp +otpapb_pclkphyarb otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[+p apb_pclkxphy@fed60000rockchip,rk3588-hdptx-phy +Trefapb8#cde!""phyapbinitcmnlaneroplllcpllokaynphy@fed80000rockchip,rk3588-usbdp-phy+lVrefclkimmortalpclkutmi(   initcmnlanepcs_apbpma_apb   okay $phy@feda0000rockchip,rk3588-mipi-dcphy+ pclkref ijm_phyapbgrfs_phy disabledyphy@fedb0000rockchip,rk3588-mipi-dcphy+ pclkref klm_phyapbgrfs_phy disabledzphy@fedc0000rockchip,rk3588-csi-dphy+pclkapbphy disabledphy@fedc8000rockchip,rk3588-csi-dphy܀+pclkapbphy disabledphy@fee00000rockchip,rk3588-naneng-combphy+vW refapbpipe`p<Cphyapb + 2  disabledphy@fee20000rockchip,rk3588-naneng-combphy+xW refapbpipe`p>Ephyapb + 2  disabled)sram@ff001000 mmio-sram;+codec-sram@0 Hkcodec-sram@78000p Hmpinctrlrockchip,rk3588-pinctrl; + gpio@fd8a0000rockchip,gpio-bank+qr M Wgpio@fec20000rockchip,gpio-bank+st M Wgpio@fec30000rockchip,gpio-bank+uv M @ Wgpio@fec40000rockchip,gpio-bank+wx M ` Wgpio@fec50000rockchip,gpio-bank+yz M W3pcfg-pull-up Ypcfg-pull-down fpcfg-pull-none u pcfg-pull-none-drv-level-2 u pcfg-pull-up-drv-level-1 Y pcfg-pull-up-drv-level-2 Y pcfg-pull-none-smt u pcfg-pull-none-drv-level-1-smt u  pcfg-pull-none-drv-level-3-smt u  pcfg-pull-none-drv-level-5-smt u  auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp0m0-pins   {dp1emmcemmc-rstnout  emmc-bus8 emmc-clk emmc-cmd emmc-data-strobe eth1fspigmac1gpuhdmihdmim0-tx0-cec  ~hdmim0-tx0-hpd  hdmim0-tx0-scl hdmim0-tx0-sda hdmim0-tx1-hpd  hdmim1-tx1-scl hdmim1-tx1-sda hdmim2-tx1-cec  i2c0i2c0m0-xfer ,i2c1i2c1m0-xfer  i2c2i2c2m0-xfer   i2c3i2c3m0-xfer   i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2c6i2c6m0-xfer   i2c7i2c7m0-xfer   i2c8i2c8m0-xfer   i2s0i2s0-lrck  i2s0-sclk  i2s0-sdi0  i2s0-sdi1  i2s0-sdi2  i2s0-sdi3  i2s0-sdo0  i2s0-sdo1  i2s0-sdo2  i2s0-sdo3  i2s1i2s1m0-lrck  i2s1m0-sclk  i2s1m0-sdi0  i2s1m0-sdi1  i2s1m0-sdi2  i2s1m0-sdi3  i2s1m0-sdo0   i2s1m0-sdo1   i2s1m0-sdo2   i2s1m0-sdo3   i2s2i2s2m1-lrck  i2s2m1-sclk   i2s2m1-sdi   i2s2m1-sdo   i2s3i2s3-lrck  i2s3-sclk  i2s3-sdi  i2s3-sdo  jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp       pmupwm0pwm0m0-pins  /pwm1pwm1m0-pins  0pwm2pwm2m0-pins  1pwm3pwm3m0-pins  2pwm4pwm4m0-pins   pwm5pwm5m0-pins  pwm6pwm6m0-pins   pwm7pwm7m0-pins   pwm8pwm8m0-pins   pwm9pwm9m0-pins   pwm10pwm10m0-pins   pwm11pwm11m0-pins   pwm12pwm12m0-pins   pwm13pwm13m0-pins   pwm14pwm14m0-pins   pwm15pwm15m0-pins   refclksatasata0sata1sata2sdiosdiom0-pins`          sdmmcsdmmc-bus4@ sdmmc-clk sdmmc-cmd sdmmc-det spdif0spdif0m0-tx  spdif1spdif1m0-tx  spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m1-pins0 spi1m1-cs0 spi1m1-cs1 spi2spi2m2-pins0  spi2m2-cs0 spi2m2-cs1 spi3spi3m1-pins0  spi3m1-cs0 spi3m1-cs1 spi4spi4m0-pins0 spi4m0-cs0 spi4m0-cs1 tsadctsadc-shut-org  uart0uart0m1-xfer  .uart1uart1m1-xfer   uart2uart2m0-xfer   uart3uart3m1-xfer   uart4uart4m1-xfer   uart5uart5m1-xfer   uart6uart6m1-xfer   uart7uart7m1-xfer   uart8uart8m1-xfer   uart9uart9m1-xfer   vopbt656gpio-functsadc-gpio-func  eth0gmac0hym8563hym8563-int usbvcc5v0-host-en  5wifiwifi-enable-h 2wifi-host-wake-irq  hdmi1-soundsimple-audio-cardi2shdmi1 disabledsimple-audio-card,codecsimple-audio-card,cpuusb@fc400000rockchip,rk3588-dwc3snps,dwc3@@+ref_clksuspend_clkbus_clkhost usb2-phyusb3-phy utmi_wideS&Ghokaysyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon[.syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon\-syscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon\@,syscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@@++usb2phy@4000rockchip,rk3588-usb2phy@+phyclk usb480m_phy1nphyapbokay*otg-portokay*syscon@fd5e4000$rockchip,rk3588-hdptxphy-grfsyscon^@)spdif-tx@fddb8000,rockchip,rk3588-spdifrockchip,rk3568-spdifۀ` mclkhclk+txw disabledi2s@fddc8000rockchip,rk3588-i2s-tdm܀+mclk_txmclk_rxhclk`xtxtx-m disabledspdif-tx@fdde8000,rockchip,rk3588-spdifrockchip,rk3568-spdifހ`F mclkhclk+IEtxw disabledi2s@fddf4000rockchip,rk3588-i2s-tdm@+99?mclk_txmclk_rxhclk`6xtxtx-m disabledi2s@fddf8000rockchip,rk3588-i2s-tdm߀+++'mclk_txmclk_rxhclk`(xrxrx-m disabledi2s@fde00000rockchip,rk3588-i2s-tdm+&&"mclk_txmclk_rxhclk`#xrxrx-m disableddp@fde60000rockchip,rk3588-dp@`p$(+apbauxhdcpi2sspdif disabledports+port@0port@1hdmi@fdea0000rockchip,rk3588-dw-hdmi-qp0+9Spclkearcrefaudhdphclk_vo1Pi+avpcecearcmainhpdodefault1refhdpqs disabledports+port@0port@1edp@fded0000rockchip,rk3588-edp+dppclkodpdpapbs disabledports+port@0port@1hdmi_receiver@fdee0000.rockchip,rk3588-hdmirx-ctrlersnps,dw-hdmi-rx`0 +cechdmidma8+   !3aclkaudiocr_parapclkrefhclk_s_hdmirxhclk_vo1  axiapbrefbiuqys disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipepciP+syspmcmsglegacyerr`     ,;!CM" pcie-phy"T;  @0 @@Rdbiapbconfig&+ pwrpipe disabledlegacy-interrupt-controllerW  pcie-ep@fe150000rockchip,rk3588-pcie-epP @ @ @ @0Rdbidbi2apbaddr_spaceatu0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipe ++syspmcmsglegacyerrdma0dma1dma2dma3,M" pcie-phy"&+ pwrpipe disabledpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+0+AF<KPu)aclk_mstaclk_slvaclk_dbipclkauxpipepciP+syspmcmsglegacyerr` ####,;!CM" pcie-phy"T;  @ @@0 @@@Rdbiapbconfig', pwrpipe disabledlegacy-interrupt-controllerW #pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /0+BG=LQ)aclk_mstaclk_slvaclk_dbipclkauxpipepciP+syspmcmsglegacyerr` $$$$,; C M% pcie-phy"T;  @0 @@Rdbiapbconfig(- pwrpipe+ disabledlegacy-interrupt-controllerW $ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a +macirqeth_wake_irq(+67X]40stmmacethclk_mac_refpclk_macaclk_macptp_ref!# stmmacethql+}&'( disabledmdiosnps,dwmac-mdio+stmmac-axi-config&rx-queues-config'queue0queue1tx-queues-config (queue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci"(+c`fUpsatapmaliverxoobrefasic#+ disabledsata-port@05@% sata-phyB Q phy@fed70000rockchip,rk3588-hdptx-phy +Urefapb8&fgh$%"phyapbinitcmnlaneroplllcpll) disabledophy@fed90000rockchip,rk3588-usbdp-phy+mW*refclkimmortalpclkutmi(initcmnlanepcs_apbpma_apb +  ,okay phy@fee10000rockchip,rk3588-naneng-combphy+wW refapbpipe`p=Dphyapb + 2- disabled%phy@fee80000rockchip,rk3588-pcie3-phy+ypclkHphy + . disabled"opp-table-cluster0operating-points-v2  opp-1008000000 < L L~ @opp-1200000000 G 4 4~ @opp-1416000000 Tfr ~ @ opp-1608000000 _" P P~ @opp-1800000000 kI ~~~ @opp-table-cluster1operating-points-v2 opp-1200000000 G L LB@ @opp-1416000000 Tfr  B@ @opp-1608000000 _" B@ @opp-1800000000 kI P PB@ @opp-2016000000 x) HHB@ @opp-2208000000 h llB@ @opp-2400000000  B@B@B@ @opp-table-cluster2operating-points-v2 opp-1200000000 G L LB@ @opp-1416000000 Tfr  B@ @opp-1608000000 _" B@ @opp-1800000000 kI P PB@ @opp-2016000000 x) HHB@ @opp-2208000000 h llB@ @opp-2400000000  B@B@B@ @opp-table-gpuoperating-points-v2 opp-300000000  L L Popp-400000000 ׄ L L Popp-500000000 e L L Popp-600000000 #F L L Popp-700000000 )' ` ` Popp-800000000 / q q Popp-900000000 5 5 5 Popp-1000000000 ; P P Pchosen serial2:1500000n8dp-con dp-connector DP OUT full-sizeportendpoint/}hdmi-conhdmi-connectoraportendpoint0sdio-pwrseqmmc-pwrseq-simple+1 ext_clockdefault2 " 9vcc12v-dcin-regulatorregulator-fixed Fvcc12v_dcin    7vcc5v0-hostregulator-fixed Fvcc5v0_host   LK@ LK@ E X3 ]4default5*regulator-vcc5v0-usbregulator-fixed Fvcc5v0_usb   LK@ LK@ ]64vcc5v0-sys-regulatorregulator-fixed Fvcc5v0_sys   LK@ LK@ ]7regulator-vcc5v0-usbdcinregulator-fixed Fvcc5v0_usbdcin   LK@ LK@ ]76 compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclockscpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2phandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellssimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesno-mapalloc-rangesalignmentassigned-clocksassigned-clock-ratesclock-namespower-domainsmali-supplysram-supplydr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosdomain-supplyreg-namesiommussramrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parentsremote-endpoint#sound-dai-cellsrockchip,vo-grfbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapiommu-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-sd-highspeedcap-sdio-irqdisable-wpkeep-power-in-suspendmmc-pwrseqno-mmcnon-removableno-sdsd-uhs-sdr104supports-cqemmc-hs400-1_8vmmc-hs400-enhanced-strobeno-sdiorockchip,trcm-sync-tx-onlydma-noncoherentmbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellswakeup-sourcenum-cs#gpio-cellsgpio-controllerspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplypinsfunctionregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-nameregulator-enable-ramp-delayregulator-coupled-withregulator-coupled-max-spreadregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsbitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,dp-lane-muxrockchip,pipe-grfrockchip,pipe-phy-grfpoolgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsmemory-regionrockchip,phy-grfopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathlabelpost-power-on-delay-msreset-gpiosenable-active-highgpiovin-supply