F88(7@beagle,am5729-beagleboneaiti,am5728ti,dra742ti,dra74ti,dra7&7BeagleBoard.org BeagleBone AIchosenB=/ocp/interconnect@48000000/segment@0/target-module@6a000/serial@0aliases?I/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0?N/ocp/interconnect@48000000/segment@0/target-module@72000/i2c@0?S/ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0?X/ocp/interconnect@48000000/segment@0/target-module@7a000/i2c@0?]/ocp/interconnect@48000000/segment@0/target-module@7c000/i2c@0Bb/ocp/interconnect@48000000/segment@0/target-module@6a000/serial@0Bj/ocp/interconnect@48000000/segment@0/target-module@6c000/serial@0Br/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0Bz/ocp/interconnect@48000000/segment@0/target-module@6e000/serial@0B/ocp/interconnect@48000000/segment@0/target-module@66000/serial@0B/ocp/interconnect@48000000/segment@0/target-module@68000/serial@0B/ocp/interconnect@48400000/segment@0/target-module@20000/serial@0B/ocp/interconnect@48400000/segment@0/target-module@22000/serial@0B/ocp/interconnect@48400000/segment@0/target-module@24000/serial@0E/ocp/interconnect@4ae00000/segment@20000/target-module@b000/serial@0X/ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/ethernet-ports/port@1X/ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/ethernet-ports/port@2B/ocp/interconnect@4ae00000/segment@30000/target-module@c000/can@0?/ocp/interconnect@48400000/segment@0/target-module@80000/can@0"/ocp/target-module@4b300000/spi@0/ocp/ipu@58820000/ocp/ipu@55020000/ocp/dsp@40800000/ocp/dsp@41000000Z/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0/tps659038@58/tps659038_rtc?/ocp/interconnect@48800000/segment@0/target-module@38000/rtc@0 /connector@0timerarm,armv7-timer disabled0   &interrupt-controller@48211000arm,cortex-a15-gic/@@H!H! H!@ H!`   &Dinterrupt-controller@48281000&ti,omap5-wugen-mputi,omap4-wugen-mpu/@H(&D cpuscpu@0Lcpuarm,cortex-a15@XlscpuDcpu@1Lcpuarm,cortex-a15@Xlscpuopp-tableoperating-points-v2-ti-cpuDopp-1000000000;, P0, P0opp-1176000000FV@ @@ @opp-1500000000Yh/v~v~ocpsimple-pm-busl l3-noc@44000000ti,dra7-l3-noc@DE ( interconnect@4a000000ti,dra7-l4-cfgsimple-pm-bus  l sfck@JJJ clock-dpll-gmac-h12x2-8@2c4ti,divider-clockdpll_gmac_h12x2_ckl=t?@clock-dpll-gmac-h13x2-8@2c8ti,divider-clockdpll_gmac_h13x2_ckl=t?@clock-dpll-gmac-m3x2-8@2bcti,divider-clockdpll_gmac_m3x2_ckl=t@clock-gmii-m-clk-divfixed-factor-clockgmii_m_clk_divl>_jclock-hdmi-clk2-divfixed-factor-clockhdmi_clk2_divl5_jclock-hdmi-divfixed-factor-clock hdmi_div_clkl5_jclock@100 ti,clksel@clock@4@ti,divider-clock l3_iclk_divtl Dclock-l4-root-clk-divfixed-factor-clockl4_root_clk_divl_jDclock-video1-clk2-divfixed-factor-clockvideo1_clk2_divl?_jclock-video1-divfixed-factor-clockvideo1_div_clkl?_jclock-video2-clk2-divfixed-factor-clockvideo2_clk2_divl@_jclock-video2-divfixed-factor-clockvideo2_div_clkl@_jclock-dummy fixed-clock dummy_ckOclockdomainsclock@300 ti,omap4-cmmpu_cm@ clock@20 ti,clkctrl mpu_clkctrl@ Dclock@400 ti,omap4-cmdsp1_cm@ clock@20 ti,clkctrl dsp1_clkctrl@ Dclock@500 ti,omap4-cmipu_cm@ clock@20 ti,clkctrl ipu1_clkctrl@  ABDAclock@50 ti,clkctrl ipu_clkctrl@P4Dclock@600 ti,omap4-cmdsp2_cm@ clock@20 ti,clkctrl dsp2_clkctrl@ Dclock@700 ti,omap4-cmrtc_cm@` `clock@20 ti,clkctrl rtc_clkctrl@ (Dclock@760 ti,omap4-cmvpe_cm@`  ` clock@0 ti,clkctrl vpe_clkctrl@ Dtarget-module@8000ti,sysc-omap4ti,sysc@