8( NH@phytec,rk3288-pcm-947phytec,rk3288-phycore-somrockchip,rk3288&7Phytec RK3288 PCM-947aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/i2c@ff140000/rtc@68/i2c@ff650000/pmic@1carm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12!%,@OVrpcpu@501cpuarm,cortex-a12!%,@OVrpcpu@502cpuarm,cortex-a12!%,@OVrpcpu@503cpuarm,cortex-a12!%,@OVrpopp-table-0operating-points-v2xpopp-126000000 @opp-216000000  opp-312000000 opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJ opp-1608000000_"preserved-memorydma-unusable@fe000000!oscillator fixed-clockn6xin24mp timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer!  H Oa  pclktimerdisplay-subsystemrockchip,display-subsystem' mmc@ff0c0000rockchip,rk3288-dw-mshc-р ODrvbiuciuciu-driveciu-sample; ! @%FresetRokayYcudefault mmc@ff0d0000rockchip,rk3288-dw-mshc-р OEswbiuciuciu-driveciu-sample; !! @%Freset Rdisabledmmc@ff0e0000rockchip,rk3288-dw-mshc-р OFtxbiuciuciu-driveciu-sample; "!@%Freset Rdisabledmmc@ff0f0000rockchip,rk3288-dw-mshc-р OGuybiuciuciu-driveciu-sample; #!@%FresetRokayYc defaultsaradc@ff100000rockchip,saradc! $OI[saradcapb_pclk%W Fsaradc-apbRokay)spi@ff110000(rockchip,rk3288-spirockchip,rk3066-spiOARspiclkapb_pclk5  :txrx ,default! Rdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spiOBSspiclkapb_pclk5 :txrx -default !! Rdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spiOCTspiclkapb_pclk5:txrx .default"#$%!Rokayflash@0 micron,n25q128a13jedec,spi-nor!DVRokayi2c@ff140000rockchip,rk3288-i2c! >i2cOMdefault&Rokaytouchscreen@44 st,stmpe811!Dadc@64maxim,max1037!drtc@68rv4162!hdefault'&( i2c@ff150000rockchip,rk3288-i2c! ?i2cOOdefault)Rokayeeprom@51 atmel,24c32!Qe i2c@ff160000rockchip,rk3288-i2c! @i2cOPdefault*Rokayleddimmer@62 nxp,pca9533!bled1 nred:user1tnoneled2 ngreen:user2tnoneled3 nblue:user3tnoneled4 nred:user4tnonei2c@ff170000rockchip,rk3288-i2c! Ai2cOQdefault+Rokayptserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart! 7OMUbaudclkapb_pclk5:txrxdefault ,-.Rokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart! 8ONVbaudclkapb_pclk5:txrxdefault/ Rdisabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart!i 9OOWbaudclkapb_pclkdefault0Rokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart! :OPXbaudclkapb_pclk5:txrxdefault1 Rdisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart! ;OQYbaudclkapb_pclk5  :txrxdefault2 Rdisableddma-controller@ff250000arm,pl330arm,primecell!%@O apb_pclkpthermal-zonesreserve-thermal3cpu-thermald3tripscpu_alert0ppassivep4cpu_alert1$passivep5cpu_crit_ criticalcooling-mapsmap0)40.map1)50.gpu-thermald3tripsgpu_alert0ppassivep6gpu_crit_ criticalcooling-mapsmap0)6 .7tsadc@ff280000rockchip,rk3288-tsadc!( %OHZtsadcapb_pclk% Ftsadc-apbinitdefaultsleep8=9G8Qg:tsRokayp3ethernet@ff290000rockchip,rk3288-gmac!)macirqeth_wake_irqg:8Ofgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac%B FstmmacethRokay;inputdefault <=>? @ rgmii-id  6'B@ KA[dmdio0snps,dwmac-mdioethernet-phy@0ethernet-phy-ieee802.3-c22!&Amp?usb@ff500000 generic-ehci!P OBusbRokayusb@ff520000 generic-ohci!R )OBusb Rdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2!T OotghostC usb2-phyRokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2!X Ootgotg @@ D usb2-phyRokayusb@ff5c0000 generic-ehci!\ O Rdisableddma-controller@ff600000arm,pl330arm,primecell!`@O apb_pclk Rdisabledi2c@ff650000rockchip,rk3288-i2c!e <i2cOLdefaultERokaypmic@1crockchip,rk818!&FdefaultG+LZHfHrH~HIHJJregulatorsDCDC_REG1vdd_log !regulator-state-mem9DCDC_REG2vdd_gpu 5!regulator-state-memRjB@DCDC_REG3vcc_ddrregulator-state-memRDCDC_REG4 vdd_3v3_io 2Z!2Zpregulator-state-memRj2ZDCDC_BOOSTvdd_sys LK@!LK@pHregulator-state-memRjLK@SWITCH_REGvdd_sdpregulator-state-mem9LDO_REG2 vdd_eth_2v5 &%!&%p@regulator-state-memRj&%LDO_REG3vdd_1v0 B@!B@regulator-state-memRjB@LDO_REG4vdd_1v8_lcd_ldo w@!w@regulator-state-memRjw@LDO_REG6 vdd_1v0_lcd B@!B@regulator-state-memRjB@LDO_REG7 vdd_1v8_ldo w@!w@pregulator-state-mem9jw@LDO_REG9 vdd_io_sd w@!2Zpregulator-state-mem9eeprom@50 atmel,24c32!Pe regulator@60 fcs,fan53555!`,vdd_cpu 5!@Hi2c@ff660000rockchip,rk3288-i2c!f =i2cONdefaultK Rdisabledpwm@ff680000rockchip,rk3288-pwm!hdefaultLO_ Rdisabledpwm@ff680010rockchip,rk3288-pwm!hdefaultMO_Rokaypwm@ff680020rockchip,rk3288-pwm!h defaultNO_ Rdisabledpwm@ff680030rockchip,rk3288-pwm!h0defaultOO_ Rdisabledsram@ff700000 mmio-sram!ppsmp-sram@0rockchip,rk3066-smp-sram!sram@ff720000#rockchip,rk3288-pmu-srammmio-sram!rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd!sppower-controller!rockchip,rk3288-power-controllerpapower-domain@9! Ochgfdehilkj$PQRSTUVWXpower-domain@11! OopYZpower-domain@12! O[power-domain@13! O\]reboot-modesyscon-reboot-mode RBRB&RB 6RBsyscon@ff740000rockchip,rk3288-sgrfsyscon!tclock-controller@ff760000rockchip,rk3288-cru!vO xin24mg:BHjk$O#gׄeрxhрxhpsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd!wp:edp-phyrockchip,rk3288-dp-phyOh24md Rdisabledpqio-domains"rockchip,rk3288-io-voltage-domainRokayo}Jusbphyrockchip,rk3288-usb-phyRokayusb-phy@320d! O]phyclk% Fphy-resetpDusb-phy@334d!4O^phyclk% Fphy-resetpBusb-phy@348d!HO_phyclk% Fphy-resetpCwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt!Op ORokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif!OT mclkhclk5^:tx 6default_g: Rdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s! 5ORi2s_clki2s_hclk5^^:txrxdefault`   Rdisabledcrypto@ff8a0000rockchip,rk3288-crypto!@ 0 O}aclkhclksclkapb_pclk% Fcrypto-rstiommu@ff900800rockchip,iommu!@ O aclkiface 7 Rdisablediommu@ff914000rockchip,iommu !@P O aclkiface 7 D Rdisabledrga@ff920000rockchip,rk3288-rga! Ojaclkhclksclk _a %ilm Fcoreaxiahbvop@ff930000rockchip,rk3288-vop ! Oaclk_vopdclk_vophclk_vop _a %def Faxiahbdclk mbRokayportp endpoint@0! tcpuendpoint@1! tdprendpoint@2! teplendpoint@3! tfpoiommu@ff930300rockchip,iommu! O aclkiface _a  7Rokaypbvop@ff940000rockchip,rk3288-vop ! Oaclk_vopdclk_vophclk_vop _a % Faxiahbdclk mgRokayportp endpoint@0! thpvendpoint@1! tipsendpoint@2! tjpmendpoint@3! tkppiommu@ff940300rockchip,iommu! O aclkiface _a  7Rokaypgdsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi!@ O~d refpclk _a g: Rdisabledportsport@0!endpoint@0! tlpeendpoint@1! tmpjport@1!lvds@ff96c000rockchip,rk3288-lvds!@Og pclk_lvdslcdcn _a g: Rdisabledportsport@0!endpoint@0! topfendpoint@1! tppkport@1!dp@ff970000rockchip,rk3288-dp!@ bh Oicdppclkqdp _a %oFdpg: Rdisabledportsport@0!endpoint@0! trpdendpoint@1! tspiport@1!hdmi@ff980000rockchip,rk3288-dw-hdmi! gOhmniahbisfrcec _a g:Rokay tportsport@0!endpoint@0! tupcendpoint@1! tvphport@1!video-codec@ff9a0000rockchip,rk3288-vpu!   vepuvdpuO aclkhclk mw _a iommu@ff9a0800rockchip,iommu! O aclkiface 7 _a pwvideo-codec@ff9c0000rockchip,rk3288-vdec!@  Oopaxiahbcabaccore opOׄ mx _a iommu@ff9c0440rockchip,iommu !@@@ oO aclkiface 7 _a pxgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760!$ jobmmugpuO,y@ _a  Rdisabledp7opp-table-1operating-points-v2pyopp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon! p\qos@ffaa0080rockchip,rk3288-qossyscon! p]qos@ffad0000rockchip,rk3288-qossyscon! pQqos@ffad0100rockchip,rk3288-qossyscon! pRqos@ffad0180rockchip,rk3288-qossyscon! pSqos@ffad0400rockchip,rk3288-qossyscon! pTqos@ffad0480rockchip,rk3288-qossyscon! pUqos@ffad0500rockchip,rk3288-qossyscon! pPqos@ffad0800rockchip,rk3288-qossyscon! pVqos@ffad0880rockchip,rk3288-qossyscon! pWqos@ffad0900rockchip,rk3288-qossyscon! pXqos@ffae0000rockchip,rk3288-qossyscon! p[qos@ffaf0000rockchip,rk3288-qossyscon! pYqos@ffaf0080rockchip,rk3288-qossyscon! pZdma-controller@ffb20000arm,pl330arm,primecell!@O apb_pclkp^efuse@ffb40000rockchip,rk3288-efuse! Oq pclk_efusecpu-id@7!cpu_leakage@17!interrupt-controller@ffc01000 arm,gic-400  @! @ `   ppinctrlrockchip,rk3288-pinctrlg:gpio@ff750000rockchip,gpio-bank!u QO@    pFgpio@ff780000rockchip,gpio-bank!x ROA    gpio@ff790000rockchip,gpio-bank!y SOB    pgpio@ff7a0000rockchip,gpio-bank!z TOC    gpio@ff7b0000rockchip,gpio-bank!{ UOD    pAgpio@ff7c0000rockchip,gpio-bank!| VOE    p(gpio@ff7d0000rockchip,gpio-bank!} WOF    gpio@ff7e0000rockchip,gpio-bank!~ XOG    pgpio@ff7f0000rockchip,gpio-bank! YOH    phdmihdmi-cec-c0 zhdmi-cec-c7 zhdmi-ddc zzhdmi-ddc-unwedge {zpcfg-output-low p{pcfg-pull-up p|pcfg-pull-down p}pcfg-pull-none pzpcfg-pull-none-12ma   p~suspendglobal-pwroff zddrio-pwroff zddr0-retention |ddr1-retention |edpedp-hpd  }i2c0i2c0-xfer zzpEi2c1i2c1-xfer zzp&i2c2i2c2-xfer  z zpKi2c3i2c3-xfer zzp)i2c4i2c4-xfer zzp*i2c5i2c5-xfer zzp+i2s0i2s0-bus` zzzzzzp`lcdclcdc-ctl@ zzzzpnsdmmcsdmmc-clk ~p sdmmc-cmd p sdmmc-cd |psdmmc-bus1 |sdmmc-bus4@ psdmmc-pwr  zsdio0sdio0-bus1 |sdio0-bus4@ ||||sdio0-cmd |sdio0-clk zsdio0-cd |sdio0-wp |sdio0-pwr |sdio0-bkpwr |sdio0-int |sdio1sdio1-bus1 |sdio1-bus4@ ||||sdio1-cd |sdio1-wp |sdio1-bkpwr |sdio1-int |sdio1-cmd |sdio1-clk zsdio1-pwr  |emmcemmc-clk ~pemmc-cmd ~pemmc-pwr  |pemmc-bus1 |emmc-bus4@ ||||emmc-bus8 ~~~~~~~~pspi0spi0-clk  |pspi0-cs0  |pspi0-tx |pspi0-rx |pspi0-cs1 |spi1spi1-clk  |pspi1-cs0  |p!spi1-rx |p spi1-tx |pspi2spi2-cs1 |spi2-clk |p"spi2-cs0 |p%spi2-rx |p$spi2-tx  |p#uart0uart0-xfer |zp,uart0-cts |p-uart0-rts zp.uart1uart1-xfer | zp/uart1-cts  |uart1-rts  zuart2uart2-xfer |zp0uart3uart3-xfer |zp1uart3-cts  |uart3-rts  zuart4uart4-xfer |zp2uart4-cts  |uart4-rts  ztsadcotp-pin zp8otp-out zp9pwm0pwm0-pin zpLpwm1pwm1-pin zpMpwm2pwm2-pin zpNpwm3pwm3-pin zpOgmacrgmii-pins zzzz~~~~zzz ~~zzp<rmii-pins zzzzzzzzzzphy-int |p>phy-rst p=spdifspdif-tx  zp_pcfg-output-high #pledsuser-led-pin ppmicpmic-int |pGpmic-sleep |pcfg-pull-up-drv-12ma   pbuttonsuser-button-pins ||prv4162i2c-rtc-int  |p'touchscreents-irq-pin zusb_hosthost0-vbus-drv  zphost1-vbus-drv zpusb_otgotg-vbus-drv  zpmemorymemory!external-gmac-clock fixed-clocksY@ ext_gmacp;user-leds gpio-ledsdefaultled-0 ngreen_led / theartbeat 5keepregulator-vdd-emmc-ioregulator-fixed vdd_emmc_io w@!w@pregulator-vdd-in-otg-outregulator-fixedvdd_in_otg_out LK@!LK@pIregulator-vdd-misc-1v8regulator-fixed vdd_misc_1v8 w@!w@pJuser-buttons gpio-keysdefaultbutton-0nhome Cf /Lbutton-1nmenu C /Lregulator-usb-host0regulator-fixed V default vcc_host0_5v LK@!LK@Iregulator-usb-host1regulator-fixed Vdefault vcc_host1_5v LK@!LK@Iregulator-usb-otgregulator-fixed V default vcc_otg_5v LK@!LK@I #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2rtc0rtc1interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclocksdynamic-power-coefficientphandleopp-sharedopp-hzopp-microvoltclock-latency-nsrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesspi-max-frequencym25p,fast-readpagesizelabellinux,default-triggerreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-handlephy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayti,rx-internal-delayti,tx-internal-delayti,fifo-depthenet-phy-lane-no-swapti,clk-output-selphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyboost-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvddio-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltfcs,suspend-voltage-selectorregulator-enable-ramp-delayregulator-ramp-delayvin-supply#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellssdcard-supplyflash0-supplyflash1-supplygpio1830-supplygpio30-supplybb-supplydvp-supplylcdc-supplywifi-supplyaudio-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highgpiosdefault-statelinux,code