8( *chipspark,popmetal-rk3288rockchip,rk3288&7PopMetal-RK3288aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500 cpuarm,cortex-a12"6ELrf qcpu@501 cpuarm,cortex-a12"6ELrf qcpu@502 cpuarm,cortex-a12"6ELrf qcpu@503 cpuarm,cortex-a12"6ELrf qopp-table-0operating-points-v2yqopp-126000000 @opp-216000000  opp-312000000 opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJ opp-1608000000_"preserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mq timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H Ea  pclktimerdisplay-subsystemrockchip,display-subsystem( mmc@ff0c0000rockchip,rk3288-dw-mshc.р EDrvbiuciuciu-driveciu-sample<  @GresetSokayZdvdefault mmc@ff0d0000rockchip,rk3288-dw-mshc.р EEswbiuciuciu-driveciu-sample< ! @Greset Sdisabledmmc@ff0e0000rockchip,rk3288-dw-mshc.р EFtxbiuciuciu-driveciu-sample< "@Greset Sdisabledmmc@ff0f0000rockchip,rk3288-dw-mshc.р EGuybiuciuciu-driveciu-sample< #@GresetSokayZd &defaultsaradc@ff100000rockchip,saradc $4EI[saradcapb_pclkW Gsaradc-apb Sdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spiEARspiclkapb_pclkF  Ktxrx ,default Sdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spiEBSspiclkapb_pclkF Ktxrx -default ! Sdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spiECTspiclkapb_pclkFKtxrx .default"#$% Sdisabledi2c@ff140000rockchip,rk3288-i2c >i2cEMdefault&Sokayak8963@dasahi-kasei,ak8975 &'default(U`l3g4200d@69st,l3g4200d-gyrokiU{mma8452@1d fsl,mma8452&'default)i2c@ff150000rockchip,rk3288-i2c ?i2cEOdefault*Sokayi2c@ff160000rockchip,rk3288-i2c @i2cEPdefault+Sokayi2c@ff170000rockchip,rk3288-i2c Ai2cEQdefault,Sokayqsserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7EMUbaudclkapb_pclkFKtxrxdefault-Sokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8ENVbaudclkapb_pclkFKtxrxdefault.Sokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9EOWbaudclkapb_pclkdefault/Sokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :EPXbaudclkapb_pclkFKtxrxdefault0Sokayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;EQYbaudclkapb_pclkF  Ktxrxdefault1Sokaydma-controller@ff250000arm,pl330arm,primecell%@E apb_pclkqthermal-zonesreserve-thermal2cpu-thermald2tripscpu_alert0ppassiveq3cpu_alert1$passiveq4cpu_crit_ criticalcooling-mapsmap0'30,map1'40,gpu-thermald2tripsgpu_alert0ppassiveq5gpu_crit_ criticalcooling-mapsmap0'5 ,6tsadc@ff280000rockchip,rk3288-tsadc( %EHZtsadcapb_pclk Gtsadc-apbinitdefaultsleep7;8E7Oe9rsSokayq2ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irqe98Efgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB GstmmacethSokay:rgmiiinput ; 'B@'7<default=N0Wusb@ff500000 generic-ehciP E`>eusb Sdisabledusb@ff520000 generic-ohciR )E`>eusb Sdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T Eotgohost`? eusb2-phyw Sdisabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X Eotgootg@@ `@ eusb2-phySokayusb@ff5c0000 generic-ehci\ E Sdisableddma-controller@ff600000arm,pl330arm,primecell`@E apb_pclk Sdisabledi2c@ff650000rockchip,rk3288-i2ce <i2cELdefaultASokaypmic@1brockchip,rk808&BdefaultCDxin32krk808-clkout2EEEEE)E5FAMZEg{regulatorsDCDC_REG1t qpvdd_armq regulator-state-memDCDC_REG2t Pvdd_gpuregulator-state-mem B@DCDC_REG3tvcc_ddrregulator-state-memDCDC_REG4t2Z2Zvcc_ioqregulator-state-mem 2ZLDO_REG1t2Z2Zvcc_lanq:regulator-state-mem 2ZLDO_REG2tw@2Z vccio_sdqregulator-state-memLDO_REG3tB@B@vdd_10regulator-state-mem B@LDO_REG4tw@w@ vcc18_lcdregulator-state-mem w@LDO_REG5tw@2Zldo5LDO_REG6tB@B@ vdd10_lcdregulator-state-mem B@LDO_REG7tw@w@vcc_18qFregulator-state-mem w@LDO_REG8t2Z2Zvcca_33qZregulator-state-mem 2ZSWITCH_REG1t vccio_wlq\regulator-state-memSWITCH_REG2tvcc_lcdregulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2cENdefaultGSokaypwm@ff680000rockchip,rk3288-pwmh&defaultHE_ Sdisabledpwm@ff680010rockchip,rk3288-pwmh&defaultIE_ Sdisabledpwm@ff680020rockchip,rk3288-pwmh &defaultJE_ Sdisabledpwm@ff680030rockchip,rk3288-pwmh0&defaultKE_ Sdisabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsqpower-controller!rockchip,rk3288-power-controller1q`power-domain@9 Echgfdehilkj$ELMNOPQRST1power-domain@11 EopEUV1power-domain@12 EEW1power-domain@13 EEXY1reboot-modesyscon-reboot-modeLSRB_RBmRB }RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvE xin24me9H'jk$#gׄeрxhрxhqsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwq9edp-phyrockchip,rk3288-dp-phyEh24m Sdisabledqpio-domains"rockchip,rk3288-io-voltage-domainSokayZ[:,\usbphyrockchip,rk3288-usb-phySokayusb-phy@320 E]phyclk Gphy-resetq@usb-phy@3344E^phyclk Gphy-resetq>usb-phy@348HE_phyclk Gphy-resetq?watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdtEp O Sdisabledsound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif8ET mclkhclkF]Ktx 6default^e9 Sdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s8 5ERi2s_clki2s_hclkF]]Ktxrxdefault_Id Sdisabledcrypto@ff8a0000rockchip,rk3288-crypto@ 0 E}aclkhclksclkapb_pclk Gcrypto-rstiommu@ff900800rockchip,iommu@ E aclkiface~ Sdisablediommu@ff914000rockchip,iommu @P E aclkiface~ Sdisabledrga@ff920000rockchip,rk3288-rga Ejaclkhclksclk` ilm Gcoreaxiahbvop@ff930000rockchip,rk3288-vop  Eaclk_vopdclk_vophclk_vop` def GaxiahbdclkaSokayportq endpoint@0bqtendpoint@1cqqendpoint@2dqkendpoint@3eqniommu@ff930300rockchip,iommu E aclkiface` ~Sokayqavop@ff940000rockchip,rk3288-vop  Eaclk_vopdclk_vophclk_vop`  GaxiahbdclkfSokayportq endpoint@0gquendpoint@1hqrendpoint@2iqlendpoint@3jqoiommu@ff940300rockchip,iommu E aclkiface` ~Sokayqfdsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ E~d refpclk` e9 Sdisabledportsport@0endpoint@0kqdendpoint@1lqiport@1lvds@ff96c000rockchip,rk3288-lvds@Eg pclk_lvdslcdcm` e9 Sdisabledportsport@0endpoint@0nqeendpoint@1oqjport@1dp@ff970000rockchip,rk3288-dp@ b'h7 Eicdppclk`pedp` oGdpe9 Sdisabledportsport@0endpoint@0qqcendpoint@1rqhport@1hdmi@ff980000rockchip,rk3288-dw-hdmi gEhmniahbisfrcec` e98Sokaysportsport@0endpoint@0tqbendpoint@1uqgport@1video-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpuE aclkhclkv` iommu@ff9a0800rockchip,iommu E aclkiface~` qvvideo-codec@ff9c0000rockchip,rk3288-vdec@  Eopaxiahbcabaccore 'opׄw` iommu@ff9c0440rockchip,iommu @@@ oE aclkiface~` qwgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpuE"x6`  Sdisabledq6opp-table-1operating-points-v2qxopp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon qXqos@ffaa0080rockchip,rk3288-qossyscon qYqos@ffad0000rockchip,rk3288-qossyscon qMqos@ffad0100rockchip,rk3288-qossyscon qNqos@ffad0180rockchip,rk3288-qossyscon qOqos@ffad0400rockchip,rk3288-qossyscon qPqos@ffad0480rockchip,rk3288-qossyscon qQqos@ffad0500rockchip,rk3288-qossyscon qLqos@ffad0800rockchip,rk3288-qossyscon qRqos@ffad0880rockchip,rk3288-qossyscon qSqos@ffad0900rockchip,rk3288-qossyscon qTqos@ffae0000rockchip,rk3288-qossyscon qWqos@ffaf0000rockchip,rk3288-qossyscon qUqos@ffaf0080rockchip,rk3288-qossyscon qVdma-controller@ffb20000arm,pl330arm,primecell@E apb_pclkq]efuse@ffb40000rockchip,rk3288-efuse Eq pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400@ @ `   qpinctrlrockchip,rk3288-pinctrle9gpio@ff750000rockchip,gpio-banku QE@ qBgpio@ff780000rockchip,gpio-bankx REA gpio@ff790000rockchip,gpio-banky SEB gpio@ff7a0000rockchip,gpio-bankz TEC gpio@ff7b0000rockchip,gpio-bank{ UED q;gpio@ff7c0000rockchip,gpio-bank| VEE gpio@ff7d0000rockchip,gpio-bank} WEF gpio@ff7e0000rockchip,gpio-bank~ XEG qgpio@ff7f0000rockchip,gpio-bank YEH q'hdmihdmi-cec-c0 yhdmi-cec-c7 yhdmi-ddc yyhdmi-ddc-unwedge zypcfg-output-low 'qzpcfg-pull-up 2q{pcfg-pull-down ?q|pcfg-pull-none Nqypcfg-pull-none-12ma N [ q}suspendglobal-pwroff yqDddrio-pwroff yddr0-retention {ddr1-retention {edpedp-hpd  |i2c0i2c0-xfer yyqAi2c1i2c1-xfer yyq&i2c2i2c2-xfer  y yqGi2c3i2c3-xfer yyq*i2c4i2c4-xfer yyq+i2c5i2c5-xfer yyq,i2s0i2s0-bus` yyyyyyq_lcdclcdc-ctl@ yyyyqmsdmmcsdmmc-clk yq sdmmc-cmd {qsdmmc-cd {qsdmmc-bus1 {sdmmc-bus4@ {{{{qsdmmc-pwr  yqsdio0sdio0-bus1 {sdio0-bus4@ {{{{sdio0-cmd {sdio0-clk ysdio0-cd {sdio0-wp {sdio0-pwr {sdio0-bkpwr {sdio0-int {sdio1sdio1-bus1 {sdio1-bus4@ {{{{sdio1-cd {sdio1-wp {sdio1-bkpwr {sdio1-int {sdio1-cmd {sdio1-clk ysdio1-pwr  {emmcemmc-clk yqemmc-cmd {qemmc-pwr  {qemmc-bus1 {emmc-bus4@ {{{{emmc-bus8 {{{{{{{{qspi0spi0-clk  {qspi0-cs0  {qspi0-tx {qspi0-rx {qspi0-cs1 {spi1spi1-clk  {qspi1-cs0  {q!spi1-rx {q spi1-tx {qspi2spi2-cs1 {spi2-clk {q"spi2-cs0 {q%spi2-rx {q$spi2-tx  {q#uart0uart0-xfer {yq-uart0-cts {uart0-rts yuart1uart1-xfer { yq.uart1-cts  {uart1-rts  yuart2uart2-xfer {yq/uart3uart3-xfer {yq0uart3-cts  {uart3-rts  yuart4uart4-xfer {yq1uart4-cts  {uart4-rts  ytsadcotp-pin  yq7otp-out  yq8pwm0pwm0-pin yqHpwm1pwm1-pin yqIpwm2pwm2-pin yqJpwm3pwm3-pin yqKgmacrgmii-pins yyyy}}}}yyy }}yyq=rmii-pins yyyyyyyyyyspdifspdif-tx  yq^ak8963comp-int {q(buttonspwrbtn {q~dvpdvp-pwr yqirir-int {qmma8452gsensor-int {q)pmicpmic-int {qCmemory@0 memoryexternal-gmac-clock fixed-clocksY@ ext_gmacq<gpio-keys gpio-keys jdefault~key-power uB {t GPIO Key Power  dir-receivergpio-ir-receiver uBdefaultregulator-flashregulator-fixed vcc_flashw@w@ qregulator-sdmmcregulator-fixed  defaultvcc_sd2Z2Z  qregulator-vsysregulator-fixedvcc_sysLK@LK@tqEregulator-vcc18-dvpregulator-fixed vcc18-dvpw@w@ q[regulator-vcc28-dvpregulator-fixed  Bdefault vcc28_dvp**t q #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclocksdynamic-power-coefficientcpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removable#io-channel-cellsdmasdma-namesvdd-supplyvid-supplyst,drdy-int-pinvddio-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthautorepeatgpioslinux,codelabellinux,input-typedebounce-intervalvin-supplystartup-delay-usenable-active-high