Ð þíÄ¡8·„( ·L£google,veyron-jaq-rev5google,veyron-jaq-rev4google,veyron-jaq-rev3google,veyron-jaq-rev2google,veyron-jaq-rev1google,veyron-jaqgoogle,veyronrockchip,rk3288& 7Google Jaqaliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000‚/i2c@ff140000‡/i2c@ff660000Œ/i2c@ff150000‘/i2c@ff160000–/i2c@ff170000›/serial@ff180000£/serial@ff190000«/serial@ff690000³/serial@ff1b0000»/serial@ff1c0000Ã/spi@ff110000È/spi@ff120000Í/spi@ff130000Ò/mmc@ff0f0000×/mmc@ff0c0000Ü/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0â—˜™šícpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'+2FU\rv ‚cpu@501cpuarm,cortex-a12'+2FU\r‚cpu@502cpuarm,cortex-a12'+2FU\r‚cpu@503cpuarm,cortex-a12'+2FU\r‚opp-table-0operating-points-v2Š‚opp-126000000•‚›€œ » ªœ@opp-216000000• ßæœ » opp-408000000•Q–œ » opp-600000000•#ÃFœ » opp-696000000•)|œ~ðopp-816000000•0£,œB@opp-1008000000•<Üœopp-1200000000•G†ŒœÈàopp-1416000000•TfrœO€opp-1512000000•ZJœÐopp-1608000000•_Ø"œÖ opp-1704000000•eúœ™popp-1800000000•kIÒœ\Àreserved-memory»dma-unusable@fe000000'þoscillator fixed-clockÂn6Òxin24må‚ timerarm,armv7-timerò0â   Ân6timer@ff810000rockchip,rk3288-timer'ÿ  âH Ua  -pclktimerdisplay-subsystemrockchip,display-subsystem9 mmc@ff0c0000rockchip,rk3288-dw-mshc?ðÑ€ UÈDrv-biuciuciu-driveciu-sampleM â 'ÿ @+€Xresetdokayku‡˜È ª ³ZÑÞëø*default8mmc@ff0d0000rockchip,rk3288-dw-mshc?ðÑ€ UÉEsw-biuciuciu-driveciu-sampleM â!'ÿ @+Xresetdokayk‡BOep*default 8ÑÞëøbtmrvl@2marvell,sd8897-bt'&â~ *default8mmc@ff0e0000rockchip,rk3288-dw-mshc?ðÑ€ UÊFtx-biuciuciu-driveciu-sampleM â"'ÿ@+‚Xreset ddisabledmmc@ff0f0000rockchip,rk3288-dw-mshc?ðÑ€ UËGuy-biuciuciu-driveciu-sampleM â#'ÿ@+ƒXresetdokayku³ž‘ep*default 8 saradc@ff100000rockchip,saradc'ÿ â$ UI[-saradcapb_pclk+W Xsaradc-apb ddisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spiUAR-spiclkapb_pclk²! ! ·txrx â,*default8"#$%'ÿdokayec@0google,cros-ec-spi'Á& â*default8&Þ-ÆÀi2c-tunnelgoogle,cros-ec-i2c-tunnelðsbs-battery@bsbs,sbs-battery' keyboard-controllergoogle,cros-ec-keyb+; NDh;<=>?@A B CD}0Y1 d"#(  \V |})  Ž + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spiUBS-spiclkapb_pclk²! !·txrx â-*default8'()*'ÿ ddisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spiUCT-spiclkapb_pclk²!!·txrx â.*default8+,-.'ÿdokayu flash@0jedec,spi-norÞúð€'i2c@ff140000rockchip,rk3288-i2c'ÿ â>-i2cUM*default8/dokay€ˆ2 dtpm@20infineon,slb9645tt' ·i2c@ff150000rockchip,rk3288-i2c'ÿ â?-i2cUO*default80 ddisabledi2c@ff160000rockchip,rk3288-i2c'ÿ â@-i2cUP*default81dokay€ˆ2 ,ts3a227e@3b ti,ts3a227e';&2â*default83Ï‚¢trackpad@15elan,ekth3000'& â*default84Ú5åi2c@ff170000rockchip,rk3288-i2c'ÿ âA-i2cUQ*default86 ddisabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart'ÿ â7óýUMU-baudclkapb_pclk²!!·txrx*default 8789dokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart'ÿ â8óýUNV-baudclkapb_pclk²!!·txrx*default8:dokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart'ÿi â9óýUOW-baudclkapb_pclk*default8;dokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart'ÿ â:óýUPX-baudclkapb_pclk²!!·txrx*default8< ddisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart'ÿ â;óýUQY-baudclkapb_pclk²! ! ·txrx*default8= ddisableddma-controller@ff250000arm,pl330arm,primecell'ÿ%@â 0U -apb_pclk‚!thermal-zonesreserve-thermalGè]ˆk>cpu-thermalGd]ˆk>tripscpu_alert0{p‡Ð"passive‚?cpu_alert1{$ø‡Ð"passive‚@cpu_crit{† ‡Ð "criticalcooling-mapsmap0’?0—ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1’@0—ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿgpu-thermalGd]ˆk>tripsgpu_alert0{4‡Ð"passive‚Agpu_crit{† ‡Ð "criticalcooling-mapsmap0’A —Bÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3288-tsadc'ÿ( â%UHZ-tsadcapb_pclk+Ÿ Xtsadc-apb*initdefaultsleep8C¦D°CºÐEÝèHdokayô ‚>ethernet@ff290000rockchip,rk3288-gmac'ÿ)â&macirqeth_wake_irqÐE8U—fgc˜Ä]M-stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac+B Xstmmaceth ddisabledusb@ff500000 generic-ehci'ÿP âUÂ6F;usbdokayEusb@ff520000 generic-ohci'ÿR â)UÂ6F;usb ddisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2'ÿT âUÃ-otg[host6G ;usb2-phycdokayzusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2'ÿX âUÁ-otg[host‘£²€€@@ 6H ;usb2-phydokayÁzÑHzusb@ff5c0000 generic-ehci'ÿ\ âUÄ ddisableddma-controller@ff600000arm,pl330arm,primecell'ÿ`@â 0UÁ -apb_pclk ddisabledi2c@ff650000rockchip,rk3288-i2c'ÿe â<-i2cUL*default8Idokay€ˆ2 dpmic@1brockchip,rk808'Òxin32kwifibt_32kin&2â*default 8JKLèåå !-9MEQ]j5w„MM ‚—regulatorsDCDC_REG1§vdd_arm¶ÊÜ q°ô  q‚ regulator-state-mem!DCDC_REG2§vdd_gpu¶ÊÜ 5ôÐ q‚„regulator-state-mem!DCDC_REG3 §vcc135_ddr¶Êregulator-state-mem:DCDC_REG4§vcc_18¶ÊÜw@ôw@‚regulator-state-mem:Rw@LDO_REG1 §vcc33_io¶ÊÜ2Z ô2Z ‚5regulator-state-mem:R2Z LDO_REG3§vdd_10¶ÊÜB@ôB@regulator-state-mem:RB@LDO_REG7§vdd10_lcd_pwren_h¶ÊÜ&% ô&% regulator-state-mem!SWITCH_REG1 §vcc33_lcd¶Ê‚cregulator-state-mem!LDO_REG6 §vcc18_codec¶ÊÜw@ôw@‚dregulator-state-mem!LDO_REG4 §vccio_sdÜw@ô2Z ‚regulator-state-mem!LDO_REG5 §vcc33_sdÜ2Z ô2Z ‚regulator-state-mem!LDO_REG8 §vcc33_ccd¶ÊÜ2Z ô2Z regulator-state-mem!LDO_REG2§mic_vcc¶ÊÜw@ôw@regulator-state-mem!i2c@ff660000rockchip,rk3288-i2c'ÿf â=-i2cUN*default8Ndokay† ˆ2  max98090@10maxim,max98090'&Oâ-mclkUq*default8P‚¡pwm@ff680000rockchip,rk3288-pwm'ÿhn*default8QU_dokay‚¨pwm@ff680010rockchip,rk3288-pwm'ÿhn*default8RU_dokay‚pwm@ff680020rockchip,rk3288-pwm'ÿh n*default8SU_ ddisabledpwm@ff680030rockchip,rk3288-pwm'ÿh0n*default8TU_ ddisabledsram@ff700000 mmio-sram'ÿp€»ÿp€smp-sram@0rockchip,rk3066-smp-sram'sram@ff720000#rockchip,rk3288-pmu-srammmio-sram'ÿrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd'ÿs‚power-controller!rockchip,rk3288-power-controllery‚hpower-domain@9' ÈUÊÍÈÌÅÆ¾¿ÔÕÖÙÑÒchgfdehilkj$UVWXYZ[\]ypower-domain@11' UÏop^_ypower-domain@12' UÐÜ`ypower-domain@13' UÀabyreboot-modesyscon-reboot-mode””›RBçRBõRBà ÅRBÃsyscon@ff740000rockchip,rk3288-sgrfsyscon'ÿtclock-controller@ff760000rockchip,rk3288-cru'ÿvU -xin24mÐEåÑHÁÑÝjÒÞk$Þ#g¸€ׄÍeá£ðÑ€xhÀá£ðÑ€xhÀ‚syscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd'ÿw‚Eedp-phyrockchip,rk3288-dp-phyUh-24módokay‚xio-domains"rockchip,rk3288-io-voltage-domaindokayþ5   !5 15 ?c K Wd dusbphyrockchip,rk3288-usb-phydokayusb-phy@320ó' U]-phyclkå+… Xphy-reset‚Husb-phy@334ó'4U^-phyclkå+ˆ Xphy-reset‚Fusb-phy@348ó'HU_-phyclkå+‹ Xphy-reset‚Gwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt'ÿ€Up âOdokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif'ÿ‹ rUTÐ -mclkhclk²e·tx â6*default8fÐE ddisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s'ÿ‰ r â5URÎ-i2s_clki2s_hclk²ee·txrx*default8g ƒ ždokay‚ crypto@ff8a0000rockchip,rk3288-crypto'ÿŠ@ â0 UÇÍ}Á-aclkhclksclkapb_pclk+® Xcrypto-rstiommu@ff900800rockchip,iommu'ÿ@ âUÊÔ -aclkiface ¸ ddisablediommu@ff914000rockchip,iommu 'ÿ‘@ÿ‘P âUÍÕ -aclkiface ¸ Å ddisabledrga@ff920000rockchip,rk3288-rga'ÿ’€ âUÈÖj-aclkhclksclk àh +ilm Xcoreaxiahbvop@ff930000rockchip,rk3288-vop 'ÿ“œÿ“ âUžÑ-aclk_vopdclk_vophclk_vop àh +def Xaxiahbdclk îidokayport‚ endpoint@0' õj‚endpoint@1' õk‚zendpoint@2' õl‚sendpoint@3' õm‚viommu@ff930300rockchip,iommu'ÿ“ âUÅÑ -aclkiface àh  ¸dokay‚ivop@ff940000rockchip,rk3288-vop 'ÿ”œÿ” âUÆ¿Ò-aclk_vopdclk_vophclk_vop àh +°±² Xaxiahbdclk îndokayport‚ endpoint@0' õo‚€endpoint@1' õp‚{endpoint@2' õq‚tendpoint@3' õr‚wiommu@ff940300rockchip,iommu'ÿ” âUÆÒ -aclkiface àh  ¸dokay‚ndsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi'ÿ–@ âU~d -refpclk àh ÐE ddisabledportsport@0'endpoint@0' õs‚lendpoint@1' õt‚qport@1'lvds@ff96c000rockchip,rk3288-lvds'ÿ–À@Ug -pclk_lvds*lcdc8u àh ÐE ddisabledportsport@0'endpoint@0' õv‚mendpoint@1' õw‚rport@1'dp@ff970000rockchip,rk3288-dp'ÿ—@ âbÁhÑ Uic-dppclk6x;dp àh +oXdpÐEdokay*default8yportsport@0'endpoint@0' õz‚kendpoint@1' õ{‚pport@1'endpoint@0' õ|‚¬hdmi@ff980000rockchip,rk3288-dw-hdmi'ÿ˜ý âgUhmn-iahbisfrcec àh ÐE rdokay*defaultunwedge8}¦~‚£portsport@0'endpoint@0' õ‚jendpoint@1' õ€‚oport@1'video-codec@ff9a0000rockchip,rk3288-vpu'ÿšâ   &vepuvdpuUÐÜ -aclkhclk î àh iommu@ff9a0800rockchip,iommu'ÿš â UÐÜ -aclkiface ¸ àh ‚video-codec@ff9c0000rockchip,rk3288-vdec'ÿœ@ â  UÏÛop-axiahbcabaccore ÁÏÛopÞׄõáá£á£ î‚ àh iommu@ff9c0440rockchip,iommu 'ÿœ@@ÿœ€@ âoUÏÛ -aclkiface ¸ àh ‚‚gpu@ffa30000#rockchip,rk3288-maliarm,mali-t760'ÿ£$â &jobmmugpuUÀ2ƒF àh dokay „‚Bopp-table-1operating-points-v2‚ƒopp-100000000•õáœ~ðopp-200000000• ëœ~ðopp-300000000•ᣜB@opp-400000000•ׄœÈàopp-600000000•#ÃFœÐqos@ffaa0000rockchip,rk3288-qossyscon'ÿª ‚aqos@ffaa0080rockchip,rk3288-qossyscon'ÿª€ ‚bqos@ffad0000rockchip,rk3288-qossyscon'ÿ­ ‚Vqos@ffad0100rockchip,rk3288-qossyscon'ÿ­ ‚Wqos@ffad0180rockchip,rk3288-qossyscon'ÿ­€ ‚Xqos@ffad0400rockchip,rk3288-qossyscon'ÿ­ ‚Yqos@ffad0480rockchip,rk3288-qossyscon'ÿ­€ ‚Zqos@ffad0500rockchip,rk3288-qossyscon'ÿ­ ‚Uqos@ffad0800rockchip,rk3288-qossyscon'ÿ­ ‚[qos@ffad0880rockchip,rk3288-qossyscon'ÿ­€ ‚\qos@ffad0900rockchip,rk3288-qossyscon'ÿ­ ‚]qos@ffae0000rockchip,rk3288-qossyscon'ÿ® ‚`qos@ffaf0000rockchip,rk3288-qossyscon'ÿ¯ ‚^qos@ffaf0080rockchip,rk3288-qossyscon'ÿ¯€ ‚_dma-controller@ffb20000arm,pl330arm,primecell'ÿ²@â 0UÁ -apb_pclk‚eefuse@ffb40000rockchip,rk3288-efuse'ÿ´ Uq -pclk_efusecpu-id@7'cpu_leakage@17'interrupt-controller@ffc01000 arm,gic-400  &@'ÿÀÿÀ ÿÀ@ ÿÀ`  â ‚pinctrlrockchip,rk3288-pinctrlÐE»*defaultsleep8…†‡ˆ‰¦…†‡Š‹gpio@ff750000rockchip,gpio-bank'ÿu âQU@ 7 G  &ç SPMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INT‚2gpio@ff780000rockchip,gpio-bank'ÿx âRUA 7 G  &gpio@ff790000rockchip,gpio-bank'ÿy âSUB 7 G  &M SCONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_EN‚–gpio@ff7a0000rockchip,gpio-bank'ÿz âTUC 7 G  &‚ SFLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bank'ÿ{ âUUD 7 G  &³ SUART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKE‚gpio@ff7c0000rockchip,gpio-bank'ÿ| âVUE 7 G  &A SSPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_EN‚›gpio@ff7d0000rockchip,gpio-bank'ÿ} âWUF 7 G  &° SI2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HALS_INTINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMD‚Ogpio@ff7e0000rockchip,gpio-bank'ÿ~ âXUG 7 G  &â SLCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVSOKSDMMC_WPEDP_HPDDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXD‚ gpio@ff7f0000rockchip,gpio-bank'ÿ âYUH 7 G  &^ SRAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 cŒhdmi-cec-c7 cŒhdmi-ddc cŒŒ‚}hdmi-ddc-unwedge cŒ‚~vcc50-hdmi-en cŒ‚œpcfg-output-low q‚pcfg-pull-up |‚Žpcfg-pull-down ‰‚pcfg-pull-none ˜‚Œpcfg-pull-none-12ma ˜ ¥ ‚’suspendglobal-pwroff cŒ‚‡ddrio-pwroff cŒ‚†ddr0-retention cŽ‚…ddr1-retention cŽsuspend-l-wake c‚ˆsuspend-l-sleep c‚Šedpedp-hpd c ‚yi2c0i2c0-xfer cŒŒ‚Ii2c1i2c1-xfer cŒŒ‚/i2c2i2c2-xfer c Œ Œ‚Ni2c3i2c3-xfer cŒŒ‚0i2c4i2c4-xfer cŒŒ‚1i2c5i2c5-xfer cŒŒ‚6i2s0i2s0-bus` cŒŒŒŒŒŒ‚glcdclcdc-ctl@ cŒŒŒŒ‚usdmmcsdmmc-clk c‘‚sdmmc-cmd c‘‚sdmmc-cd cŽsdmmc-bus1 cŽsdmmc-bus4@ c‘‘‘‘‚sdmmc-cd-disabled cŒ‚sdmmc-cd-pin cŒ‚sdio0sdio0-bus1 cŽsdio0-bus4@ c‘‘‘‘‚sdio0-cmd c‘‚sdio0-clk c‘‚sdio0-cd cŽsdio0-wp cŽsdio0-pwr cŽsdio0-bkpwr cŽsdio0-int cŽwifienable-h cŒ‚˜bt-enable-l cŒbt-host-wake cbt-host-wake-l cŒ‚bt-dev-wake-sleep c‚‹bt-dev-wake-awake c‚‰bt-dev-wake cŒsdio1sdio1-bus1 cŽsdio1-bus4@ cŽŽŽŽsdio1-cd cŽsdio1-wp cŽsdio1-bkpwr cŽsdio1-int cŽsdio1-cmd cŽsdio1-clk cŒsdio1-pwr c Žemmcemmc-clk c‘‚emmc-cmd c‘‚emmc-pwr c Žemmc-bus1 cŽemmc-bus4@ cŽŽŽŽemmc-bus8€ c‘‘‘‘‘‘‘‘‚ emmc-reset c Œ‚•spi0spi0-clk c Ž‚"spi0-cs0 c Ž‚%spi0-tx cŽ‚#spi0-rx cŽ‚$spi0-cs1 cŽspi1spi1-clk c Ž‚'spi1-cs0 c Ž‚*spi1-rx cŽ‚)spi1-tx cŽ‚(spi2spi2-cs1 cŽspi2-clk cŽ‚+spi2-cs0 cŽ‚.spi2-rx cŽ‚-spi2-tx c Ž‚,uart0uart0-xfer cŽŒ‚7uart0-cts cŽ‚8uart0-rts cŒ‚9uart1uart1-xfer cŽ Œ‚:uart1-cts c Žuart1-rts c Œuart2uart2-xfer cŽŒ‚;uart3uart3-xfer cŽŒ‚<uart3-cts c Žuart3-rts c Œuart4uart4-xfer cŽŒ‚=uart4-cts c Žuart4-rts c Œtsadcotp-pin c Œ‚Cotp-out c Œ‚Dpwm0pwm0-pin cŒ‚Qpwm1pwm1-pin cŒ‚Rpwm2pwm2-pin cŒ‚Spwm3pwm3-pin cŒ‚Tgmacrgmii-pinsð cŒŒŒŒ’’’’ŒŒŒ ’’ŒŒrmii-pins  cŒŒŒŒŒŒŒŒŒŒspdifspdif-tx c Œ‚fpcfg-pull-none-drv-8ma ˜ ¥‚‘pcfg-pull-up-drv-8ma | ¥pcfg-output-high ´‚buttonspwr-key-l cŽ‚“ap-lid-int-l cŽ‚®pmicpmic-int-l cŽ‚Jdvs-1 c ‚Kdvs-2 c‚Lrebootap-warm-reset-h c Œ‚”recovery-switchrec-mode-l c Žtpmtpm-int-h cŒwrite-protectfw-wp-ap cŒcodechp-det cŽ‚Ÿint-codec c‚Pmic-det c Ž‚žheadsetts3a227e-int-l cŽ‚3backlightbl_pwr_en c Œ‚¤bl-en cŒ‚§lcdlcd-en cŒ‚¥avdd-1v8-disp-en c Œ‚¦chargerac-present-ap cŽ‚­cros-ecec-int cŒ‚&trackpadtrackpad-int cŽ‚4usb-hosthost1-pwr-en c Œ‚¯usbotg-pwren-h c Œ‚°buck-5vdrv-5v cŒ‚šchosen Àserial2:115200n8memorymemory'€power-button gpio-keys*default8“key-power ÌPower ­2 Òt Ýdågpio-restart gpio-restart ­2 *default8” ïÈemmc-pwrseqmmc-pwrseq-emmc8•*default ø– ‚sdio-pwrseqmmc-pwrseq-simpleU— -ext_clock*default8˜ ø‚regulator-vcc-5vregulator-fixed§vcc_5v¶ÊÜLK@ôLK@ ™  " *default8š‚Mregulator-vcc33-sysregulator-fixed §vcc33_sys¶ÊÜ2Z ô2Z  ™‚regulator-vcc50-hdmiregulator-fixed §vcc50_hdmi¶Ê M  "›*default8œregulator-vdd-logicpwm-regulator §vdd_logic 'Ê , 7{ K”¶ÊÜ~ðô™p  sound!rockchip,rockchip-audio-max98090*default8žŸ ^VEYRON-I2S m  …¡ šO °O  Ç¢ Þ£regulator-backlightregulator-fixed  "– *default8¤§backlight_regulator  ò:˜‚©regulator-panelregulator-fixed  " *default8¥§panel_regulator ‚ªvcc18-lcdregulator-fixed  "– *default8¦ §vcc18_lcd¶Ê backlightpwm-backlight ÿ ÷ ,€ E *default8§ '¨B@ R  g  x©‚«panelinnolux,n116bgedokay xª …«panel-timingÂl÷ V —ˆ ¤< ° º Ç Ï Ü  è  òportsportendpoint õ¬‚|gpio-charger gpio-charger ÿmains ­2*default8­lid-switch gpio-keys*default8®switch-lid ÌLid ­2å Ò  Ýregulator-vccsysregulator-fixed§vccsysʶ‚™regulator-vcc5-host1regulator-fixed  "2 *default8¯ §vcc5_host1¶Êregulator-vcc5v-otgregulator-fixed  "2 *default8° §vcc5_host2¶Ê #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemarvell,wakeup-pinmmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenhsync-activevactivevfront-porchvback-porchvsync-lenvsync-activecharger-typelinux,input-type