8( 4%amarula,vyasa-rk3288rockchip,rk3288&7Amarula Vyasa-RK3288aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500 cpuarm,cortex-a12"6ELrf qcpu@501 cpuarm,cortex-a12"6ELrf qcpu@502 cpuarm,cortex-a12"6ELrf qcpu@503 cpuarm,cortex-a12"6ELrf qopp-table-0operating-points-v2yqopp-126000000 @opp-216000000  opp-312000000 opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJ opp-1608000000_"preserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mq timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H Ea  pclktimerdisplay-subsystemrockchip,display-subsystem( mmc@ff0c0000rockchip,rk3288-dw-mshc.р EDrvbiuciuciu-driveciu-sample<  @GresetSokayZdvdefault mmc@ff0d0000rockchip,rk3288-dw-mshc.р EEswbiuciuciu-driveciu-sample< ! @Greset Sdisabledmmc@ff0e0000rockchip,rk3288-dw-mshc.р EFtxbiuciuciu-driveciu-sample< "@Greset Sdisabledmmc@ff0f0000rockchip,rk3288-dw-mshc.р EGuybiuciuciu-driveciu-sample< #@GresetSokayZddefaultsaradc@ff100000rockchip,saradc $EI[saradcapb_pclkW Gsaradc-apb Sdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spiEARspiclkapb_pclk  txrx ,default Sdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spiEBSspiclkapb_pclk txrx -default  Sdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spiECTspiclkapb_pclktxrx .default!"#$ Sdisabledi2c@ff140000rockchip,rk3288-i2c >i2cEMdefault% Sdisabledi2c@ff150000rockchip,rk3288-i2c ?i2cEOdefault& Sdisabledi2c@ff160000rockchip,rk3288-i2c @i2cEPdefault' Sdisabledi2c@ff170000rockchip,rk3288-i2c Ai2cEQdefault(Sokayqqserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7EMUbaudclkapb_pclktxrxdefault) Sdisabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8ENVbaudclkapb_pclktxrxdefault* Sdisabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9EOWbaudclkapb_pclkdefault+Sokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :EPXbaudclkapb_pclktxrxdefault, Sdisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;EQYbaudclkapb_pclk  txrxdefault- Sdisableddma-controller@ff250000arm,pl330arm,primecell%@&AE apb_pclkqthermal-zonesreserve-thermalXn|.cpu-thermalXdn|.tripscpu_alert0ppassiveq/cpu_alert1$passiveq0cpu_crit_ criticalcooling-mapsmap0/0map100gpu-thermalXdn|.tripsgpu_alert0ppassiveq1gpu_crit_ criticalcooling-mapsmap01 2tsadc@ff280000rockchip,rk3288-tsadc( %EHZtsadcapb_pclk Gtsadc-apbinitdefaultsleep3435sSokayq.ethernet@ff290000rockchip,rk3288-gmac)7macirqeth_wake_irq58Efgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB GstmmacethSokayGW6ninputdefault789:{;rgmii 'B@ <0usb@ff500000 generic-ehciP E=usbSokayusb@ff520000 generic-ohciR )E=usb Sdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T Eotghost> usb2-phySokaydefault?usb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X Eotgotg +@@ @ usb2-phySokay:Ausb@ff5c0000 generic-ehci\ E Sdisableddma-controller@ff600000arm,pl330arm,primecell`@&AE apb_pclk Sdisabledi2c@ff650000rockchip,rk3288-i2ce <i2cELdefaultBSokaypmic@1brockchip,rk808&Cxin32krk808-clkout2defaultDEFguFFFFFFFFFregulatorsDCDC_REG1vdd_arm q#p;Oq regulator-state-memaDCDC_REG2vdd_gpu P#;Oqwregulator-state-memzB@DCDC_REG3vcc_ddr;Oregulator-state-memzDCDC_REG4vcc_io 2Z#2Z;Oqregulator-state-memz2ZLDO_REG1vcc_tp 2Z#2Z;Oregulator-state-memz2ZLDO_REG2 vcc_codec 2Z#2Z;Oregulator-state-memaLDO_REG3vdd_10 B@#B@;Oregulator-state-memzB@LDO_REG4vcc_gps w@#w@;Oregulator-state-memzw@LDO_REG5 vccio_sd w@#2Z;Oqregulator-state-memz2ZLDO_REG6 vdd10_lcd B@#B@;Oregulator-state-memzB@LDO_REG7vcc_18 w@#w@;OqZregulator-state-memzw@LDO_REG8 vcc18_lcd w@#w@;Oregulator-state-memzw@SWITCH_REG1vcc_sd 2Z#2Z;Oqregulator-state-memzSWITCH_REG2vcc_lan 2Z#2Z;Oq;regulator-state-memzi2c@ff660000rockchip,rk3288-i2cf =i2cENdefaultG Sdisabledpwm@ff680000rockchip,rk3288-pwmhdefaultHE_ Sdisabledpwm@ff680010rockchip,rk3288-pwmhdefaultIE_ Sdisabledpwm@ff680020rockchip,rk3288-pwmh defaultJE_ Sdisabledpwm@ff680030rockchip,rk3288-pwmh0defaultKE_ Sdisabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsqpower-controller!rockchip,rk3288-power-controllerq^power-domain@9 Echgfdehilkj$LMNOPQRSTpower-domain@11 EopUVpower-domain@12 EWpower-domain@13 EXYreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvE xin24m5HGjk$#gׄeрxhрxhqsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwq5edp-phyrockchip,rk3288-dp-phyEh24m3 Sdisabledqnio-domains"rockchip,rk3288-io-voltage-domainSokay>ZKU`Zn;|Zusbphyrockchip,rk3288-usb-phySokayusb-phy@3203 E]phyclk Gphy-resetq@usb-phy@33434E^phyclk Gphy-resetq=usb-phy@3483HE_phyclk Gphy-resetq>watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdtEp OSokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifET mclkhclk[tx 6default\5 Sdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5ERi2s_clki2s_hclk[[txrxdefault] Sdisabledcrypto@ff8a0000rockchip,rk3288-crypto@ 0 E}aclkhclksclkapb_pclk Gcrypto-rstiommu@ff900800rockchip,iommu@ E aclkiface Sdisablediommu@ff914000rockchip,iommu @P E aclkiface Sdisabledrga@ff920000rockchip,rk3288-rga Ejaclkhclksclk.^ ilm Gcoreaxiahbvop@ff930000rockchip,rk3288-vop  Eaclk_vopdclk_vophclk_vop.^ def Gaxiahbdclk<_Sokayportq endpoint@0C`qrendpoint@1Caqoendpoint@2Cbqiendpoint@3Ccqliommu@ff930300rockchip,iommu E aclkiface.^ Sokayq_vop@ff940000rockchip,rk3288-vop  Eaclk_vopdclk_vophclk_vop.^  Gaxiahbdclk<dSokayportq endpoint@0Ceqsendpoint@1Cfqpendpoint@2Cgqjendpoint@3Chqmiommu@ff940300rockchip,iommu E aclkiface.^ Sokayqddsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ E~d refpclk.^ 5 Sdisabledportsport@0endpoint@0Ciqbendpoint@1Cjqgport@1lvds@ff96c000rockchip,rk3288-lvds@Eg pclk_lvdslcdck.^ 5 Sdisabledportsport@0endpoint@0Clqcendpoint@1Cmqhport@1dp@ff970000rockchip,rk3288-dp@ bGhW Eicdppclkndp.^ oGdp5 Sdisabledportsport@0endpoint@0Coqaendpoint@1Cpqfport@1hdmi@ff980000rockchip,rk3288-dw-hdmi gEhmniahbisfrcec.^ 5SokaySqportsport@0endpoint@0Crq`endpoint@1Csqeport@1video-codec@ff9a0000rockchip,rk3288-vpu   7vepuvdpuE aclkhclk<t.^ iommu@ff9a0800rockchip,iommu E aclkiface.^ qtvideo-codec@ff9c0000rockchip,rk3288-vdec@  Eopaxiahbcabaccore Gopׄ<u.^ iommu@ff9c0440rockchip,iommu @@@ oE aclkiface.^ qugpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ 7jobmmugpuE"v6.^ Sokay_wq2opp-table-1operating-points-v2qvopp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon qXqos@ffaa0080rockchip,rk3288-qossyscon qYqos@ffad0000rockchip,rk3288-qossyscon qMqos@ffad0100rockchip,rk3288-qossyscon qNqos@ffad0180rockchip,rk3288-qossyscon qOqos@ffad0400rockchip,rk3288-qossyscon qPqos@ffad0480rockchip,rk3288-qossyscon qQqos@ffad0500rockchip,rk3288-qossyscon qLqos@ffad0800rockchip,rk3288-qossyscon qRqos@ffad0880rockchip,rk3288-qossyscon qSqos@ffad0900rockchip,rk3288-qossyscon qTqos@ffae0000rockchip,rk3288-qossyscon qWqos@ffaf0000rockchip,rk3288-qossyscon qUqos@ffaf0080rockchip,rk3288-qossyscon qVdma-controller@ffb20000arm,pl330arm,primecell@&AE apb_pclkq[efuse@ffb40000rockchip,rk3288-efuse Eq pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400k@ @ `   qpinctrlrockchip,rk3288-pinctrl5gpio@ff750000rockchip,gpio-banku QE@kqCgpio@ff780000rockchip,gpio-bankx REAkgpio@ff790000rockchip,gpio-banky SEBkgpio@ff7a0000rockchip,gpio-bankz TECkgpio@ff7b0000rockchip,gpio-bank{ UEDkq<gpio@ff7c0000rockchip,gpio-bank| VEEkgpio@ff7d0000rockchip,gpio-bank} WEFkgpio@ff7e0000rockchip,gpio-bank~ XEGkqgpio@ff7f0000rockchip,gpio-bank YEHkqhdmihdmi-cec-c0xhdmi-cec-c7xhdmi-ddc xxhdmi-ddc-unwedge yxvcc50-hdmi-en xqpcfg-output-lowqypcfg-pull-upqzpcfg-pull-downq{pcfg-pull-noneqxpcfg-pull-none-12ma q|suspendglobal-pwroffxqEddrio-pwroffxddr0-retentionzddr1-retentionzedpedp-hpd {i2c0i2c0-xfer xxqBi2c1i2c1-xfer xxq%i2c2i2c2-xfer  x xqGi2c3i2c3-xfer xxq&i2c4i2c4-xfer xxq'i2c5i2c5-xfer xxq(i2s0i2s0-bus`xxxxxxq]lcdclcdc-ctl@xxxxqksdmmcsdmmc-clkxq sdmmc-cmdzqsdmmc-cdzqsdmmc-bus1zsdmmc-bus4@zzzzqsdio0sdio0-bus1zsdio0-bus4@zzzzsdio0-cmdzsdio0-clkxsdio0-cdzsdio0-wpzsdio0-pwrzsdio0-bkpwrzsdio0-intzsdio1sdio1-bus1zsdio1-bus4@zzzzsdio1-cdzsdio1-wpzsdio1-bkpwrzsdio1-intzsdio1-cmdzsdio1-clkxsdio1-pwr zemmcemmc-clkxqemmc-cmdzqemmc-pwr zqemmc-bus1zemmc-bus4@zzzzemmc-bus8zzzzzzzzqspi0spi0-clk zqspi0-cs0 zqspi0-txzqspi0-rxzqspi0-cs1zspi1spi1-clk zqspi1-cs0 zq spi1-rxzqspi1-txzqspi2spi2-cs1zspi2-clkzq!spi2-cs0zq$spi2-rxzq#spi2-tx zq"uart0uart0-xfer zxq)uart0-ctszuart0-rtsxuart1uart1-xfer z xq*uart1-cts zuart1-rts xuart2uart2-xfer zxq+uart3uart3-xfer zxq,uart3-cts zuart3-rts xuart4uart4-xfer zxq-uart4-cts zuart4-rts xtsadcotp-pin xq3otp-out xq4pwm0pwm0-pinxqHpwm1pwm1-pinxqIpwm2pwm2-pinxqJpwm3pwm3-pinxqKgmacrgmii-pinsxxxx||||xxx ||xxq7rmii-pinsxxxxxxxxxxphy-int zq:phy-pmebzq9phy-rst}q8spdifspdif-tx xq\pcfg-output-highq}pmicpmic-intzqDusb_hostphy-pwr-en }q?usb2-pwr-en xqusb_otgotg-vbus-drv xqchosen /serial@ff690000memory memoryregulator-dc12-vbatregulator-fixed dc12_vbat #;Oq~regulator-vboot-3v3regulator-fixed vboot_3v3 2Z#2Z;O ~regulator-vsysregulator-fixedvcc_sys 8u #8u ;O ~qFregulator-vboot-5vregulator-fixed vboot_sv LK@#LK@;O ~regulator-v3g-3v3regulator-fixedv3g_3v3 2Z#2Z;O ~regulator-vsus-5vregulator-fixedvsus_5v LK@#LK@;O qregulator-vcc50-hdmiregulator-fixed vcc50_hdmi !  default;O regulator-vusb1-5vregulator-fixed vusb1_5v ! C default LK@#LK@ qAregulator-vusb2-5vregulator-fixed vusb2_5v !  default LK@#LK@;O external-gmac-clock fixed-clocksY@ ext_gmacq6 #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclocksdynamic-power-coefficientcpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsdmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizevbus-supplyrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathvin-supplyenable-active-high