G8B$(A"beagle,beaglev-aheadthead,th1520 &BeagleV Aheadcpus ,-cpu@0thead,c910riscv?cpu Krv64imafdcUrv64iAdimafdcziccrsezicntrzicsrzifenceizihpmzfhxtheadvectory@@ riscv,sv39interrupt-controllerriscv,cpu-intc#cpu@1thead,c910riscv?cpu Krv64imafdcUrv64iAdimafdcziccrsezicntrzicsrzifenceizihpmzfhxtheadvectory@@ riscv,sv39interrupt-controllerriscv,cpu-intc#cpu@2thead,c910riscv?cpu Krv64imafdcUrv64iAdimafdcziccrsezicntrzicsrzifenceizihpmzfhxtheadvectory@@ riscv,sv39interrupt-controllerriscv,cpu-intc#cpu@3thead,c910riscv?cpu Krv64imafdcUrv64iAdimafdcziccrsezicntrzicsrzifenceizihpmzfhxtheadvectory@@ riscv,sv39interrupt-controllerriscv,cpu-intc#l2-cachecache@+7#pmu riscv,pmuE  a   Hz      !"#$%&'()*oscillator fixed-clockosc_24mn6#32k-oscillator fixed-clockosc_32kclock-73728000 fixed-clocke aonsys_clk#mem-clk fixed-clock gpu_mem_clk#stmmac-axi-config@ # aonthead,th1520-aonaon  gpu-clkgen#soc simple-bus- >Ninterrupt-controller@ffd8000000"thead,th1520-plicthead,c900-plic@U         i#timer@ffdc000000$thead,th1520-clintthead,c900-clint@Ureset-controller@ffe4040100thead,th1520-reset-vitspi@ffe700c000!thead,th1520-spisnps,dw-apb-ssi6 6  disabledserial@ffe7014000snps,dw-apb-uart@$ U 7baudclkapb_pclkokaydefault ethernet@ffe7060000#thead,th1520-gmacsnps,dwmac-3.70a  @ dwmacapbCmacirq 0 , stmmacethpclkapb  @$ @  disabledmdiosnps,dwmac-mdio ethernet@ffe7070000#thead,th1520-gmacsnps,dwmac-3.70a  0 dwmacapbBmacirq 0 2 stmmacethpclkapb  @$ @ okaydefault P  [rgmii-idmdiosnps,dwmac-mdio ethernet-phy@1- dp'P# mmc@ffe7080000thead,th1520-dwcmshc> +coreokay =mmc@ffe7090000thead,th1520-dwcmshc @ +coreokay =mmc@ffe70a0000thead,th1520-dwcmshc G +core disabledserial@ffe7f00000snps,dw-apb-uart% U 8baudclkapb_pclk disabledserial@ffe7f04000snps,dw-apb-uart@' U :baudclkapb_pclk disabledgpio@ffe7f34000snps,dw-apb-gpio@  ?busgpio-controller@0snps,dw-apb-gpio-port  :gpio@ffe7f38000snps,dw-apb-gpio  1busgpio-controller@0snps,dw-apb-gpio-port ;#pinctrl@ffe7f3c000thead,th1520-pinctrl -#gpio@ffec005000snps,dw-apb-gpioP  =busgpio-controller@0snps,dw-apb-gpio-port  8gpio@ffec006000snps,dw-apb-gpio`  >busgpio-controller@0snps,dw-apb-gpio-port 9pinctrl@ffec007000thead,th1520-pinctrlp /#gmac0-0# tx-pinsDGMAC0_TX_CLKGMAC0_TXENGMAC0_TXD0GMAC0_TXD1GMAC0_TXD2GMAC0_TXD3gmac0#0?Mcrx-pinsDGMAC0_RX_CLKGMAC0_RXDVGMAC0_RXD0GMAC0_RXD1GMAC0_RXD2GMAC0_RXD3gmac0#0mMcmdc-pins GMAC0_MDCgmac0#0 ?Mcmdio-pins GMAC0_MDIOgmac0#0 mzcphy-reset-pins GMAC0_COL#0?Mcphy-interrupt-pins GMAC0_CRSgpio0mzcuart0-0# tx-pins UART0_TXDuart#0?Mcrx-pins UART0_RXDuart0mzcserial@ffec010000snps,dw-apb-uart@& U 9baudclkapb_pclk disabledpwm@ffec01c000thead,th1520-pwm@ 3reset-controller@ffec02c000thead,th1520-reset-misctreset-controller@ffecc30000thead,th1520-reset-vptclock-controller@ffef010000thead,th1520-clk-ap# reset-controller@ffef014000thead,th1520-reset-ap@treset-controller@ffef040028thead,th1520-reset-dsp(tgpu@ffef4000000thead,th1520-gpuimg,img-bxm-4-64img,img-rogue@-f corememsysreset-controller@ffef528000thead,th1520-resetROt#clock-controller@ffef528050thead,th1520-clk-voRP #dma-controller@ffefc00000snps,axi-dma-1.01a  core-clkcfgr-clk okaytimer@ffefc32000snps,dw-apb-timer  timer disabledtimer@ffefc32014snps,dw-apb-timer  timer disabledtimer@ffefc32028snps,dw-apb-timer ( timer disabledtimer@ffefc3203csnps,dw-apb-timer < timer disabledserial@fff7f08000snps,dw-apb-uart@( U ;baudclkapb_pclk disabledserial@fff7f0c000snps,dw-apb-uart@) U <baudclkapb_pclk disabledtimer@ffffc33000snps,dw-apb-timer0 timer disabledtimer@ffffc33014snps,dw-apb-timer0 timer disabledtimer@ffffc33028snps,dw-apb-timer0( timer disabledtimer@ffffc3303csnps,dw-apb-timer0< timer disabledmailbox@ffffc38000thead,th1520-mbox@À`` @ *localremote-icu0remote-icu1remote-icu2  H I J K:clk-localclk-remote-icu0clk-remote-icu1clk-remote-icu2-##gpio@fffff41000snps,dw-apb-gpio gpio-controller@0snps,dw-apb-gpio-port Lreset-controller@fffff44000thead,th1520-reset-ao@ t reservedpinctrl@fffff4a000thead,th1520-pinctrl #led-0#led-pins5AUDIO_PA8AUDIO_PA9AUDIO_PA10AUDIO_PA11AUDIO_PA12#0?Mcpvt@fffff4e000moortec,mr75203@commontspdvm/gpio@fffff52000snps,dw-apb-gpio  gpio-controller@0snps,dw-apb-gpio-port 7#aliasesE/soc/ethernet@ffe7070000'O/soc/gpio@ffec005000/gpio-controller@0'U/soc/gpio@ffec006000/gpio-controller@0'[/soc/gpio@ffe7f34000/gpio-controller@0'a/soc/gpio@ffe7f38000/gpio-controller@0'g/soc/gpio@fffff52000/gpio-controller@0'm/soc/gpio@fffff41000/gpio-controller@0s/soc/serial@ffe7014000{/soc/serial@ffe7f00000/soc/serial@ffec010000/soc/serial@ffe7f04000/soc/serial@fff7f08000/soc/serial@fff7f0c000/soc/spi@ffe700c000chosenserial0:115200n8memory@0?memoryledsdefault gpio-ledsled-1 jled1led-2 j led2led-3 j led3led-4 j led4led-5 j led5 compatible#address-cells#size-cellsmodeltimebase-frequencydevice_typeriscv,isariscv,isa-baseriscv,isa-extensionsthead,vlenbregi-cache-block-sizei-cache-sizei-cache-setsd-cache-block-sized-cache-sized-cache-setsnext-level-cachemmu-typeinterrupt-controller#interrupt-cellsphandlecache-levelcache-unifiedriscv,event-to-mhpmcountersriscv,event-to-mhpmeventriscv,raw-event-to-mhpmcountersclock-output-names#clock-cellsclock-frequencysnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blenmboxesmbox-namesresetsreset-names#power-domain-cellsinterrupt-parentdma-noncoherentrangesinterrupts-extendedriscv,ndev#reset-cellsinterruptsclocksstatusclock-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0reg-namesinterrupt-namessnps,pblsnps,fixed-burstsnps,multicast-filter-binssnps,perfect-filter-entriessnps,axi-configphy-handlephy-modereset-gpiosreset-delay-usreset-post-delay-usbus-widthmax-frequencymmc-hs400-1_8vnon-removableno-sdiono-sdgpio-controller#gpio-cellsngpiosgpio-rangesthead,pad-grouppinsfunctionbias-disabledrive-strengthinput-disableinput-schmitt-disableslew-rateinput-enableinput-schmitt-enablebias-pull-up#pwm-cellspower-domains#dma-cellsdma-channelssnps,block-sizesnps,prioritysnps,dma-masterssnps,data-widthsnps,axi-max-burst-len#mbox-cells#thermal-sensor-cellsethernet0gpio0gpio1gpio2gpio3gpio4gpio5serial0serial1serial2serial3serial4serial5spi0stdout-pathcolorlabel