Ð þí ~8ì(’´Milianke MLKPAI-FS01$!milianke,mlkpai-fs01anlogic,dr1v90cpus,/¯cpu@0!nuclei,ux900riscv?@R_€lcpux@‹˜€ ¥riscv,sv39®²rv64iKÁimafdcbzbazbbzbczbkczbszicntrzicsrzifenceizihintpausezihpminterrupt-controller!riscv,cpu-intcÖçüsoc !simple-businterrupt-controller@680310004!anlogic,dr1v90-aclint-mswinuclei,ux900-aclint-mswi®h@timer@680350008!anlogic,dr1v90-aclint-mtimernuclei,ux900-aclint-mtimer®hP€ 0mtimecmpinterrupt-controller@6803d0004!anlogic,dr1v90-aclint-sswinuclei,ux900-aclint-sswi®hÐ0Öçinterrupt-controller@6c000000&!anlogic,dr1v90-plicsifive,plic-1.0.0®lÖç  :–üserial@f8400000%!anlogic,dr1v90-uartsnps,dw-apb-uart®ø@Eúð€UG`m wdisabledserial@f8401000%!anlogic,dr1v90-uartsnps,dw-apb-uart®ø@Eúð€UH`mwokayaliases~/soc/serial@f8401000chosen†serial0:115200n8memory@0lmemory®  #address-cells#size-cellsmodelcompatibletimebase-frequencyd-cache-block-sized-cache-setsd-cache-sizedevice_typei-cache-block-sizei-cache-setsi-cache-sizemmu-typeregriscv,isa-baseriscv,isa-extensions#interrupt-cellsinterrupt-controllerphandleinterrupt-parentrangesinterrupts-extendedreg-namesriscv,ndevclock-frequencyinterruptsreg-io-widthreg-shiftstatusserial0stdout-path