8(qh)sifive,hifive-premier-p550eswin,eic7700&SiFive HiFive Premier P550cpus,B@cpu@0sifive,p550riscv?cpuK@^kx @  riscv,sv48rv64i.imafdchsscofpmfzbazbbzicsrzifenceiinterrupt-controllerriscv,cpu-intc.Ccpu@1sifive,p550riscvK@^kx ?cpu@  riscv,sv48rv64i.imafdchsscofpmfzbazbbzicsrzifenceiinterrupt-controllerriscv,cpu-intc.Ccpu@2sifive,p550riscvK@^kx ?cpu@  riscv,sv48rv64i.imafdchsscofpmfzbazbbzicsrzifenceiinterrupt-controllerriscv,cpu-intc.C cpu@3sifive,p550riscvK@^kx ?cpu@  riscv,sv48rv64i.imafdchsscofpmfzbazbbzicsrzifenceiinterrupt-controllerriscv,cpu-intc.C l2-cache0cacheM@K`mWCl2-cache1cacheM@K`mWCl2-cache2cacheM@K`mWCl2-cache3cacheM@K`mWCpmu riscv,pmuHex  xx!!xH@  !@xxxxxxxxx x x x x xxxsoc simple-bustimer@2000000"eswin,eic7700-clintsifive,clint0@    cache-controller@2010000,eswin,eic7700-l3-cachesifive,ccache0cache@M@K`m@WCinterrupt-controller@c000000%eswin,eic7700-plicsifive,plic-1.0.0 .@    Cserial@50900000snps,dw-apb-uartPd )3okayserial@50910000snps,dw-apb-uartPe ) 3disabledserial@50920000snps,dw-apb-uartPf )3okayserial@50930000snps,dw-apb-uartPg ) 3disabledserial@50940000snps,dw-apb-uartPh ) 3disabledgpio@51600000snps,dw-apb-gpioQ`gpio-port@0snps,dw-apb-gpio-port./0123456789:;<=>?@ABCDEFGHIJKLMN:J Qgpio-port@1snps,dw-apb-gpio-port:J Qgpio-port@2snps,dw-apb-gpio-port:J Qgpio-port@3snps,dw-apb-gpio-port:JQaliases]/soc/serial@50900000choseneserial0:115200n8 #address-cells#size-cellscompatiblemodeltimebase-frequencydevice_typed-cache-block-sized-cache-setsd-cache-sized-tlb-setsd-tlb-sizei-cache-block-sizei-cache-setsi-cache-sizei-tlb-setsi-tlb-sizemmu-typenext-level-cacheregriscv,isa-baseriscv,isa-extensionstlb-split#interrupt-cellsinterrupt-controllerphandlecache-levelcache-unifiedriscv,event-to-mhpmcountersriscv,event-to-mhpmeventriscv,raw-event-to-mhpmcountersrangesinterrupt-parentdma-noncoherentinterrupts-extendedinterruptsriscv,ndevclock-frequencyreg-io-widthreg-shiftstatusgpio-controllerngpios#gpio-cellsserial0stdout-path