e8_(W_ OrangePi R2S!!xunlong,orangepi-r2sspacemit,k1cpus,n6cpu-mapcluster0core0?core1?core2?core3?cluster1core0?core1?core2?core3?cpu@0!spacemit,x60riscvCcpuOSrv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt]rv64ilimafdcbvzicbomzicbopzicbozzicntrzicondzicsrzifenceizihintpausezihpmzfhzbazbbzbczbszktzvfhzvktsscofpmfsstcsvinvalsvnapotsvpbmt@@@@@  .riscv,sv397interrupt-controller!riscv,cpu-intc?T7cpu@1!spacemit,x60riscvCcpuOSrv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt]rv64ilimafdcbvzicbomzicbopzicbozzicntrzicondzicsrzifenceizihintpausezihpmzfhzbazbbzbczbszktzvfhzvktsscofpmfsstcsvinvalsvnapotsvpbmt@@@@@  .riscv,sv397interrupt-controller!riscv,cpu-intc?T7cpu@2!spacemit,x60riscvCcpuOSrv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt]rv64ilimafdcbvzicbomzicbopzicbozzicntrzicondzicsrzifenceizihintpausezihpmzfhzbazbbzbczbszktzvfhzvktsscofpmfsstcsvinvalsvnapotsvpbmt@@@@@  .riscv,sv397interrupt-controller!riscv,cpu-intc?T7cpu@3!spacemit,x60riscvCcpuOSrv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt]rv64ilimafdcbvzicbomzicbopzicbozzicntrzicondzicsrzifenceizihintpausezihpmzfhzbazbbzbczbszktzvfhzvktsscofpmfsstcsvinvalsvnapotsvpbmt@@@@@  .riscv,sv397interrupt-controller!riscv,cpu-intc?T7cpu@4!spacemit,x60riscvCcpuOSrv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt]rv64ilimafdcbvzicbomzicbopzicbozzicntrzicondzicsrzifenceizihintpausezihpmzfhzbazbbzbczbszktzvfhzvktsscofpmfsstcsvinvalsvnapotsvpbmt@@@@@  .riscv,sv397interrupt-controller!riscv,cpu-intc?T7cpu@5!spacemit,x60riscvCcpuOSrv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt]rv64ilimafdcbvzicbomzicbopzicbozzicntrzicondzicsrzifenceizihintpausezihpmzfhzbazbbzbczbszktzvfhzvktsscofpmfsstcsvinvalsvnapotsvpbmt@@@@@  .riscv,sv397interrupt-controller!riscv,cpu-intc?T7cpu@6!spacemit,x60riscvCcpuOSrv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt]rv64ilimafdcbvzicbomzicbopzicbozzicntrzicondzicsrzifenceizihintpausezihpmzfhzbazbbzbczbszktzvfhzvktsscofpmfsstcsvinvalsvnapotsvpbmt@@@@@  .riscv,sv397interrupt-controller!riscv,cpu-intc?T7cpu@7!spacemit,x60riscvCcpuOSrv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt]rv64ilimafdcbvzicbomzicbopzicbozzicntrzicondzicsrzifenceizihintpausezihpmzfhzbazbbzbczbszktzvfhzvktsscofpmfsstcsvinvalsvnapotsvpbmt@@@@@  .riscv,sv397interrupt-controller!riscv,cpu-intc?T7l2-cache0!cache@eq7 l2-cache1!cache@eq7 clocksclock-1m !fixed-clockB@ vctcxo_1m7clock-24m !fixed-clockn6 vctcxo_24m7clock-3m !fixed-clock- vctcxo_3m7clock-32k !fixed-clock}osc_32k7soc !simple-bus system-controller@c0880000!spacemit,k1-syscon-rcpuO Hsystem-controller@c0888000!spacemit,k1-syscon-rcpu2O(i2c@d4010800!spacemit,k1-i2cO8 T funcbus $  disabledi2c@d4011000!spacemit,k1-i2cO8 ! U funcbus !%  disabledi2c@d4012000!spacemit,k1-i2cO 8 " V funcbus "&  disabledi2c@d4012800!spacemit,k1-i2cO(8 # W funcbus #(  disabledi2c@d4013800!spacemit,k1-i2cO88 $ X funcbus $)  disabledphy@c0a30000!spacemit,k1-usb2-phyO   disabled7"phy@c0b10000!spacemit,k1-combo-phyO   refclkdbimstrslv     phydbimstrslv'   disabled7#phy@c0c10000!spacemit,k1-pcie-phyOrefclk phy  disabledphy@c0d10000!spacemit,k1-pcie-phyOrefclk "phy  disabledsystem-controller@d4015000!spacemit,k1-syscon-apbcOP#oscvctcxo_1mvctcxo_3mvctcxo_24m7 i2c@d4018800!spacemit,k1-i2cO8 % Y funcbus %F  disabledgpio@d4019000!spacemit,k1-gpioO = corebus5E: ?TPQ  @ ` 7pwm@d401a000#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d401a400#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d401a800#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d401ac00#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d401b000#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d401b400#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d401b800#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d401bc00#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledi2c@d401d000!spacemit,k1-i2cO8 & Z funcbus &  disabledi2c@d401d800!spacemit,k1-i2cO8 ' [ funcbus '  disabledpinctrl@d401e000!spacemit,k1-pinctrlO * ^ funcbush 7gmac0-cfg7gmac0-pins@v     -}gmac1-cfg7!gmac1-pins@v !"#$%&'()*+.}i2c2-0-cfgi2c2-0-pinsvTUi2c8-cfgi2c8-0-pinsv]^qspi-cfgqspi-pinsvbcdef qspi-cs1-pinsvg} uart0-2-cfg7uart0-2-pinsvDE} pcie0-3-cfgpcie0-3-pins v675}pcie1-3-cfgpcie1-3-pins v;<=}pcie2-4-cfgpcie2-4-pins v>pu}pwm14-1-cfgpwm14-1-pinsv,} pwm@d4020000#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d4020400#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d4020800#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d4020c00#!spacemit,k1-pwmmarvell,pxa910-pwmO ]    disabledpwm@d4021000#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d4021400#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d4021800#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d4021c00#!spacemit,k1-pwmmarvell,pxa910-pwmO]    disabledpwm@d4022000#!spacemit,k1-pwmmarvell,pxa910-pwmO ]    disabledpwm@d4022400#!spacemit,k1-pwmmarvell,pxa910-pwmO$]    disabledpwm@d4022800#!spacemit,k1-pwmmarvell,pxa910-pwmO(]    disabledpwm@d4022c00#!spacemit,k1-pwmmarvell,pxa910-pwmO,]    disabledsystem-controller@d4050000!spacemit,k1-syscon-mpmuO #oscvctcxo_1mvctcxo_3mvctcxo_24m7clock-controller@d4090000!spacemit,k1-pllO system-controller@d4282800!spacemit,k1-syscon-apmuO((#oscvctcxo_1mvctcxo_3mvctcxo_24m7 interrupt-controller@e0000000#!spacemit,k1-plicsifive,plic-1.0.0O                ?T7 timer@e4000000 !spacemit,k1-clintsifive,clint0Osystem-controller@f0610000!spacemit,k1-syscon-apbc2Oa camera-bus !simple-bus0dma-bus !simple-bus0dma-controller@d4000000!spacemit,k1-pdmaO@  H  okayserial@d4017000#!spacemit,k1-uartintel,xscale-uartOp 4 corebus *! okay.default<serial@d4017100#!spacemit,k1-uartintel,xscale-uartOq  5 corebus ,!  disabledserial@d4017200#!spacemit,k1-uartintel,xscale-uartOr  6 corebus -!  disabledserial@d4017300#!spacemit,k1-uartintel,xscale-uartOs  7 corebus .!  disabledserial@d4017400#!spacemit,k1-uartintel,xscale-uartOt  8 corebus /!  disabledserial@d4017500#!spacemit,k1-uartintel,xscale-uartOu  9 corebus 0!  disabledserial@d4017600#!spacemit,k1-uartintel,xscale-uartOv  : corebus 1!  disabledserial@d4017700#!spacemit,k1-uartintel,xscale-uartOw  ; corebus 2!  disabledserial@d4017800#!spacemit,k1-uartintel,xscale-uartOx  < corebus 3!  disabledspi@d420c000!spacemit,k1-qspi O FQuadSPIQuadSPI-memory   qspi_enqspi u  disabledmultimedia-bus !simple-bus0network-bus !simple-bus0ethernet@cac80000!spacemit,k1-emacO  %P #'  okay\ grgmii-id.default<pmdio-bus'phy@1O7ethernet@cac81000!spacemit,k1-emacO  'P $'  okay\  grgmii-id.default<!pmdio-bus'phy@1O7 pcie-bus !simple-bus08Hpcie@ca000000Cpci!spacemit,k1-pcie@O0$ Fdbiatuconfiglink8 msi    dbimstrslv    dbimstrslv'   disabledpcie@0Cpci!pciclass,0604Opcie@ca400000Cpci!spacemit,k1-pcie@O@p$ Fdbiatuconfiglink8 msi !   dbimstrslv    dbimstrslv'   disabledpcie@0Cpci!pciclass,0604Opcie@ca800000Cpci!spacemit,k1-pcie@Oʀʰ$ FdbiatuconfiglinkT Bmsi $ " # dbimstrslv !   dbimstrslv'   disabledpcie@0Cpci!pciclass,0604Ostorage-bus !simple-bususb@c0a00000!spacemit,k1-dwc3O  usbdrd30} "#usb2-phyusb3-phyutmi   ahbvccphy%utmi:Rs  disabledmmc@d4281000!spacemit,k1-sdhciO( coreio  axisdhe okay!'aliases//soc/dma-bus/serial@d4017000#7/soc/network-bus/ethernet@cac80000#A/soc/network-bus/ethernet@cac81000chosenKserial0 #address-cells#size-cellsmodelcompatibletimebase-frequencycpudevice_typeregriscv,isariscv,isa-baseriscv,isa-extensionsriscv,cbom-block-sizeriscv,cbop-block-sizeriscv,cboz-block-sizei-cache-block-sizei-cache-sizei-cache-setsd-cache-block-sized-cache-sized-cache-setsnext-level-cachemmu-typephandleinterrupt-controller#interrupt-cellscache-levelcache-unifiedclock-frequencyclock-output-names#clock-cellsinterrupt-parentdma-noncoherentranges#reset-cellsclocksclock-namesresetsinterruptsstatus#phy-cellsreset-namesspacemit,apmugpio-controller#gpio-cellsgpio-ranges#pwm-cellsspacemit,apbcpinmuxbias-pull-updrive-strengthbias-disablepower-source#power-domain-cellsspacemit,mpmuinterrupts-extendedriscv,ndevdma-rangesdma-channels#dma-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0reg-namesmac-addressphy-handlephy-moderx-internal-delay-pstx-internal-delay-psreset-gpiosreset-delay-usreset-post-delay-usmotorcomm,auto-sleep-disabledinterrupt-namesbus-rangephysphy-namesphy_typereset-delaysnps,hsphy_interfacesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirksnps,dis_rxdet_inp3_quirkbus-widthmmc-hs400-1_8vmmc-hs400-enhanced-strobenon-removableno-sdno-sdioserial0ethernet0ethernet1stdout-path